From nobody Fri Sep 5 20:10:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723865; cv=none; d=zohomail.com; s=zohoarc; b=oAJvVIwdbkPDt7XkodudG9ifSxzpXIjDDI6B5H6luuF0vq2i5B359rSqkb7AM8ii0NKROVPcEt1qoPsVz1WJ95vIUSbkra/w0yRsNzfWT2NEggr/UUVw51qCSMctsa5xN87/tO/GuM7x6wGVed9bf1aILsGNuBm7Je+pIj13FFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723865; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=R+7G0jtF9M9vv/6Dni7ochFBNEKeKhy3HdYxp9ad8mw=; b=b+0tBnJXPfIsKu17vE+q55/xzvDx2a/arNSrp/Nz2Wj+oDFET1vH5ao6U7Xf7PTs3EhfHqYt/O9XJuU4zx9OYAmneD8xHEMDOFoYs7gIEFvkeDzAQpFPwsLc9foGpmDykaVAORY+/fk/9rchWTelfnV+tSYT7X+4Q7nUsijAVPk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752723865631949.7453635320854; Wed, 16 Jul 2025 20:44:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFWp-0005QV-KJ; Wed, 16 Jul 2025 23:43:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVJ-0003ig-F2; Wed, 16 Jul 2025 23:42:04 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVI-0000ZH-2y; Wed, 16 Jul 2025 23:41:53 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:59 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:59 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Date: Thu, 17 Jul 2025 11:40:41 +0800 Message-ID: <20250717034054.1903991-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723867549116600 Content-Type: text/plain; charset="utf-8" In the previous design, both the PSP and SSP were started together during SoC initialization. However, on real hardware, the SSP begins in a powered-= off state. The typical boot sequence involves the PSP powering up first, loading the SSP firmware binary into shared memory via DRAM remap, and then releasi= ng the SSP reset and enabling it through SCU control registers. To more accurately model this behavior in QEMU, this commit sets the "start-powered-off" property for the SSP's ARMv7M core. This change ensures the SSP remains off until explicitly enabled via the SCU, simulating the real-world flow where the PSP controls SSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index fff95eac6a..b1dfbc4292 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -177,6 +177,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); + /* + * The SSP starts in a powered-down state and can be powered up + * by setting the SSP Control Register through the SCU + * (System Control Unit) + */ + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 /* SDRAM */ --=20 2.43.0