From nobody Fri Sep 5 20:21:04 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724092; cv=none; d=zohomail.com; s=zohoarc; b=fbeUsLmLsNSAZf4O1Z+Ol3DR14xulCDF/3SZCFff5PU5kXMcVTHtYxBfcZCvpEgmBpVrfo5mRqdAIJb1PqqgQtFbPsO5CdvzIevEIYmzf1xrEX1PAa17829kd4dAFf4UtYUpxuItjFbfmu8HLpyVMNVNv5uBqfwWGP/76ogUDh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724092; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=uxUJVv27+8E+V3obVi150BqLYrp5qb/L0MuGJ2Q6wZo=; b=BiTCMQzxxmpj7l1eZyKTFjvL4nyXE437+o6jNdY1Wv1977Z0u0YHNnWAa5vWWbIDg+FnvVJw7d6w0Nm9OM1IFP3BAnSFFNfJ/fnzRdzD3I/VYHY4/rTaX/P3jLGV8TzKUq0Hu+9Zja5NvZyMu68BKRodnZFn7OpvVYzK8jAkvPc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17527240924011011.3066777074847; Wed, 16 Jul 2025 20:48:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFY4-0007xH-Td; Wed, 16 Jul 2025 23:44:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUr-0003Yq-Gy; Wed, 16 Jul 2025 23:41:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUp-0000ZH-FB; Wed, 16 Jul 2025 23:41:24 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:58 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:58 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Date: Thu, 17 Jul 2025 11:40:38 +0800 Message-ID: <20250717034054.1903991-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724093909116600 To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the initialization of the SDMC (SDRAM controller) and DRAM models earlier in the device realization order. In the upcoming changes, the PSP will expose a portion of its DRAM as shared memory by creating a memory region alias at a specific offset. This alias is mapped into the coprocessor's SDRAM address space, allowing both PSP and the coprocessor (SSP/TSP) to access the same physical memory through their resp= ective views =E2=80=94 PSP via its DRAM, and the coprocessor via its SDRAM. The remapping is configured through SCU registers and enables shared memory communication between PSP and the coprocessors. Therefore, the DRAM and SDMC devices must be realized before: - the SCU, which configures the alias offset and size - the coprocessors, which access the alias through their SDRAM window No functional change. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2d27eb1deb..9d67c5f631 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -765,6 +765,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0])= , i)); } =20 + /* + * SDMC - SDRAM Memory Controller + * The SDMC controller is unlocked at SPL stage. + * At present, only supports to emulate booting + * start from u-boot stage. Set SDMC controller + * unlocked by default. It is a temporarily solution. + */ + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, + sc->memmap[ASPEED_DEV_SDMC]); + + /* RAM */ + if (!aspeed_soc_ast2700_dram_init(dev, errp)) { + return; + } + /* SRAM */ name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, @@ -872,26 +892,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } =20 - /* - * SDMC - SDRAM Memory Controller - * The SDMC controller is unlocked at SPL stage. - * At present, only supports to emulate booting - * start from u-boot stage. Set SDMC controller - * unlocked by default. It is a temporarily solution. - */ - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { - return; - } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, - sc->memmap[ASPEED_DEV_SDMC]); - - /* RAM */ - if (!aspeed_soc_ast2700_dram_init(dev, errp)) { - return; - } - /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, --=20 2.43.0