From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723774; cv=none; d=zohomail.com; s=zohoarc; b=gx6PwjqZVido3Kigl/Jh+1ZB2Sl3CNyce/x0yJ0FEsKh17upxxxN9wKt2nznh/8r5W0Y5Sdw3o9LE8FgGc5n6RAtFqSpgi+ZqFr0sUgqIQpQ2jADERJrLqu0FCEf95x7KtHTr9x9wO/EyvKdHyYZNVSZOJJiVJaZuulbOPxzt0A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723774; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=DBNssKmwza/hd3rUo6WuynQBbftS6aX1RjCd5qiRelY=; b=W2DkGARM8Pe7COfsLY0N6H63dxoGtF9Trofk4IT8rE0N/k6JpMg3AYdcLWE9sTtwJSWL/F5WaiCqv8raL3A0uuK/t9+1hVns873lU1aiv8Q+ZYDJQCN290e5g0E/gMO1dk+FlpNBz5wJgs1Am5GVECG01pRNiH4YD3TJNbXM990= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752723774919243.058609446113; Wed, 16 Jul 2025 20:42:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFVo-00045S-0H; Wed, 16 Jul 2025 23:42:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUd-0003PZ-Rp; Wed, 16 Jul 2025 23:41:12 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUb-0000ZH-9U; Wed, 16 Jul 2025 23:41:10 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom Date: Thu, 17 Jul 2025 11:40:29 +0800 Message-ID: <20250717034054.1903991-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723776547116600 Content-Type: text/plain; charset="utf-8" Introduces support for loading a vbootrom image into the dedicated vbootrom memory region in the AST2700 Full Core machine. Additionally, it implements a mechanism to extract the content of fmc_cs0 flash data(backend file) and copy it into the memory-mapped region corresponding to ASPEED_DEV_SPI_BOOT. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-fc.c | 75 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index 7087be4288..e2eee6183f 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -11,6 +11,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/datadir.h" #include "qapi/error.h" #include "system/block-backend.h" #include "system/system.h" @@ -35,6 +36,7 @@ struct Ast2700FCState { =20 MemoryRegion ca35_memory; MemoryRegion ca35_dram; + MemoryRegion ca35_boot_rom; MemoryRegion ssp_memory; MemoryRegion tsp_memory; =20 @@ -55,12 +57,65 @@ struct Ast2700FCState { #define AST2700FC_HW_STRAP2 0x00000003 #define AST2700FC_FMC_MODEL "w25q01jvq" #define AST2700FC_SPI_MODEL "w25q512jv" +#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin" + +static void ast2700fc_ca35_load_vbootrom(AspeedSoCState *soc, + const char *bios_name, Error **er= rp) +{ + g_autofree char *filename =3D NULL; + int ret; + + filename =3D qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!filename) { + error_setg(errp, "Could not find vbootrom image '%s'", bios_name); + return; + } + + ret =3D load_image_mr(filename, &soc->vbootrom); + if (ret < 0) { + error_setg(errp, "Failed to load vbootrom image '%s'", bios_name); + return; + } +} + +static void ast2700fc_ca35_write_boot_rom(DriveInfo *dinfo, hwaddr addr, + size_t rom_size, Error **errp) +{ + BlockBackend *blk =3D blk_by_legacy_dinfo(dinfo); + g_autofree void *storage =3D NULL; + int64_t size; + + /* + * The block backend size should have already been 'validated' by + * the creation of the m25p80 object. + */ + size =3D blk_getlength(blk); + if (size <=3D 0) { + error_setg(errp, "failed to get flash size"); + return; + } + + if (rom_size > size) { + rom_size =3D size; + } + + storage =3D g_malloc0(rom_size); + if (blk_pread(blk, 0, rom_size, storage, 0) < 0) { + error_setg(errp, "failed to read the initial flash content"); + return; + } + + rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); +} =20 static void ast2700fc_ca35_init(MachineState *machine) { Ast2700FCState *s =3D AST2700A1FC(machine); + const char *bios_name =3D NULL; AspeedSoCState *soc; AspeedSoCClass *sc; + uint64_t rom_size; + DriveInfo *mtd0; =20 object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1"); soc =3D ASPEED_SOC(&s->ca35); @@ -118,6 +173,26 @@ static void ast2700fc_ca35_init(MachineState *machine) ast2700fc_board_info.ram_size =3D machine->ram_size; ast2700fc_board_info.loader_start =3D sc->memmap[ASPEED_DEV_SDRAM]; =20 + /* Install first FMC flash content as a boot rom. */ + if (!s->mmio_exec) { + mtd0 =3D drive_get(IF_MTD, 0, 0); + + if (mtd0) { + rom_size =3D memory_region_size(&soc->spi_boot); + memory_region_init_rom(&s->ca35_boot_rom, NULL, "aspeed.boot_r= om", + rom_size, &error_abort); + memory_region_add_subregion_overlap(&soc->spi_boot_container, = 0, + &s->ca35_boot_rom, 1); + ast2700fc_ca35_write_boot_rom(mtd0, + sc->memmap[ASPEED_DEV_SPI_BOOT], + rom_size, &error_abort); + } + } + + /* VBOOTROM */ + bios_name =3D machine->firmware ?: VBOOTROM_FILE_NAME; + ast2700fc_ca35_load_vbootrom(soc, bios_name, &error_abort); + arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); } =20 --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723796; cv=none; d=zohomail.com; s=zohoarc; b=K6pvhDzNPsFATOs77oXB1Mp0/f+e0GMyJc5GxxDa0cUdVf8W/9vzVlzoAp6OaN6nJM2U1TkyaMUkGAYWgNZYuTonb7d6mENLg0QVA9ItBjsluEVszbqwprX2+vPovV1CyHFZlGjGdSYjeHXHgWt3qww3jsmBauS7iZF7jLV4t4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723796; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=kbNWpP4I0U5R+GMdZvkqPIg3lJUYo6HQxs940zl8B3Q=; b=BsEjcixspKc5LRw6fN3KQWuSYkthBoBTkUy/M2qknKivDYH8kQU945Pc+EjnnPi0i0z8ZQb7I0UAp4eej0Rh1zDHqY/sk8JpEYNvlzFXOxFCAZ0y57suls0laE44ShwOR6eRknE/JDxBlVfGaifn8yp/hZpowC4wfxZUeZFuecw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17527237967206.900608423848098; Wed, 16 Jul 2025 20:43:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFWJ-0004eD-B7; Wed, 16 Jul 2025 23:42:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUd-0003PY-Ru; Wed, 16 Jul 2025 23:41:12 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUb-0000YT-KS; Wed, 16 Jul 2025 23:41:11 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve Date: Thu, 17 Jul 2025 11:40:30 +0800 Message-ID: <20250717034054.1903991-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723799210116600 In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was initial= ized and realized at the machine level (e.g., AST2700FC). However, to make sure = the coprocessors can work together properly=E2=80=94such as using the same SRAM= , sharing the SCU, and having consistent memory remapping=E2=80=94we need to change h= ow these devices are set up. This commit moves the SSP coprocessor initialization and realization into t= he AST2700 SoC (aspeed_soc_ast2700_init() and aspeed_soc_ast2700_realize()). By doing so, the SSP becomes a proper child of the SoC device, rather than the machine. This is a preparation step for future commits that will support shared SCU, SRAM, and memory remap logic=E2=80=94specifically enabling PSP DRAM remap f= or SSP SDRAM access. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 27 +++++++++++++----------- hw/arm/aspeed_ast27x0-fc.c | 30 ++------------------------ hw/arm/aspeed_ast27x0.c | 42 +++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 40 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 217ef0eafd..2831da91ab 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,6 +128,19 @@ struct Aspeed2600SoCState { #define TYPE_ASPEED2600_SOC "aspeed2600-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) =20 +struct Aspeed27x0SSPSoCState { + AspeedSoCState parent; + AspeedINTCState intc[2]; + UnimplementedDeviceState ipc[2]; + UnimplementedDeviceState scuio; + MemoryRegion memory; + + ARMv7MState armv7m; +}; + +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) + struct Aspeed27x0SoCState { AspeedSoCState parent; =20 @@ -135,6 +148,8 @@ struct Aspeed27x0SoCState { AspeedINTCState intc[2]; GICv3State gic; MemoryRegion dram_empty; + + Aspeed27x0SSPSoCState ssp; }; =20 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" @@ -146,18 +161,6 @@ struct Aspeed10x0SoCState { ARMv7MState armv7m; }; =20 -struct Aspeed27x0SSPSoCState { - AspeedSoCState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) - struct Aspeed27x0TSPSoCState { AspeedSoCState parent; AspeedINTCState intc[2]; diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index e2eee6183f..c9b338fe78 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -37,14 +37,11 @@ struct Ast2700FCState { MemoryRegion ca35_memory; MemoryRegion ca35_dram; MemoryRegion ca35_boot_rom; - MemoryRegion ssp_memory; MemoryRegion tsp_memory; =20 - Clock *ssp_sysclk; Clock *tsp_sysclk; =20 Aspeed27x0SoCState ca35; - Aspeed27x0SSPSoCState ssp; Aspeed27x0TSPSoCState tsp; =20 bool mmio_exec; @@ -158,6 +155,8 @@ static void ast2700fc_ca35_init(MachineState *machine) return; } aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0)); + aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp), ASPEED_DEV_UART4, + serial_hd(1)); if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) { return; } @@ -196,30 +195,6 @@ static void ast2700fc_ca35_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); } =20 -static void ast2700fc_ssp_init(MachineState *machine) -{ - AspeedSoCState *soc; - Ast2700FCState *s =3D AST2700A1FC(machine); - s->ssp_sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); - clock_set_hz(s->ssp_sysclk, 200000000ULL); - - object_initialize_child(OBJECT(s), "ssp", &s->ssp, TYPE_ASPEED27X0SSP_= SOC); - memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory", - UINT64_MAX); - - qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk); - if (!object_property_set_link(OBJECT(&s->ssp), "memory", - OBJECT(&s->ssp_memory), &error_abort)) { - return; - } - - soc =3D ASPEED_SOC(&s->ssp); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1)); - if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) { - return; - } -} - static void ast2700fc_tsp_init(MachineState *machine) { AspeedSoCState *soc; @@ -247,7 +222,6 @@ static void ast2700fc_tsp_init(MachineState *machine) static void ast2700fc_init(MachineState *machine) { ast2700fc_ca35_init(machine); - ast2700fc_ssp_init(machine); ast2700fc_tsp_init(machine); } =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6aa3841b69..ffbc32fef2 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -22,6 +22,8 @@ #include "hw/intc/arm_gicv3.h" #include "qobject/qlist.h" #include "qemu/log.h" +#include "hw/qdev-clock.h" +#include "hw/boards.h" =20 #define AST2700_SOC_IO_SIZE 0x00FE0000 #define AST2700_SOC_IOMEM_SIZE 0x01000000 @@ -410,6 +412,8 @@ static bool aspeed_soc_ast2700_dram_init(DeviceState *d= ev, Error **errp) =20 static void aspeed_soc_ast2700_init(Object *obj) { + MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(obj); AspeedSoCState *s =3D ASPEED_SOC(obj); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); @@ -426,6 +430,11 @@ static void aspeed_soc_ast2700_init(Object *obj) aspeed_soc_cpu_type(sc)); } =20 + /* Coprocessors */ + if (mc->default_cpus > sc->num_cpus) { + object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SO= C); + } + object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); =20 object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); @@ -610,9 +619,35 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState= *dev, Error **errp) return true; } =20 +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp) +{ + Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); + AspeedSoCState *s =3D ASPEED_SOC(dev); + Clock *sysclk; + + sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); + clock_set_hz(sysclk, 200000000ULL); + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk); + + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory", + UINT64_MAX); + if (!object_property_set_link(OBJECT(&a->ssp), "memory", + OBJECT(&a->ssp.memory), &error_abort)) { + return false; + } + + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { + return false; + } + + return true; +} + static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) { int i; + MachineState *ms =3D MACHINE(qdev_get_machine()); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); AspeedSoCState *s =3D ASPEED_SOC(dev); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); @@ -719,6 +754,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, sc->memmap[ASPEED_DEV_SCUIO]); =20 + /* Coprocessors */ + if (mc->default_cpus > sc->num_cpus) { + if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { + return; + } + } + /* UART */ if (!aspeed_soc_uart_realize(s, errp)) { return; --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723772; cv=none; d=zohomail.com; s=zohoarc; b=bixHrlbJHE/tGDbMuD7ia/V4ft1xxQu/+hO3krMeOdDLcWFYWQH9OedgBjfwP/ql2tAR2XnWbYYj/cTmBKWU03n4YesF5Fy5yxd/qVQGprEmkgL7F519koZNGN0IKROK9+UZEFSW/CEEqGquaQOJiW6OIFTHcL9qT1hRn1Uo+C4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723772; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=ykxPHDvIIKVF/fUVhcjL0TllHFhHIJriP6PDNAaZ7Qg=; b=iEEUzTa8SF+mbWe7WjGn0LBLGwkkqa7f5mhnVYWXXsrWSLZQUvzGmjXAzGv5UdoCB3YS8cs6bgLOCslVlkHvOmnJbJV3R6jEFXPoXvpsVoq28Mie+H8oj4UAqrqXABIwxzbTI9hMhhylkAqrDkmwWcxJdvNczijIz4/kgqUOaac= ARC-Authentication-Results: i=1; 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Thu, 17 Jul 2025 11:40:56 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:56 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 03/21] hw/arm/ast27x0: Move TSP coprocessor initialization from machine to SoC leve Date: Thu, 17 Jul 2025 11:40:31 +0800 Message-ID: <20250717034054.1903991-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723774598116600 In the previous design, the TSP coprocessor (aspeed27x0tsp-soc) was initial= ized and realized at the machine level (e.g., AST2700FC). To allow proper integration between coprocessors=E2=80=94such as shared use of SRAM, SCU, a= nd memory remap configuration=E2=80=94this commit moves TSP initialization into the A= ST2700 SoC. By handling TSP initialization and realization at the SoC level, it becomes easier to manage device ordering and ensure correct dependencies between coprocessors and controllers. It also reflects the hardware design more accurately, as these processors belong to the SoC, not the board. Benefits of this change: - TSP can share SCU, SRAM, and memory regions with other SoC devices. - Centralizes coprocessor setup logic under SoC for better maintenance. - Simplifies machine-level code in "aspeed_ast27x0-fc.c". This is part of ongoing work to support shared SCU, SRAM, and memory remap handling across PSP, SSP, and TSP. Future commits will add memory remap mechanisms and tightly integrated SoC controller coordination. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 26 ++++++++++++++------------ hw/arm/aspeed_ast27x0-fc.c | 32 ++------------------------------ hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 42 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 2831da91ab..3dd317cfee 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -141,6 +141,19 @@ struct Aspeed27x0SSPSoCState { #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC) =20 +struct Aspeed27x0TSPSoCState { + AspeedSoCState parent; + AspeedINTCState intc[2]; + UnimplementedDeviceState ipc[2]; + UnimplementedDeviceState scuio; + MemoryRegion memory; + + ARMv7MState armv7m; +}; + +#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) + struct Aspeed27x0SoCState { AspeedSoCState parent; =20 @@ -150,6 +163,7 @@ struct Aspeed27x0SoCState { MemoryRegion dram_empty; =20 Aspeed27x0SSPSoCState ssp; + Aspeed27x0TSPSoCState tsp; }; =20 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" @@ -161,18 +175,6 @@ struct Aspeed10x0SoCState { ARMv7MState armv7m; }; =20 -struct Aspeed27x0TSPSoCState { - AspeedSoCState parent; - AspeedINTCState intc[2]; - UnimplementedDeviceState ipc[2]; - UnimplementedDeviceState scuio; - - ARMv7MState armv7m; -}; - -#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc" -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC) - #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) =20 diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c index c9b338fe78..eb25a2635b 100644 --- a/hw/arm/aspeed_ast27x0-fc.c +++ b/hw/arm/aspeed_ast27x0-fc.c @@ -37,18 +37,13 @@ struct Ast2700FCState { MemoryRegion ca35_memory; MemoryRegion ca35_dram; MemoryRegion ca35_boot_rom; - MemoryRegion tsp_memory; - - Clock *tsp_sysclk; =20 Aspeed27x0SoCState ca35; - Aspeed27x0TSPSoCState tsp; =20 bool mmio_exec; }; =20 #define AST2700FC_BMC_RAM_SIZE (1 * GiB) -#define AST2700FC_CM4_DRAM_SIZE (32 * MiB) =20 #define AST2700FC_HW_STRAP1 0x000000C0 #define AST2700FC_HW_STRAP2 0x00000003 @@ -157,6 +152,8 @@ static void ast2700fc_ca35_init(MachineState *machine) aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0)); aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp), ASPEED_DEV_UART4, serial_hd(1)); + aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.tsp), ASPEED_DEV_UART7, + serial_hd(2)); if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) { return; } @@ -195,34 +192,9 @@ static void ast2700fc_ca35_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info); } =20 -static void ast2700fc_tsp_init(MachineState *machine) -{ - AspeedSoCState *soc; - Ast2700FCState *s =3D AST2700A1FC(machine); - s->tsp_sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); - clock_set_hz(s->tsp_sysclk, 200000000ULL); - - object_initialize_child(OBJECT(s), "tsp", &s->tsp, TYPE_ASPEED27X0TSP_= SOC); - memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory", - UINT64_MAX); - - qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk); - if (!object_property_set_link(OBJECT(&s->tsp), "memory", - OBJECT(&s->tsp_memory), &error_abort)) { - return; - } - - soc =3D ASPEED_SOC(&s->tsp); - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2)); - if (!qdev_realize(DEVICE(&s->tsp), NULL, &error_abort)) { - return; - } -} - static void ast2700fc_init(MachineState *machine) { ast2700fc_ca35_init(machine); - ast2700fc_tsp_init(machine); } =20 static void ast2700fc_class_init(ObjectClass *oc, const void *data) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index ffbc32fef2..665627f788 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -433,6 +433,7 @@ static void aspeed_soc_ast2700_init(Object *obj) /* Coprocessors */ if (mc->default_cpus > sc->num_cpus) { object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SO= C); + object_initialize_child(obj, "tsp", &a->tsp, TYPE_ASPEED27X0TSP_SO= C); } =20 object_initialize_child(obj, "gic", &a->gic, gicv3_class_name()); @@ -643,6 +644,30 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState= *dev, Error **errp) return true; } =20 +static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp) +{ + Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); + AspeedSoCState *s =3D ASPEED_SOC(dev); + Clock *sysclk; + + sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); + clock_set_hz(sysclk, 200000000ULL); + qdev_connect_clock_in(DEVICE(&a->tsp), "sysclk", sysclk); + + memory_region_init(&a->tsp.memory, OBJECT(&a->tsp), "tsp-memory", + UINT64_MAX); + if (!object_property_set_link(OBJECT(&a->tsp), "memory", + OBJECT(&a->tsp.memory), &error_abort)) { + return false; + } + + if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) { + return false; + } + + return true; +} + static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) { int i; @@ -759,6 +784,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { return; } + if (!aspeed_soc_ast2700_tsp_realize(dev, errp)) { + return; + } } =20 /* UART */ --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723864; cv=none; d=zohomail.com; s=zohoarc; b=nMr6W7Mq3r7DntjykbDE+q9EZn2sN5hjPnzFagnRWeD5vaKbnF23g6cRmtaiUizibqaIhJiMY56Ofj2pt2pWGsyQLRtRKp7LcJa5fSM/KafNtfleWdYGH+93laKV1wgsriqRbjEqJEbBIn2xpdbYZKvBTYES87fSOtWrovTJ1u4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723864; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Wed, 16 Jul 2025 23:41:14 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:56 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:56 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support Date: Thu, 17 Jul 2025 11:40:32 +0800 Message-ID: <20250717034054.1903991-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723865490116600 According to the AST2700 design, the SSP coprocessor uses its own SDRAM instead of SRAM. Additionally, all three coprocessors=E2=80=94SSP, TSP, and= PSP=E2=80=94share a common SRAM block. In the previous implementation, the SSP memory region was labeled and sized as "SRAM", but in practice it was being used as SSP's local SDRAM. This commit updates the SSP memory mapping to reflect the correct hardware design: - Replace the SRAM region with a "512MB SDRAM" region starting at 0x0. - Rename the internal variable from "sram" to "dram_container" for clarity. - Use "AST2700_SSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM si= ze. - Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM". This change also prepares for future enhancements where PSP DRAM will be remapped into this SSP SDRAM container using subregions at specific offsets. Using "dram_container" makes it easier to manage aliases and remap logic. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 80ec5996c1..9641e27de1 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -15,10 +15,10 @@ #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" =20 -#define AST2700_SSP_RAM_SIZE (32 * MiB) +#define AST2700_SSP_SDRAM_SIZE (512 * MiB) =20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] =3D { - [ASPEED_DEV_SRAM] =3D 0x00000000, + [ASPEED_DEV_SDRAM] =3D 0x00000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCState *s =3D ASPEED_SOC(dev_soc); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; - g_autofree char *sram_name =3D NULL; + g_autofree char *name =3D NULL; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState= *dev_soc, Error **errp) OBJECT(s->memory), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 - sram_name =3D g_strdup_printf("aspeed.dram.%d", - CPU(a->armv7m.cpu)->cpu_index); + /* SDRAM */ + name =3D g_strdup_printf("aspeed.sdram-container.%d", + CPU(a->armv7m.cpu)->cpu_index); =20 - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, - errp)) { + if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name, + AST2700_SSP_SDRAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, - sc->memmap[ASPEED_DEV_SRAM], - &s->sram); + sc->memmap[ASPEED_DEV_SDRAM], + &s->dram_container); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, const void *dat =20 sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; - sc->sram_size =3D AST2700_SSP_RAM_SIZE; sc->spis_num =3D 0; sc->ehcis_num =3D 0; sc->wdts_num =3D 0; --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723901; cv=none; d=zohomail.com; s=zohoarc; b=mrK4zSmDEbQ/Ib2xBbKC23Gf7W4qXcWSa8WI164ddiYYZrvl5MeiHUkYDMN8ikZU2XteimzCeVAbfp2DQmlYMudfTRGK11GRkPp4Ir5ZoZ26P6PCpEpbw5r5eTYz4vzQybIXheIDemAFsqJwOCN/AXmLrWS+K/o3q4JqSsdPH3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723901; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Wed, 16 Jul 2025 23:41:17 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:56 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:56 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP memory to SDRAM and use dram_container for remap support Date: Thu, 17 Jul 2025 11:40:33 +0800 Message-ID: <20250717034054.1903991-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723901939116600 According to the AST2700 design, the TSP coprocessor uses its own SDRAM instead of SRAM. Additionally, all three coprocessors=E2=80=94SSP, TSP, and= PSP=E2=80=94share a common SRAM block. In the previous implementation, the TSP memory region was labeled and sized as "SRAM", but in practice it was being used as TSP's local SDRAM. This commit updates the TSP memory mapping to reflect the correct hardware design: - Replace the SRAM region with a 512MB SDRAM region starting at 0x0. - Rename the internal variable from `sram` to `dram_container` for clarity. - Use "AST2700_TSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM si= ze. - Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM". This change also prepares for future enhancements where PSP DRAM will be remapped into this TSP SDRAM container using subregions at specific offsets. Using "dram_container" makes it easier to manage aliases and remap logic. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-tsp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 4e0efaef07..a70e30fc16 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -15,10 +15,10 @@ #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" =20 -#define AST2700_TSP_RAM_SIZE (32 * MiB) +#define AST2700_TSP_SDRAM_SIZE (512 * MiB) =20 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] =3D { - [ASPEED_DEV_SRAM] =3D 0x00000000, + [ASPEED_DEV_SDRAM] =3D 0x00000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AspeedSoCState *s =3D ASPEED_SOC(dev_soc); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; - g_autofree char *sram_name =3D NULL; + g_autofree char *name =3D NULL; int i; =20 if (!clock_has_source(s->sysclk)) { @@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState= *dev_soc, Error **errp) OBJECT(s->memory), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 - sram_name =3D g_strdup_printf("aspeed.dram.%d", - CPU(a->armv7m.cpu)->cpu_index); + /* SDRAM */ + name =3D g_strdup_printf("aspeed.sdram-container.%d", + CPU(a->armv7m.cpu)->cpu_index); =20 - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_s= ize, - errp)) { + if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name, + AST2700_TSP_SDRAM_SIZE, errp)) { return; } memory_region_add_subregion(s->memory, - sc->memmap[ASPEED_DEV_SRAM], - &s->sram); + sc->memmap[ASPEED_DEV_SDRAM], + &s->dram_container); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, const void *dat =20 sc->valid_cpu_types =3D valid_cpu_types; sc->silicon_rev =3D AST2700_A1_SILICON_REV; - sc->sram_size =3D AST2700_TSP_RAM_SIZE; sc->spis_num =3D 0; sc->ehcis_num =3D 0; sc->wdts_num =3D 0; --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724300; cv=none; d=zohomail.com; s=zohoarc; b=HkJafm1s3tRimonu4UKYfsDJPTbEHTkmM9zOCZ5HY5hZujZZ6cByeWleABj+48SHTwngdBU6HtNlrItKQTMXi6rg7Hywy6ughJZhtjFWrKhdpanFK3o5WGp1gmXrCZOEBqnxW+DUPSJbi38hThY69IeJGI9x8ZLuWfRlXNSEFcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724300; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Wed, 16 Jul 2025 23:41:17 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:57 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:57 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order Date: Thu, 17 Jul 2025 11:40:34 +0800 Message-ID: <20250717034054.1903991-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724302307116600 AST2700 has a 128KB SRAM, physically mapped at 0x10000000=E2=80=930x1001FFF= F for the main CA35 processor. The SSP coprocessor accesses this same memory at a different memory address: 0x70000000=E2=80=930x7001FFFF. To support this shared memory model, this commit introduces "ssp.sram_mr_al= ias", a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is realized during SSP SoC setup and mapped into the SSP's SoC memory map. Additionally, because the SRAM must be realized before the SSP can create an alias to it, the device realization order is explicitly managed: "aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized. This ensures that SSP=E2=80=99s access to shared SRAM functions correctly. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-ssp.c | 5 +++++ hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++- 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 3dd317cfee..9b935b9bca 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState { UnimplementedDeviceState ipc[2]; UnimplementedDeviceState scuio; MemoryRegion memory; + MemoryRegion sram_mr_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 9641e27de1..b7b886f4bf 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -19,6 +19,7 @@ =20 static const hwaddr aspeed_soc_ast27x0ssp_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x00000000, + [ASPEED_DEV_SRAM] =3D 0x70000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); =20 + /* SRAM */ + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], + &a->sram_mr_alias); + /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 665627f788..9064249bed 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -624,6 +624,7 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState = *dev, Error **errp) { Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); AspeedSoCState *s =3D ASPEED_SOC(dev); + MemoryRegion *mr; Clock *sysclk; =20 sysclk =3D clock_new(OBJECT(s), "SSP_SYSCLK"); @@ -637,6 +638,9 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState = *dev, Error **errp) return false; } =20 + mr =3D &s->sram; + memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.a= lias", + mr, 0, memory_region_size(mr)); if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { return false; } @@ -779,7 +783,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0, sc->memmap[ASPEED_DEV_SCUIO]); =20 - /* Coprocessors */ + /* + * Coprocessors must be realized after the SRAM region. + * + * The SRAM is used for shared memory between the main CPU (PSP) and + * coprocessors. The coprocessors accesses this shared SRAM region + * through a memory alias mapped to a different physical address. + * + * Therefore, the SRAM must be fully initialized before the coprocesso= rs + * can create aliases pointing to it. + */ if (mc->default_cpus > sc->num_cpus) { if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { return; --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724086; cv=none; d=zohomail.com; s=zohoarc; b=ndSG0RSkb2T606jMw4CgNn+0jpDAxn2OKlC52DjwsMQiepvwIy6P59s0aKmUAPFa5GXnY+BgqB51GgiEW33yzufYXptzI1faBdwIFpI98XNCFu9dmYM43kcuCWqs9W0nwb+0rOWmigto0oxrSjWpiWN4VVnqWJqxc7+CA4CeP/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724086; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=zXaTs0YBrQWTbHQAEuYVSvZgFwQdgaHKUBoWjbctVZ0=; b=OLby9LxeJjGptaYvQPfF7S0q/bYHnrYyAhWmd4lnnxMwH3qE2YQJXTSCDOM5AdWCiGArN9K968qZ8Q4awzo26NSwIcolLqWCGanp+EKoS4BwO2sdBqrYlF1PoNhUXA8FomL7FzVi2gchCJzubvwaq6XI3a0cDd0c4pvS3X6kWOw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752724086336617.6694061983263; Wed, 16 Jul 2025 20:48:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFXm-0006i3-BJ; Wed, 16 Jul 2025 23:44:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUm-0003XO-ST; Wed, 16 Jul 2025 23:41:25 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUl-0000YT-AB; Wed, 16 Jul 2025 23:41:20 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:57 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:57 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP and ensure correct device realization order Date: Thu, 17 Jul 2025 11:40:35 +0800 Message-ID: <20250717034054.1903991-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724087964116600 AST2700 has a 128KB SRAM, physically mapped at 0x10000000=E2=80=930x1001FFF= F for the main CA35 processor. The TSP coprocessor accesses this same memory at a different memory address: 0x70000000=E2=80=930x7001FFFF. To support this shared memory model, this commit introduces "tsp.sram_mr_al= ias", a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is realized during TSP SoC setup and mapped into the TSP's SoC memory map. Additionally, because the SRAM must be realized before the TSP can create an alias to it, the device realization order is explicitly managed: "aspeed_soc_ast2700_tsp_realize()" is invoked after SRAM is initialized. This ensures that TSP=E2=80=99s access to shared SRAM functions correctly. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-tsp.c | 5 +++++ hw/arm/aspeed_ast27x0.c | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9b935b9bca..1e4f8580b1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -148,6 +148,7 @@ struct Aspeed27x0TSPSoCState { UnimplementedDeviceState ipc[2]; UnimplementedDeviceState scuio; MemoryRegion memory; + MemoryRegion sram_mr_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index a70e30fc16..8438aefee5 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -19,6 +19,7 @@ =20 static const hwaddr aspeed_soc_ast27x0tsp_memmap[] =3D { [ASPEED_DEV_SDRAM] =3D 0x00000000, + [ASPEED_DEV_SRAM] =3D 0x70000000, [ASPEED_DEV_INTC] =3D 0x72100000, [ASPEED_DEV_SCU] =3D 0x72C02000, [ASPEED_DEV_SCUIO] =3D 0x74C02000, @@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); =20 + /* SRAM */ + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], + &a->sram_mr_alias); + /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9064249bed..8272a28ad5 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -652,6 +652,7 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState = *dev, Error **errp) { Aspeed27x0SoCState *a =3D ASPEED27X0_SOC(dev); AspeedSoCState *s =3D ASPEED_SOC(dev); + MemoryRegion *mr; Clock *sysclk; =20 sysclk =3D clock_new(OBJECT(s), "TSP_SYSCLK"); @@ -665,6 +666,9 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState = *dev, Error **errp) return false; } =20 + mr =3D &s->sram; + memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.a= lias", + mr, 0, memory_region_size(mr)); if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) { return false; } --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 17 Jul 2025 11:40:57 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:57 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order Date: Thu, 17 Jul 2025 11:40:36 +0800 Message-ID: <20250717034054.1903991-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724063663116600 AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000=E2=80= =930x12C03FFF from the perspective of the main CA35 processor (PSP). The SSP coprocessor = accesses this same SCU block at a different address: 0x72C02000=E2=80=930x72C03FFF. To support this shared SCU model, this commit introduces "ssp.scu_mr_alias", a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The ali= as is realized during SSP SoC setup and mapped into the SSP's SoC memory map. Additionally, because the SCU must be realized before the SSP can create an= alias to it, the device realization order is explicitly managed: "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized. This ensures that PSP and SSP access a consistent SCU state, as expected by= hardware. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-ssp.c | 9 ++------- hw/arm/aspeed_ast27x0.c | 24 ++++++++++++++++++------ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 1e4f8580b1..65a452123b 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -135,6 +135,7 @@ struct Aspeed27x0SSPSoCState { UnimplementedDeviceState scuio; MemoryRegion memory; MemoryRegion sram_mr_alias; + MemoryRegion scu_mr_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index b7b886f4bf..0a58b8ea4b 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -135,9 +135,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -198,10 +196,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) &a->sram_mr_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &a->scu_mr_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -273,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClas= s *klass, const void *dat dc->realize =3D aspeed_soc_ast27x0ssp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->spis_num =3D 0; sc->ehcis_num =3D 0; sc->wdts_num =3D 0; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 8272a28ad5..04b8b340ba 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -641,6 +641,10 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState= *dev, Error **errp) mr =3D &s->sram; memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.a= lias", mr, 0, memory_region_size(mr)); + + mr =3D &s->scu.iomem; + memory_region_init_alias(&a->ssp.scu_mr_alias, OBJECT(s), "ssp.scu.ali= as", + mr, 0, memory_region_size(mr)); if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) { return false; } @@ -788,14 +792,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) sc->memmap[ASPEED_DEV_SCUIO]); =20 /* - * Coprocessors must be realized after the SRAM region. + * Coprocessors must be realized after the SRAM and SCU regions. + * + * The SRAM is used as shared memory between the main CPU (PSP) and the + * coprocessors. Coprocessors access this shared SRAM region through a + * MemoryRegion alias mapped to a different physical address. + * + * Similarly, the SCU is a single hardware block shared across all + * processors. Coprocessors access it via a MemoryRegion alias that ma= ps + * to a different address than the one used by the main CPU. * - * The SRAM is used for shared memory between the main CPU (PSP) and - * coprocessors. The coprocessors accesses this shared SRAM region - * through a memory alias mapped to a different physical address. + * Therefore, both the SRAM and SCU must be fully initialized before t= he + * coprocessors can create aliases pointing to them. * - * Therefore, the SRAM must be fully initialized before the coprocesso= rs - * can create aliases pointing to it. + * To ensure correctness, the device realization order is explicitly + * managed: + * coprocessors are initialized only after SRAM and SCU are ready. */ if (mc->default_cpus > sc->num_cpus) { if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723905; cv=none; d=zohomail.com; s=zohoarc; b=Ym4UZd/ozn7+mGNas5bc6BG1A0pWRP4rBnrM7UpO85joD+LQyfX3NFV5P6VWZunJgjzk0F+BbSah2eUOHEZ7/bikC+UfsE1OphlpE7C+DkPL4nG8GTGWG0PA10eo525LvJ2JDLcNilF5xNj5IFZiuQjFJDBbw1AQlATs0aBfVeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723905; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=rxcYF1uI6g4PQAlvbSB6sag5/VUEOeEDQ5IUDqSV1X0=; b=LX+feP4Ezm8s169Lv4VxSRS4Vy1hMYEiosUNCOHZqc4FGMn08E8mzRB47yn2oAl488d8Hjj35RBYbufH7HzcTvsRUTxgPzWthw6UrDuDoUc+pXMJTRO91rdUq9eHS46nceacpe/jxGNK/NkGEnsVXmAkQQ2Rdvh7b+ntPmo6z3w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752723905058142.5939216677881; Wed, 16 Jul 2025 20:45:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFY1-0007ed-AN; Wed, 16 Jul 2025 23:44:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUr-0003Yo-Fu; Wed, 16 Jul 2025 23:41:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUo-0000YT-S4; Wed, 16 Jul 2025 23:41:24 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:58 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:58 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP and ensure correct device realization order Date: Thu, 17 Jul 2025 11:40:37 +0800 Message-ID: <20250717034054.1903991-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723906030116600 AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000=E2=80= =930x12C03FFF from the perspective of the main CA35 processor (PSP). The TSP coprocessor = accesses this same SCU block at a different address: 0x72C02000=E2=80=930x72C03FFF. To support this shared SCU model, this commit introduces "tsp.scu_mr_alias", a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The ali= as is realized during TSP SoC setup and mapped into the TSP's SoC memory map. Additionally, because the SCU must be realized before the TSP can create an= alias to it, the device realization order is explicitly managed: "aspeed_soc_ast2700_tsp_realize()" is invoked after the SCU is initialized. This ensures that PSP and TSP access a consistent SCU state, as expected by= hardware. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-tsp.c | 9 ++------- hw/arm/aspeed_ast27x0.c | 4 ++++ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 65a452123b..4152fbf495 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -150,6 +150,7 @@ struct Aspeed27x0TSPSoCState { UnimplementedDeviceState scuio; MemoryRegion memory; MemoryRegion sram_mr_alias; + MemoryRegion scu_mr_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 8438aefee5..6b035e2612 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -135,9 +135,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj) int i; =20 object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); - object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU); s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); - qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev); =20 for (i =3D 0; i < sc->uarts_num; i++) { object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_M= M); @@ -198,10 +196,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) &a->sram_mr_alias); =20 /* SCU */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; - } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_S= CU]); + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], + &a->scu_mr_alias); =20 /* INTC */ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) { @@ -273,7 +269,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClas= s *klass, const void *dat dc->realize =3D aspeed_soc_ast27x0tsp_realize; =20 sc->valid_cpu_types =3D valid_cpu_types; - sc->silicon_rev =3D AST2700_A1_SILICON_REV; sc->spis_num =3D 0; sc->ehcis_num =3D 0; sc->wdts_num =3D 0; diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 04b8b340ba..2d27eb1deb 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -673,6 +673,10 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState= *dev, Error **errp) mr =3D &s->sram; memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.a= lias", mr, 0, memory_region_size(mr)); + + mr =3D &s->scu.iomem; + memory_region_init_alias(&a->tsp.scu_mr_alias, OBJECT(s), "tsp.scu.ali= as", + mr, 0, memory_region_size(mr)); if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) { return false; } --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724092; cv=none; d=zohomail.com; s=zohoarc; b=fbeUsLmLsNSAZf4O1Z+Ol3DR14xulCDF/3SZCFff5PU5kXMcVTHtYxBfcZCvpEgmBpVrfo5mRqdAIJb1PqqgQtFbPsO5CdvzIevEIYmzf1xrEX1PAa17829kd4dAFf4UtYUpxuItjFbfmu8HLpyVMNVNv5uBqfwWGP/76ogUDh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724092; 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Wed, 16 Jul 2025 23:44:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUr-0003Yq-Gy; Wed, 16 Jul 2025 23:41:31 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFUp-0000ZH-FB; Wed, 16 Jul 2025 23:41:24 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:58 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:58 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Date: Thu, 17 Jul 2025 11:40:38 +0800 Message-ID: <20250717034054.1903991-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724093909116600 To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the initialization of the SDMC (SDRAM controller) and DRAM models earlier in the device realization order. In the upcoming changes, the PSP will expose a portion of its DRAM as shared memory by creating a memory region alias at a specific offset. This alias is mapped into the coprocessor's SDRAM address space, allowing both PSP and the coprocessor (SSP/TSP) to access the same physical memory through their resp= ective views =E2=80=94 PSP via its DRAM, and the coprocessor via its SDRAM. The remapping is configured through SCU registers and enables shared memory communication between PSP and the coprocessors. Therefore, the DRAM and SDMC devices must be realized before: - the SCU, which configures the alias offset and size - the coprocessors, which access the alias through their SDRAM window No functional change. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 2d27eb1deb..9d67c5f631 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -765,6 +765,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0])= , i)); } =20 + /* + * SDMC - SDRAM Memory Controller + * The SDMC controller is unlocked at SPL stage. + * At present, only supports to emulate booting + * start from u-boot stage. Set SDMC controller + * unlocked by default. It is a temporarily solution. + */ + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, + sc->memmap[ASPEED_DEV_SDMC]); + + /* RAM */ + if (!aspeed_soc_ast2700_dram_init(dev, errp)) { + return; + } + /* SRAM */ name =3D g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size, @@ -872,26 +892,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); } =20 - /* - * SDMC - SDRAM Memory Controller - * The SDMC controller is unlocked at SPL stage. - * At present, only supports to emulate booting - * start from u-boot stage. Set SDMC controller - * unlocked by default. It is a temporarily solution. - */ - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true, - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { - return; - } - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, - sc->memmap[ASPEED_DEV_SDMC]); - - /* RAM */ - if (!aspeed_soc_ast2700_dram_init(dev, errp)) { - return; - } - /* Net */ for (i =3D 0; i < sc->macs_num; i++) { object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724066; cv=none; d=zohomail.com; s=zohoarc; b=cms/VjzdXmq6cTrMJ9lCwWPfaK+Y3V9wb8d8WBu7pTZITHwfHf8M5vURVFNpgVn4US+WzpVMDUI9CYgThiN+6Z9JODCKGORuBAeHfdOimVAgtundpgODnd64d/fZ2v2bb7tGKPVpdtZo+z2rIgC/4O6q2MfI87/q87QVe7TQ/3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gbjMzMoLW3dK1Ar5H77b408gFCeq3cUiJVO+YqRtbjA=; b=Ehc3mncrKrWZjoN1kROqJC8pkRs43enoULcG6+i6NXDYsgYhR+70/sQ8KMuXfl0Y7Dzxe1xj2W0MHKGUl5XZJD8Rq8X/FuNO8/VLScdmf33BWNLVeON/84Z4CjyDfL85zBlWB7rUNp0ZFXWXpBbsSqTEBgeU/8qMJvWqpBhZKjY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752724066603305.9049010256607; Wed, 16 Jul 2025 20:47:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFXz-0007V6-Ff; Wed, 16 Jul 2025 23:44:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVF-0003gw-DC; Wed, 16 Jul 2025 23:42:04 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVD-0000YT-0l; Wed, 16 Jul 2025 23:41:48 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:58 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:58 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order Date: Thu, 17 Jul 2025 11:40:39 +0800 Message-ID: <20250717034054.1903991-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724067765116600 Content-Type: text/plain; charset="utf-8" This commit adds two MemoryRegion aliases to support PSP access to SSP SDRAM through shared memory remapping, as defined by the default SCU configuration. The SSP coprocessor exposes two DRAM aliases: - remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000 - remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0 These regions correspond to the default SCU register values, which control the mapping between PSP and coprocessor memory windows. To ensure correctness, the aliases are initialized early in aspeed_soc_ast2700_realize(), before SCU and coprocessor realization. This allows SSP to reference the alias regions during its SDRAM setup. Additionally, the realization order comment has been updated to reflect the new DRAM dependency: coprocessors must now be realized after DRAM, SRAM, and SCU are all initialized. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_ast27x0-ssp.c | 5 ++++ hw/arm/aspeed_ast27x0.c | 49 ++++++++++++++++++++++++++++--------- 3 files changed, 45 insertions(+), 11 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4152fbf495..d628a189c1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -136,6 +136,8 @@ struct Aspeed27x0SSPSoCState { MemoryRegion memory; MemoryRegion sram_mr_alias; MemoryRegion scu_mr_alias; + MemoryRegion sdram_remap1_alias; + MemoryRegion sdram_remap2_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index 0a58b8ea4b..fff95eac6a 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -187,6 +187,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) AST2700_SSP_SDRAM_SIZE, errp)) { return; } + /* SDRAM remap alias used by PSP to access SSP SDRAM */ + memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap2_al= ias); + memory_region_add_subregion(&s->dram_container, + memory_region_size(&a->sdram_remap2_alias), + &a->sdram_remap1_alias); memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 9d67c5f631..be130db5e2 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -803,6 +803,28 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) sc->memmap[ASPEED_DEV_VBOOTROM], &s->vboot= rom); =20 /* SCU */ + /* + * The SSP coprocessor uses two memory aliases (remap1 and remap2) + * to access shared memory regions in the PSP DRAM: + * + * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM + * offset 0x2000000 + * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM + * offset 0x0 + * + * These mappings correspond to the default values of the SCU register= s: + * + * This configuration enables shared memory communication between the = PSP + * and coprocessors, with address translation controlled by the SCU. + */ + if (mc->default_cpus > sc->num_cpus) { + memory_region_init_alias(&a->ssp.sdram_remap1_alias, OBJECT(a), + "ssp.sdram.remap1", s->memory, + 0x400000000ULL, 32 * MiB); + memory_region_init_alias(&a->ssp.sdram_remap2_alias, OBJECT(a), + "ssp.sdram.remap2", s->memory, + 0x42c000000ULL, 32 * MiB); + } if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; } @@ -816,22 +838,27 @@ static void aspeed_soc_ast2700_realize(DeviceState *d= ev, Error **errp) sc->memmap[ASPEED_DEV_SCUIO]); =20 /* - * Coprocessors must be realized after the SRAM and SCU regions. + * Coprocessors must be realized after the DRAM, SRAM, and SCU regions. * - * The SRAM is used as shared memory between the main CPU (PSP) and the - * coprocessors. Coprocessors access this shared SRAM region through a - * MemoryRegion alias mapped to a different physical address. + * - DRAM: Coprocessors access shared memory through MemoryRegion alia= ses + * that point into PSP's DRAM space. These aliases are mapped into t= he + * coprocessors' SDRAM windows at specific offsets (e.g., 0x0 and + * 0x2000000), and configured according to SCU register defaults. + * Therefore, DRAM must be fully initialized before coprocessors can + * attach aliases to it. * - * Similarly, the SCU is a single hardware block shared across all - * processors. Coprocessors access it via a MemoryRegion alias that ma= ps - * to a different address than the one used by the main CPU. + * - SRAM: Used as shared memory between the PSP and coprocessors. + * Coprocessors access this memory via alias regions mapped to + * different physical addresses. * - * Therefore, both the SRAM and SCU must be fully initialized before t= he - * coprocessors can create aliases pointing to them. + * - SCU: A single hardware block shared across all processors. + * Coprocessors access SCU registers through alias mappings. + * SCU must be initialized first to allow for consistent register + * state and memory remap configuration. * * To ensure correctness, the device realization order is explicitly - * managed: - * coprocessors are initialized only after SRAM and SCU are ready. + * managed: coprocessors are initialized only after DRAM, SRAM, and SCU + * are ready. */ if (mc->default_cpus > sc->num_cpus) { if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) { --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 17 Jul 2025 11:40:59 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:59 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap and update realization order Date: Thu, 17 Jul 2025 11:40:40 +0800 Message-ID: <20250717034054.1903991-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724205222116600 Content-Type: text/plain; charset="utf-8" This commit adds a MemoryRegion alias to support PSP access to TSP SDRAM through shared memory remapping, as defined by the default SCU configuration. The TSP coprocessor exposes one DRAM alias: - remap maps PSP DRAM at 0x42e000000 (32MB) to TSP SDRAM offset 0x0 This region corresponds to the default SCU register value, which controls the mapping between PSP and coprocessor memory windows. To ensure correctness, the alias is initialized early in aspeed_soc_ast2700_realize(), before SCU and coprocessor realization. This allows TSP to reference the alias region during its SDRAM setup. Signed-off-by: Jamin Lin --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast27x0-tsp.c | 2 ++ hw/arm/aspeed_ast27x0.c | 9 +++++++++ 3 files changed, 12 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index d628a189c1..83e07582d2 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -153,6 +153,7 @@ struct Aspeed27x0TSPSoCState { MemoryRegion memory; MemoryRegion sram_mr_alias; MemoryRegion scu_mr_alias; + MemoryRegion sdram_remap_alias; =20 ARMv7MState armv7m; }; diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 6b035e2612..4c3b18695e 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -187,6 +187,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *= dev_soc, Error **errp) AST2700_TSP_SDRAM_SIZE, errp)) { return; } + /* SDRAM remap alias used by PSP to access TSP SDRAM */ + memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap_ali= as); memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index be130db5e2..0f988eaa4d 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -812,6 +812,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM * offset 0x0 * + * The TSP coprocessor uses one memory alias (remap) to access a shared + * region in the PSP DRAM: + * + * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM + * offset 0x0 + * * These mappings correspond to the default values of the SCU register= s: * * This configuration enables shared memory communication between the = PSP @@ -824,6 +830,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) memory_region_init_alias(&a->ssp.sdram_remap2_alias, OBJECT(a), "ssp.sdram.remap2", s->memory, 0x42c000000ULL, 32 * MiB); + memory_region_init_alias(&a->tsp.sdram_remap_alias, OBJECT(a), + "tsp.sdram.remap", s->memory, + 0x42e000000, 32 * MiB); } if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723865; cv=none; d=zohomail.com; s=zohoarc; b=oAJvVIwdbkPDt7XkodudG9ifSxzpXIjDDI6B5H6luuF0vq2i5B359rSqkb7AM8ii0NKROVPcEt1qoPsVz1WJ95vIUSbkra/w0yRsNzfWT2NEggr/UUVw51qCSMctsa5xN87/tO/GuM7x6wGVed9bf1aILsGNuBm7Je+pIj13FFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723865; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=R+7G0jtF9M9vv/6Dni7ochFBNEKeKhy3HdYxp9ad8mw=; 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Wed, 16 Jul 2025 23:41:53 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:59 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:59 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Date: Thu, 17 Jul 2025 11:40:41 +0800 Message-ID: <20250717034054.1903991-14-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723867549116600 Content-Type: text/plain; charset="utf-8" In the previous design, both the PSP and SSP were started together during SoC initialization. However, on real hardware, the SSP begins in a powered-= off state. The typical boot sequence involves the PSP powering up first, loading the SSP firmware binary into shared memory via DRAM remap, and then releasi= ng the SSP reset and enabling it through SCU control registers. To more accurately model this behavior in QEMU, this commit sets the "start-powered-off" property for the SSP's ARMv7M core. This change ensures the SSP remains off until explicitly enabled via the SCU, simulating the real-world flow where the PSP controls SSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c index fff95eac6a..b1dfbc4292 100644 --- a/hw/arm/aspeed_ast27x0-ssp.c +++ b/hw/arm/aspeed_ast27x0-ssp.c @@ -177,6 +177,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp) qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); + /* + * The SSP starts in a powered-down state and can be powered up + * by setting the SSP Control Register through the SCU + * (System Control Unit) + */ + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 /* SDRAM */ --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752724010309762.5037022968634; Wed, 16 Jul 2025 20:46:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFZK-00021e-1Q; Wed, 16 Jul 2025 23:46:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVV-0003lq-0X; Wed, 16 Jul 2025 23:42:11 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVO-0000g2-Nm; Wed, 16 Jul 2025 23:41:59 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:40:59 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:40:59 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 14/21] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior Date: Thu, 17 Jul 2025 11:40:42 +0800 Message-ID: <20250717034054.1903991-15-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724011200116600 Content-Type: text/plain; charset="utf-8" In the previous design, both the PSP and TSP were started together during SoC initialization. However, on real hardware, the TSP begins in a powered-= off state. The typical boot sequence involves the PSP powering up first, loading the TSP firmware binary into shared memory via DRAM remap, and then releasi= ng the TSP reset and enabling it through SCU control registers. To more accurately model this behavior in QEMU, this commit sets the "start-powered-off" property for the TSP's ARMv7M core. This change ensures the TSP remains off until explicitly enabled via the SCU, simulating the real-world flow where the PSP controls TSP boot through SCU interaction. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c index 4c3b18695e..49a49604de 100644 --- a/hw/arm/aspeed_ast27x0-tsp.c +++ b/hw/arm/aspeed_ast27x0-tsp.c @@ -177,6 +177,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp) qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); + /* + * The TSP starts in a powered-down state and can be powered up + * by setting the TSP Control Register through the SCU + * (System Control Unit) + */ + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true, + &error_abort); sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort); =20 /* SDRAM */ --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752724114167413.92575187164744; Wed, 16 Jul 2025 20:48:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFZv-0002nD-HG; Wed, 16 Jul 2025 23:46:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVV-0003lr-1O; Wed, 16 Jul 2025 23:42:11 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVS-0000g2-0W; Wed, 16 Jul 2025 23:42:03 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:41:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Date: Thu, 17 Jul 2025 11:40:43 +0800 Message-ID: <20250717034054.1903991-16-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724116206116600 Content-Type: text/plain; charset="utf-8" This commit adds SCU register support for SSP SDRAM remap control and runti= me activation. It introduces logic for the PSP to dynamically configure the ma= pping of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory communication via memory region aliases. Two MemoryRegion aliases are attached to the SCU via QOM property links: - ssp-sdram-remap1: maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM offset 0x2000000 - ssp-sdram-remap2: maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM offset 0x0 The SCU registers AST2700_SCU_SSP_CTRL_1/2 and AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfigu= ration of alias offset, base, and size. Bumps the SCU VMState version to 3. |------------------------------------------| |---------------------= -------| | PSP DRAM | | SSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 = | | remap1 base |---| | | - SCU_150: target a= ddr | | size: 32MB (SCU_14C) | | | | remap2 = | |------------------------------------------| | | |---------------------= -------| | | | | | = | | 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 = | | remap2 base | | | - SCU_148: target a= ddr | | size: 32MB (SCU_154) | |---> | remap1 = | |------------------------------------------| |---------------------= -------| Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_scu.h | 3 ++ hw/arm/aspeed_ast27x0.c | 6 ++++ hw/misc/aspeed_scu.c | 53 ++++++++++++++++++++++++++++++++++-- 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 684b48b722..408f821379 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -39,6 +39,9 @@ struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; + + MemoryRegion *ssp_sdram_remap1; + MemoryRegion *ssp_sdram_remap2; }; =20 #define AST2400_A0_SILICON_REV 0x02000303U diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 0f988eaa4d..587c042c30 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -833,6 +833,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) memory_region_init_alias(&a->tsp.sdram_remap_alias, OBJECT(a), "tsp.sdram.remap", s->memory, 0x42e000000, 32 * MiB); + object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap1", + OBJECT(&a->ssp.sdram_remap1_alias), + &error_abort); + object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2", + OBJECT(&a->ssp.sdram_remap2_alias), + &error_abort); } if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index a0ab5eed8f..df379cafbe 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -143,6 +143,14 @@ #define AST2700_HW_STRAP1_SEC2 TO_REG(0x28) #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C) =20 +/* SSP */ +#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124) +#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128) +#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148) +#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c) +#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150) +#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) + #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) #define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304) @@ -605,8 +613,8 @@ static void aspeed_scu_realize(DeviceState *dev, Error = **errp) =20 static const VMStateDescription vmstate_aspeed_scu =3D { .name =3D "aspeed.scu", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_R= EGS), VMSTATE_END_OF_LIST() @@ -618,6 +626,10 @@ static const Property aspeed_scu_properties[] =3D { DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), + DEFINE_PROP_LINK("ssp-sdram-remap1", AspeedSCUState, ssp_sdram_remap1, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("ssp-sdram-remap2", AspeedSCUState, ssp_sdram_remap2, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void aspeed_scu_class_init(ObjectClass *klass, const void *data) @@ -902,6 +914,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, int reg =3D TO_REG(offset); /* Truncate here so bitwise operations below behave as expected */ uint32_t data =3D data64; + MemoryRegion *mr; =20 if (reg >=3D ASPEED_AST2700_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -913,6 +926,36 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset, trace_aspeed_ast2700_scu_write(offset, size, data); =20 switch (reg) { + case AST2700_SCU_SSP_CTRL_1: + case AST2700_SCU_SSP_CTRL_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_1) ? + s->ssp_sdram_remap1 : s->ssp_sdram_remap2; + if (mr =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + memory_region_set_alias_offset(mr, (uint64_t) data << 4); + break; + case AST2700_SCU_SSP_REMAP_ADDR_1: + case AST2700_SCU_SSP_REMAP_ADDR_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_ADDR_1) ? + s->ssp_sdram_remap1 : s->ssp_sdram_remap2; + if (mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_address(mr, data); + break; + case AST2700_SCU_SSP_REMAP_SIZE_1: + case AST2700_SCU_SSP_REMAP_SIZE_2: + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_SIZE_1) ? + s->ssp_sdram_remap1 : s->ssp_sdram_remap2; + if (mr =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(mr, data); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -940,6 +983,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700= _SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF, [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, + [AST2700_SCU_SSP_CTRL_1] =3D 0x40000000, + [AST2700_SCU_SSP_CTRL_2] =3D 0x42C00000, + [AST2700_SCU_SSP_REMAP_ADDR_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x02000000, + [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, + [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752723954; cv=none; d=zohomail.com; s=zohoarc; b=bzrPFowOEKOjwkbydh8+YHEGFn/UfJwdMX9K2nUJ5uP9HqHe4CT8Imo+kHAWxFwCJ8vQcndtHljVNdAqw09Fh/HaikF+7yKdABdzDHaPJtZ/QK6MkRicCEvwSOU83urpMgEzCLLU+P0HGv1nO2petXR2mi3QYgPnmF7Ag0OralY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752723954; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=8/9vZWiRKPeoA7IIajWKt3lzrfpNlsu2ZwYV+7BdPz8=; b=iM3CuVfWTQVJtF85nCYFqBbkj6ZzyM2LiKX9m3uBIEMg/CR6JeI8lX3O3A8dDGZZ14kB/g+z8FtPNdpUwgFA7LZp2IS4zw0MAj3HBsoAnX0jgYVxh/UYBCia5XMtVTXV658kTtiQQVoxRJEfWpsZgTwzcDIakR1TMiOevceeWEo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752723954498205.04122946066877; Wed, 16 Jul 2025 20:45:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFYY-0000Wc-DQ; Wed, 16 Jul 2025 23:45:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVX-0003oh-9D; Wed, 16 Jul 2025 23:42:11 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVV-0000g2-Kk; Wed, 16 Jul 2025 23:42:07 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:41:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap Date: Thu, 17 Jul 2025 11:40:44 +0800 Message-ID: <20250717034054.1903991-17-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723956671116600 Content-Type: text/plain; charset="utf-8" This commit adds SCU register support for TSP SDRAM remap control and runti= me activation. Unlike SSP, the TSP does not support configurable target addres= s remapping through SCU registers. It only supports setting the PSP DRAM base and size,= which are then aliased into the TSP-visible SDRAM window. One MemoryRegion alias is attached to the SCU via QOM property link: - tsp-sdram-remap: maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDR= AM offset 0x0 The SCU registers AST2700_SCU_TSP_CTRL_1 and AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base= (alias offset) and mapping size. |------------------------------------------| |---------------------= -------| | PSP DRAM | | TSP SDRAM = | |------------------------------------------| |---------------------= -------| | 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 = | | remap base |------> | - fixed target addr= | | size: 32MB (SCU_194) | | = | |------------------------------------------| |---------------------= -------| SCU VMState version remains at 3, as it was already bumped in a previous co= mmit. Signed-off-by: Jamin Lin --- include/hw/misc/aspeed_scu.h | 1 + hw/arm/aspeed_ast27x0.c | 3 +++ hw/misc/aspeed_scu.c | 24 +++++++++++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 408f821379..5e7c80feb1 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -42,6 +42,7 @@ struct AspeedSCUState { =20 MemoryRegion *ssp_sdram_remap1; MemoryRegion *ssp_sdram_remap2; + MemoryRegion *tsp_sdram_remap; }; =20 #define AST2400_A0_SILICON_REV 0x02000303U diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 587c042c30..23096bda34 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -839,6 +839,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2", OBJECT(&a->ssp.sdram_remap2_alias), &error_abort); + object_property_set_link(OBJECT(&s->scu), "tsp-sdram-remap", + OBJECT(&a->tsp.sdram_remap_alias), + &error_abort); } if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { return; diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index df379cafbe..21a0d1ad5c 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -143,13 +143,15 @@ #define AST2700_HW_STRAP1_SEC2 TO_REG(0x28) #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C) =20 -/* SSP */ +/* SSP TSP */ #define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124) #define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128) #define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148) #define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c) #define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150) #define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) +#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168) +#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194) =20 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) @@ -630,6 +632,8 @@ static const Property aspeed_scu_properties[] =3D { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("ssp-sdram-remap2", AspeedSCUState, ssp_sdram_remap2, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("tsp-sdram-remap", AspeedSCUState, tsp_sdram_remap, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void aspeed_scu_class_init(ObjectClass *klass, const void *data) @@ -956,6 +960,22 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset, data &=3D 0x3fffffff; memory_region_set_size(mr, data); break; + case AST2700_SCU_TSP_CTRL_1: + if (s->tsp_sdram_remap =3D=3D NULL) { + return; + } + data &=3D 0x7fffffff; + /* remapped to SOC DRAM by adding data << 4 */ + memory_region_set_alias_offset(s->tsp_sdram_remap, + (uint64_t) data << 4); + break; + case AST2700_SCU_TSP_REMAP_SIZE_2: + if (s->tsp_sdram_remap =3D=3D NULL) { + return; + } + data &=3D 0x3fffffff; + memory_region_set_size(s->tsp_sdram_remap, data); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -989,6 +1009,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700= _SCU_NR_REGS] =3D { [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x02000000, [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, + [AST2700_SCU_TSP_CTRL_1] =3D 0x42E00000, + [AST2700_SCU_TSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 17 Jul 2025 11:41:00 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:00 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Date: Thu, 17 Jul 2025 11:40:45 +0800 Message-ID: <20250717034054.1903991-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724023375116600 Content-Type: text/plain; charset="utf-8" This patch implements SSP reset and power control logic in the SCU for AST2= 700. It introduces support for the following behavior: 1. SSP Reset Trigger (via SCU 0x220): - SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL= _1. 2. SSP Reset State and Source Hold (via SCU 0x120): - Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset. - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source. - Bit 1 (RST) is a software-controlled bit used to request holding SSP i= n reset. - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB) will also be asserted to indicate the SSP is being held in reset. - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly. 3. Hold Release and Power-on: - If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset= is deasserted. - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_C= TRL_0 to release the hold and power on SSP explicitly. - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution. 4. Reset Status Clear (via SCU 0x204): - The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_R= ST_CLR_1, which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active. 5. SSP Power Control Logic: - `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and = invokes `arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4). - `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, a= lso asserts RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`. 6. Register Initialization and Definitions: - Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (= 0x220), and SYS_RST_CLR_1 (0x204). - Updates the reset values for these registers during SCU initialization. The default values are based on EVB (evaluation board) register dump observ= ations. This patch enables proper modeling of SSP lifecycle management across reset, hold, and power-on states for the AST2700 SoC. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 94 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 21a0d1ad5c..50f3f6ff17 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -20,6 +20,7 @@ #include "qemu/guest-random.h" #include "qemu/module.h" #include "trace.h" +#include "target/arm/arm-powerctl.h" =20 #define TO_REG(offset) ((offset) >> 2) =20 @@ -144,6 +145,7 @@ #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C) =20 /* SSP TSP */ +#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) #define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124) #define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128) #define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148) @@ -152,6 +154,14 @@ #define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) #define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168) #define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194) +#define AST2700_SSP_TSP_ENABLE BIT(0) +#define AST2700_SSP_TSP_RST BIT(1) +#define AST2700_SSP_TSP_RST_RB BIT(8) +#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9) +#define AST2700_SSP_TSP_RST_SRC_RB BIT(10) +#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) +#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) +#define AST2700_SCU_SYS_RST_SSP BIT(30) =20 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) @@ -911,6 +921,35 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, = hwaddr offset, return s->regs[reg]; } =20 +static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid) +{ + int reg =3D AST2700_SCU_SSP_CTRL_0; + uint32_t val =3D s->regs[reg]; + + val &=3D ~AST2700_SSP_TSP_RST_SRC_RB; + if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) { + val &=3D ~AST2700_SSP_TSP_RST_RB; + arm_set_cpu_on_and_reset(cpuid); + } + + s->regs[reg] =3D val; +} + +static void handle_ssp_tsp_off(struct AspeedSCUState *s, int cpuid) +{ + int reg =3D AST2700_SCU_SSP_CTRL_0; + uint32_t val =3D s->regs[reg]; + + val |=3D AST2700_SSP_TSP_RST_RB; + val |=3D AST2700_SSP_TSP_RST_SRC_RB; + if (val & AST2700_SSP_TSP_RST) { + val |=3D AST2700_SSP_TSP_RST_HOLD_RB; + } + arm_set_cpu_off(cpuid); + + s->regs[reg] =3D val; +} + static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset, uint64_t data64, unsigned size) { @@ -919,6 +958,9 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, /* Truncate here so bitwise operations below behave as expected */ uint32_t data =3D data64; MemoryRegion *mr; + uint32_t active; + uint32_t oldval; + int cpuid; =20 if (reg >=3D ASPEED_AST2700_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -930,6 +972,40 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset, trace_aspeed_ast2700_scu_write(offset, size, data); =20 switch (reg) { + case AST2700_SCU_SSP_CTRL_0: + cpuid =3D 4; + oldval =3D s->regs[reg]; + data &=3D 0xff; + active =3D oldval ^ data; + + /* + * If reset bit is being released (1 -> 0) and no other reset sour= ce + * is active, clear HOLD_RB and power on the corresponding CPU. + */ + if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST= )) { + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB; + if ((oldval & AST2700_SSP_TSP_RST_RB) && + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) { + handle_ssp_tsp_on(s, cpuid); + } + } + + /* + * If ENABLE bit is newly set and reset state is ready, + * clear HOLD_RB and power on the corresponding CPU. + */ + if ((active & AST2700_SSP_TSP_ENABLE) && + (oldval & AST2700_SSP_TSP_RST_RB) && + (oldval & AST2700_SSP_TSP_RST_HOLD_RB) && + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) { + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB; + handle_ssp_tsp_on(s, cpuid); + } + + /* Auto-clear the ENABLE bit (one-shot behavior) */ + data &=3D ~AST2700_SSP_TSP_ENABLE; + s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff); + return; case AST2700_SCU_SSP_CTRL_1: case AST2700_SCU_SSP_CTRL_2: mr =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_1) ? @@ -976,6 +1052,22 @@ static void aspeed_ast2700_scu_write(void *opaque, hw= addr offset, data &=3D 0x3fffffff; memory_region_set_size(s->tsp_sdram_remap, data); break; + case AST2700_SCU_SYS_RST_CTRL_1: + oldval =3D s->regs[reg]; + active =3D data & ~oldval; + if (active & AST2700_SCU_SYS_RST_SSP) { + handle_ssp_tsp_off(s, 4); + } + s->regs[reg] |=3D active; + return; + case AST2700_SCU_SYS_RST_CLR_1: + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_1]; + active =3D data & oldval; + if (active & AST2700_SCU_SYS_RST_SSP) { + handle_ssp_tsp_on(s, 4); + } + s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active; + return; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -1003,6 +1095,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF, [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, + [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_SSP_CTRL_1] =3D 0x40000000, [AST2700_SCU_SSP_CTRL_2] =3D 0x42C00000, [AST2700_SCU_SSP_REMAP_ADDR_1] =3D 0x02000000, @@ -1011,6 +1104,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_TSP_CTRL_1] =3D 0x42E00000, [AST2700_SCU_TSP_REMAP_SIZE_2] =3D 0x02000000, + [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 17 Jul 2025 11:41:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers Date: Thu, 17 Jul 2025 11:40:46 +0800 Message-ID: <20250717034054.1903991-19-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724057636116600 Content-Type: text/plain; charset="utf-8" This patch implements TSP reset and power control logic in the SCU module for AST2700. It introduces support for the following behavior: 1. TSP Reset Trigger (via SCU 0x224): - TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_= 2. 2. TSP Reset State and Source Hold (via SCU 0x160): - Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset. - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source. - Bit 1 (RST) is a software-controlled bit used to request holding TSP i= n reset. - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB) will also be asserted to indicate the TSP is being held in reset. - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly. 3. Hold Release and Power-on: - If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset= is deasserted. - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_C= TRL_0 to release the hold and power on TSP explicitly. - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution. 4. Reset Status Clear (via SCU 0x224): - The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RS= T_CLR_2, which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active. 5. TSP Power Control Logic: - handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and in= vokes arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5). - handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, als= o asserts RST_HOLD_RB and invokes arm_set_cpu_off(cpuid). The default values are based on EVB (evaluation board) register dump observ= ations. TSP reset control shares the same helper functions and register bit layout = as SSP, with logic selected by cpuid and distinct external reset sources. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 50f3f6ff17..ee31a9aabd 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -152,6 +152,7 @@ #define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c) #define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150) #define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154) +#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160) #define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168) #define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194) #define AST2700_SSP_TSP_ENABLE BIT(0) @@ -162,6 +163,9 @@ #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) #define AST2700_SCU_SYS_RST_SSP BIT(30) +#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220) +#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224) +#define AST2700_SCU_SYS_RST_TSP BIT(9) =20 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) @@ -923,7 +927,7 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, h= waddr offset, =20 static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid) { - int reg =3D AST2700_SCU_SSP_CTRL_0; + int reg =3D (cpuid =3D=3D 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TS= P_CTRL_0; uint32_t val =3D s->regs[reg]; =20 val &=3D ~AST2700_SSP_TSP_RST_SRC_RB; @@ -937,7 +941,7 @@ static void handle_ssp_tsp_on(struct AspeedSCUState *s,= int cpuid) =20 static void handle_ssp_tsp_off(struct AspeedSCUState *s, int cpuid) { - int reg =3D AST2700_SCU_SSP_CTRL_0; + int reg =3D (cpuid =3D=3D 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TS= P_CTRL_0; uint32_t val =3D s->regs[reg]; =20 val |=3D AST2700_SSP_TSP_RST_RB; @@ -973,7 +977,8 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset, =20 switch (reg) { case AST2700_SCU_SSP_CTRL_0: - cpuid =3D 4; + case AST2700_SCU_TSP_CTRL_0: + cpuid =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_0) ? 4 : 5; oldval =3D s->regs[reg]; data &=3D 0xff; active =3D oldval ^ data; @@ -1068,6 +1073,24 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, } s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active; return; + case AST2700_SCU_SYS_RST_CTRL_2: + data &=3D 0x00001fff; + oldval =3D s->regs[reg]; + active =3D data & ~oldval; + if (data & AST2700_SCU_SYS_RST_TSP) { + handle_ssp_tsp_off(s, 5); + } + s->regs[reg] |=3D data; + return; + case AST2700_SCU_SYS_RST_CLR_2: + data &=3D 0x00001fff; + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_2]; + active =3D data & oldval; + if (active & AST2700_SCU_SYS_RST_TSP) { + handle_ssp_tsp_on(s, 5); + } + s->regs[AST2700_SCU_SYS_RST_CTRL_2] &=3D ~active; + return; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -1102,9 +1125,11 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST27= 00_SCU_NR_REGS] =3D { [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x02000000, [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000, [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x02000000, + [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_TSP_CTRL_1] =3D 0x42E00000, [AST2700_SCU_TSP_REMAP_SIZE_2] =3D 0x02000000, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, + [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752723955080872.7456743026763; Wed, 16 Jul 2025 20:45:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ucFZ5-0001GB-Td; Wed, 16 Jul 2025 23:45:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVn-000447-BO; Wed, 16 Jul 2025 23:42:23 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ucFVk-0000g2-Fr; Wed, 16 Jul 2025 23:42:22 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 11:41:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Date: Thu, 17 Jul 2025 11:40:47 +0800 Message-ID: <20250717034054.1903991-20-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752723956474116600 Content-Type: text/plain; charset="utf-8" The updated boot ROM includes logic to initialize and enable SSP/TSP using = SCU registers, based on reserved-memory regions defined in the device tree. Its source code is available at: https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c21= 02fa98e Build Information: Build Date : Jul 17 2025 02:26:07 FW Version : git-f9eb0bb Signed-off-by: Jamin Lin --- pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/pc-bios/ast27x0_bootrom.bin b/pc-bios/ast27x0_bootrom.bin index 0b9b3a2360e375bb6007ecdf13b39d931870f6fa..339ae7ca8759b9e4e0100bf6e12= 3963bccab4920 100644 GIT binary patch delta 6044 zcmaJ_3v^V~x&F^N!({RxB=3Dg9`BqV3@BE%$wydSijJmjIFLOS(Y#gf-xB9Vk-5EbeS zm{nU*>v4|_azP_y-I7__QUOiwZELF7dc}LM#s`9clLQrncBS&l2x0EG&rCvUS9?}Y z&VRoBzxMywd!HG4Xx~qS{ofIUcJ^Iin`o$EZwO1OKGlPQnj@{UcWV>zpF`92G@|Vu2DyJ zr+(>Rk&cQU6|-VJ+HKnYf=3DK6nD!Itss83GSYc4It} z$lP76s4f_`T@Bca5Uo)c3^$4^-%q2yVJ!-G>eW^-UxI?mk1DTR4(t2+busQ-Ka_Gq zqM>h?^QO|!*BXCTgt{918m-f*CUOtY4+MJCV5|=3DjNTK+3TSc;O6D>zZPz-JueL^A+ zfBNxsDFPL5!wVnOl-R@6Wl%Wsrl4}BbmZwIa?i(oQk=3DI+bI$603)lq>vv|LRB1NR) zJ&2^HV|BR7`KwV=3D#o)IhYF9ENfmxx$9uc!eR8Zz7Z#de48@()%_Z>LR@jjv=3DKIRL_kB9Uo zB0`tIrwA^sFUDzrdl%=3D8fD@WS2xUB!AH5#vg+=3DoynEALimL8=3DN_{I(hkO>;siuQ>p zby*mBCcx_^Iylo`jpc1QR+D&4;LCko~Mnq z%vL{V$8?#g<8*PhdR$|14~|Ijh@{zTMC3KyJ<;k1%r?vF`YSx(v2_cfP$9H$LrUXH zidEm5qA^1&X7~(d$SaeFDFNZW>z9#gBA%On9;I$V*bvTa&UaayD7i8jIA}uuHtbQ# z6{3bUsSWzzyDZXL7`Fz)bTL*1;kkOV;`af&@cpX(OLtdeaj3!KP}@Jb`Q3f5 zV<8!m)_feyBVVpe-tDva1QNVFKXowR6R3!XdQ?gbEomn2D4U#>uw5;w9Rau6xMUBh|GZ_-l!7?f*5Ncl31{T>t5jC+E{FR`=3DwjGU1C-Z^S1cus&v zlWC990`@Ds^Tk|1GHvm!A}mdaXFm$NT}WoX4ok%Ucfy_u-m^4 zM61%0$mmL^4a=3D?t?A1CQiwwUmt!pLKA;SE~4F$hLhHW4u^D$I}BHR`Blt&4Y!WKga`? znxy#m5MMVGznnyVLQHrO%XnS~FW((qlbc`dpV}6A>1olwW>kG)v-&l<-K6^9xvY@t zE9FYCi=3D6;g3Cs;_aR_TSs~2hnm2as?;rNy77A#CO9{*^Z>Z<|o5TZbW%D3G(w5dOh z{5N4+9rrDrQfh|L@P1yi8%4#>`z1kJDk)n*PxE*AZi{*mJ%T>=3DqxStN1{(Yr+3v0; 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spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752724199; cv=none; d=zohomail.com; s=zohoarc; b=T+T1h7cckNU7CspxKaybg4NBbNhdD12twKvtUhWqgj1jJHJITI4XR8ceT1pXeMp3bVk5fAa9Nqw+B3SfKhomuwkuGhIwZ+xYWeOcMUA0bZESs7bKvQuJQJTDpywNQuF/P2/cQKEXH+jkHnbBMpxG9x/zXKV0CIb52G33kLaCb6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752724199; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=GrNG2wdPGTInpO9GEAjnbzqFeEttesCpLgsubl+6CUQ=; b=RmPKyBznJpxzT64XHMDLUtoEPY7RfFSOLpO2akJP3CDcWO7StkqVBd8PjGSXSVQdabFO81OJo/AasBrerq8E+QaI63WFOC0hfQ5NrZvmT7q8Tuy+6tXLEyFZ41AiSbJpJAVZZEAQeOPQk6kIrLCU0+K1+8KNyDdp3QCZo6SgWa8= ARC-Authentication-Results: i=1; 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Thu, 17 Jul 2025 11:41:01 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:01 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test Date: Thu, 17 Jul 2025 11:40:48 +0800 Message-ID: <20250717034054.1903991-21-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724201092116600 Content-Type: text/plain; charset="utf-8" SSP and TSP now boot in a powered-off state by default. Enabling them requi= res the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. Th= is behavior aligns with real hardware. However, the current functional test framework design does not support swit= ching the active VM console after launch. For example, when the PSP is launched f= irst to enable SSP via SCU, the test framework cannot dynamically attach to the = SSP console afterward to verify its behavior. Due to this limitation, the test case for AST2700FC has been modified to use vBootROM (`ast27x0_bootrom.bin`) instead of manually loading boot images and firmwares via `-device loader`. The vBootROM integrates boot sequencing for PSP, TSP, and SSP and sets up SCU configuration as part of its flow, enabli= ng more realistic full-system testing without relying on console switching. Signed-off-by: Jamin Lin --- .../test_aarch64_aspeed_ast2700fc.py | 47 +------------------ 1 file changed, 1 insertion(+), 46 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed_ast2700fc.py b/tests/func= tional/test_aarch64_aspeed_ast2700fc.py index b85370e182..d7d50eda4d 100755 --- a/tests/functional/test_aarch64_aspeed_ast2700fc.py +++ b/tests/functional/test_aarch64_aspeed_ast2700fc.py @@ -72,52 +72,7 @@ def do_ast2700fc_tsp_test(self): '[72c02000] 06010103') =20 def start_ast2700fc_test(self, name): - ca35_core =3D 4 - uboot_size =3D os.path.getsize(self.scratch_file(name, - 'u-boot-nodtb.bin')) - uboot_dtb_load_addr =3D hex(0x400000000 + uboot_size) - - load_images_list =3D [ - { - 'addr': '0x400000000', - 'file': self.scratch_file(name, - 'u-boot-nodtb.bin') - }, - { - 'addr': str(uboot_dtb_load_addr), - 'file': self.scratch_file(name, 'u-boot.dtb') - }, - { - 'addr': '0x430000000', - 'file': self.scratch_file(name, 'bl31.bin') - }, - { - 'addr': '0x430080000', - 'file': self.scratch_file(name, 'optee', - 'tee-raw.bin') - } - ] - - for load_image in load_images_list: - addr =3D load_image['addr'] - file =3D load_image['file'] - self.vm.add_args('-device', - f'loader,force-raw=3Don,addr=3D{addr},file=3D= {file}') - - for i in range(ca35_core): - self.vm.add_args('-device', - f'loader,addr=3D0x430000000,cpu-num=3D{i}') - - load_elf_list =3D { - 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'), - 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf') - } - - for cpu_num, key in enumerate(load_elf_list, start=3D4): - file =3D load_elf_list[key] - self.vm.add_args('-device', - f'loader,file=3D{file},cpu-num=3D{cpu_num}') - + self.vm.add_args('-bios', 'ast27x0_bootrom.bin') self.do_test_aarch64_aspeed_sdk_start( self.scratch_file(name, 'image-bmc')) =20 --=20 2.43.0 From nobody Fri Sep 5 20:21:05 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 17 Jul 2025 11:41:02 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 17 Jul 2025 11:41:02 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , Subject: [PATCH v1 21/21] docs: Add support vbootrom for ast2700fc Date: Thu, 17 Jul 2025 11:40:49 +0800 Message-ID: <20250717034054.1903991-22-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> References: <20250717034054.1903991-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752724021252116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 41 ++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index bf18c56347..bc836e486f 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,4 +1,4 @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, `= `bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2= -bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-fir= ework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonor= apass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-b= mc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``,= ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-b= mc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``qu= anta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``su= permicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspo= on-bmc``, ``yosemitev2-bmc``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of various OpenPOWER systems and @@ -243,7 +243,7 @@ under Linux), use : =20 -M ast2500-evb,bmc-console=3Duart3 =20 -Aspeed 2700 family boards (``ast2700-evb``) +Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards. @@ -360,6 +360,14 @@ Booting the ast2700fc machine AST2700 features four Cortex-A35 primary processors and two Cortex-M4 copr= ocessors. **ast2700-evb** machine focuses on emulating the four Cortex-A35 primary p= rocessors, **ast2700fc** machine extends **ast2700-evb** by adding support for the tw= o Cortex-M4 coprocessors. +There are two methods to boot the ast2700fc machine. + +Manual boot using ``-device loader``: + +In this approach, users manually load firmware and assign entry points via= QEMU loader devices. +By default, the PSP begins execution at address ``0x430000000``, the load = address of the bl31 +firmware. The SSP and TSP start in the powered-off state and must be expli= citly enabled by the +PSP through writes to SCU registers. =20 Steps to boot the AST2700fc machine: =20 @@ -370,8 +378,8 @@ Steps to boot the AST2700fc machine: * bl31.bin * optee/tee-raw.bin * image-bmc - * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5) - * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6) + * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5) + * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6) =20 2. Execute the following command to start ``ast2700fc`` machine: =20 @@ -385,17 +393,38 @@ Steps to boot the AST2700fc machine: -device loader,force-raw=3Don,addr=3D$((0x400000000 + ${UBOOT_SIZE}= )),file=3D${IMGDIR}/u-boot.dtb \ -device loader,force-raw=3Don,addr=3D0x430000000,file=3D${IMGDIR}/b= l31.bin \ -device loader,force-raw=3Don,addr=3D0x430080000,file=3D${IMGDIR}/o= ptee/tee-raw.bin \ + -device loader,addr=3D0x42C000000,file=3D${IMGDIR}/zephyr-aspeed-ss= p.bin,force-raw=3Don \ + -device loader,addr=3D0x42E000000,file=3D${IMGDIR}/zephyr-aspeed-ts= p.bin,force-raw=3Don \ -device loader,cpu-num=3D0,addr=3D0x430000000 \ -device loader,cpu-num=3D1,addr=3D0x430000000 \ -device loader,cpu-num=3D2,addr=3D0x430000000 \ -device loader,cpu-num=3D3,addr=3D0x430000000 \ -drive file=3D${IMGDIR}/image-bmc,if=3Dmtd,format=3Draw \ - -device loader,file=3D${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=3D4 \ - -device loader,file=3D${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=3D5 \ -serial pty -serial pty -serial pty \ -snapshot \ -S -nographic =20 +Boot using a virtual boot ROM (-bios): + +In this method, the virtual boot ROM (vbootrom) handles the full initializ= ation sequence. +It starts the PSP, which then enables the SSP and TSP by programming the a= ppropriate SCU +registers, following the hardware behavior. + +Execute the following command to start ``ast2700fc`` machine: + +.. code-block:: bash + + IMGDIR=3Dast2700-default + + $ qemu-system-aarch64 -M ast2700fc \ + -bios ast27x0_bootrom.bin \ + -drive file=3D${IMGDIR}/image-bmc,if=3Dmtd,format=3Draw \ + -serial pty -serial pty -serial pty \ + -snapshot \ + -S -nographic + +Serial Console Redirection: + After launching QEMU, serial devices will be automatically redirected. Example output: =20 --=20 2.43.0