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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH 32/48] hw/misc/xlnx-versal-crl: split into base/concrete classes Date: Wed, 16 Jul 2025 11:54:14 +0200 Message-ID: <20250716095432.81923-33-luc.michel@amd.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250716095432.81923-1-luc.michel@amd.com> References: <20250716095432.81923-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|DS0PR12MB8456:EE_ X-MS-Office365-Filtering-Correlation-Id: 9555bf88-a1de-464f-1898-08ddc44efd3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?u1ovBLsGAW9gTH8yOSCOVGpOu0yvLka8oZU2oJOGRmHyQJC9UR/mBTP5tBt3?= =?us-ascii?Q?p7lc6u0wSMGXM3hp+gNPg9VzVhzmcHPbB6uK7btA+BYpL6+hM3CCQYb3wuBB?= =?us-ascii?Q?A646nRSROwHu6LCH7zY8LMhH7t5KwsuLXMm0Omx8IKkVmQNes+z6IoRgHEMq?= =?us-ascii?Q?cEnPQahWY8g2HyhY/nFuUYZq/taSyNAZJ/Xv7FlANrYFzBCqX/9lbI7RI/kf?= =?us-ascii?Q?G3LMrw0Se0H2APn2MDqvt0+Rd6bnaGiaCg0MOsXNWyzRlzzCTVl95ZeDz0Bg?= =?us-ascii?Q?RhcIOrJRB4Fk0b2XG5YgD5o49X7Flju4o5H7KnnDttgauFtOARmUXvkV6yKN?= =?us-ascii?Q?SErds7UM3uWjI/rCZa3i9945COUbqIYbUD/z55fBtLmFUw9N3OyTxs92t4+x?= =?us-ascii?Q?OWCGkEWG0BDHf3DluAB7OgBUaOxmQPtvy5RgmM5KSnmwX0EjemiF4su19TKo?= =?us-ascii?Q?FyD2VWC9jf6ZuS6/qCoIKM1+LCEwnkEkiQmjQvRzeolRX4xodgYdGeKzm+Q7?= =?us-ascii?Q?7LqBdoT2YWdWgDTK6VbmsvRjKZ4B+ydv1clBPqkH/fbEKYAWt2S77hfWIemB?= =?us-ascii?Q?Z2vtqXrAOPr5e2NT5Xtr8IwqVGWFuGJy4BiMm1Hmwx9+wa6lrIHF+4DLuVHV?= =?us-ascii?Q?OFsqH9XSzJ+Z5XCHx1u6Tibe2RvFYVOqM4FV3GnK6b+5Kgi5jAanfmAzh26p?= =?us-ascii?Q?bmxmetRve+owLzozrUSzcqYNTWFQRUh/i3LnuGwV9WHdbuND00ievFUh4RMd?= =?us-ascii?Q?/Xo/ueUGmYpSmsK0wP22b0u4urgxD/LWU5kIA/l9twxsL4I68tn0SGfTsOH+?= =?us-ascii?Q?sxCnsmLHwx0LjNs2b4eU/aq4is0/GQhooIc7enLSvUUUQvSU5y5KLCph5e+O?= =?us-ascii?Q?rm4lBGKtyKxhP81pZJNhPGYvpHuTIYQBA5d0j1PRI+gH+l7ji+HKUpIeJcRg?= =?us-ascii?Q?LsdvZRVP/QCmyGf7spL8PQ7325AQZOLJxn//pk0rNS3F/V13QQs0V2ENB9/Q?= =?us-ascii?Q?c4GhJbgFLtXc4DDCjS6eh/6Hzz28imz+hGYOAA7oHe3dGgIgoIYEXZLMD33O?= =?us-ascii?Q?XI3/Q2qDQlxOI3fEOs8yvkM7oUzFxFlk4Bv4jqxCSmgnlqR+bUE9yDkusygn?= =?us-ascii?Q?bvXxGnf3mxTi9Kpv02PogmE+SdlSUWtQ2E2+si1CdrvqYtdsKieUR/ZOwHQH?= =?us-ascii?Q?n7pR3Q3E0U9T3igTuOYC5mSQCYsbqf9Zy/FGcUVZQXQ1+u9hQ0P+N9Te4eFm?= =?us-ascii?Q?A9GFI0sFBXS3hFPMmB5fC7xREBafwgyhxgG5JWcjvu0Hg28Sx0aFghV97ILY?= =?us-ascii?Q?9SYILly3uFlWH0Ysy/Z/7ZcOLeNBWPhqjeXSVJzzdgRC6sbr1zk3Q5lWtXRy?= =?us-ascii?Q?d7tcmlSeFHayWLwdteRDjENHMMGBXwwh1t6gZfXaGgsXdsSKWG33DQJybhnG?= =?us-ascii?Q?lpNp66uoehDp9HFkVgm45nDicjOTMreAkHb/atgrpIE6T8/eGLoXvfEwNGz8?= =?us-ascii?Q?7BrNGo0RBmhhYOWraGt05IbsrZpniibyhKJO?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 09:56:09.0860 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9555bf88-a1de-464f-1898-08ddc44efd3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8456 Received-SPF: permerror client-ip=2a01:111:f403:2417::631; envelope-from=Luc.Michel@amd.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1752660038067116600 Content-Type: text/plain; charset="utf-8" Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/misc/xlnx-versal-crl.h | 31 ++++++++++++++++++-- hw/misc/xlnx-versal-crl.c | 48 +++++++++++++++++++------------ 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h index dba6d3585d1..2b39d203a67 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -1,21 +1,27 @@ /* * QEMU model of the Clock-Reset-LPD (CRL). * * Copyright (c) 2022 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * SPDX-License-Identifier: GPL-2.0-or-later * * Written by Edgar E. Iglesias */ #ifndef HW_MISC_XLNX_VERSAL_CRL_H #define HW_MISC_XLNX_VERSAL_CRL_H =20 #include "hw/sysbus.h" #include "hw/register.h" #include "target/arm/cpu-qom.h" +#include "hw/arm/xlnx-versal-version.h" =20 +#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" + +OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass, + XLNX_VERSAL_CRL_BASE) OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) =20 REG32(ERR_CTRL, 0x0) FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) REG32(IR_STATUS, 0x4) @@ -214,22 +220,43 @@ REG32(PSM_RST_MODE, 0x370) =20 #define CRL_R_MAX (R_PSM_RST_MODE + 1) =20 #define RPU_MAX_CPU 2 =20 -struct XlnxVersalCRL { +struct XlnxVersalCRLBase { SysBusDevice parent_obj; + + RegisterInfoArray *reg_array; + uint32_t *regs; +}; + +struct XlnxVersalCRLBaseClass { + SysBusDeviceClass parent_class; +}; + +struct XlnxVersalCRL { + XlnxVersalCRLBase parent_obj; qemu_irq irq; =20 struct { ARMCPU *cpu_r5[RPU_MAX_CPU]; DeviceState *adma[8]; DeviceState *uart[2]; DeviceState *gem[2]; DeviceState *usb; } cfg; =20 - RegisterInfoArray *reg_array; uint32_t regs[CRL_R_MAX]; RegisterInfo regs_info[CRL_R_MAX]; }; + +static inline const char *xlnx_versal_crl_class_name(VersalVersion ver) +{ + switch (ver) { + case VERSAL_VER_VERSAL: + return TYPE_XLNX_VERSAL_CRL; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index f288545967a..be89e0da40d 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -296,21 +296,21 @@ static const RegisterAccessInfo crl_regs_info[] =3D { .reset =3D 0x1, .rsvd =3D 0xf8, } }; =20 -static void crl_reset_enter(Object *obj, ResetType type) +static void versal_crl_reset_enter(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); unsigned int i; =20 for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { register_reset(&s->regs_info[i]); } } =20 -static void crl_reset_hold(Object *obj, ResetType type) +static void versal_crl_reset_hold(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); =20 crl_update_irq(s); } @@ -323,24 +323,26 @@ static const MemoryRegionOps crl_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, }; =20 -static void crl_init(Object *obj) +static void versal_crl_init(Object *obj) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *xvcb =3D XLNX_VERSAL_CRL_BASE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); int i; =20 - s->reg_array =3D + xvcb->reg_array =3D register_init_block32(DEVICE(obj), crl_regs_info, ARRAY_SIZE(crl_regs_info), s->regs_info, s->regs, &crl_ops, XLNX_VERSAL_CRL_ERR_DEBUG, CRL_R_MAX * 4); - sysbus_init_mmio(sbd, &s->reg_array->mem); + xvcb->regs =3D s->regs; + sysbus_init_mmio(sbd, &xvcb->reg_array->mem); sysbus_init_irq(sbd, &s->irq); =20 for (i =3D 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, (Object **)&s->cfg.cpu_r5[i], @@ -375,45 +377,53 @@ static void crl_init(Object *obj) OBJ_PROP_LINK_STRONG); } =20 static void crl_finalize(Object *obj) { - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(obj); register_finalize_block(s->reg_array); } =20 -static const VMStateDescription vmstate_crl =3D { +static const VMStateDescription vmstate_versal_crl =3D { .name =3D TYPE_XLNX_VERSAL_CRL, .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), VMSTATE_END_OF_LIST(), } }; =20 -static void crl_class_init(ObjectClass *klass, const void *data) +static void versal_crl_class_init(ObjectClass *klass, const void *data) { - ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 - dc->vmsd =3D &vmstate_crl; - - rc->phases.enter =3D crl_reset_enter; - rc->phases.hold =3D crl_reset_hold; + dc->vmsd =3D &vmstate_versal_crl; + rc->phases.enter =3D versal_crl_reset_enter; + rc->phases.hold =3D versal_crl_reset_hold; } =20 -static const TypeInfo crl_info =3D { - .name =3D TYPE_XLNX_VERSAL_CRL, +static const TypeInfo crl_base_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL_BASE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(XlnxVersalCRL), - .class_init =3D crl_class_init, - .instance_init =3D crl_init, + .instance_size =3D sizeof(XlnxVersalCRLBase), + .class_size =3D sizeof(XlnxVersalCRLBaseClass), .instance_finalize =3D crl_finalize, + .abstract =3D true, +}; + +static const TypeInfo versal_crl_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL, + .parent =3D TYPE_XLNX_VERSAL_CRL_BASE, + .instance_size =3D sizeof(XlnxVersalCRL), + .instance_init =3D versal_crl_init, + .class_init =3D versal_crl_class_init, }; =20 static void crl_register_types(void) { - type_register_static(&crl_info); + type_register_static(&crl_base_info); + type_register_static(&versal_crl_info); } =20 type_init(crl_register_types) --=20 2.50.0