From nobody Sat Nov 15 11:14:43 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1752659826; cv=pass; d=zohomail.com; s=zohoarc; b=R5w36r2DJknnTO6zKLvHrNPtL0rbFQN70zf7n8MliHItz8+fB0L8fVe5AO1a27IfEhB8UciKtVnGFCfN8VWy8TetBUAQJKEi1TqsbhPqSHnVy7blk45UPw9pvDwaz53w2ne8p6/rcCcoTGRcQxcp7aB6ehry13ST1NgTUGzI02Q= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752659826; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XRI0Hk65XgOooBzAm1qzF4mAt2gixf9r3c6mINbJpi0=; b=QQI3AzOVBMvhQgHUoS/QAm2XEL9tob4nrxW59VccBjeE98H848eQIitC9bRC21yssQDVzRS8tG6ei6mOh8zVZ8jtUEWqLLSsUz7sIoUrr5Te4ds5Bi48mYPHIzbp9astAizEF88Id744x577T+gaEW6Gjae/vv6+UkiREGhFnWs= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752659826282699.3457456850552; Wed, 16 Jul 2025 02:57:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ubysa-0002t7-32; Wed, 16 Jul 2025 05:56:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubys3-0001uR-Cj; Wed, 16 Jul 2025 05:56:16 -0400 Received: from mail-bn8nam04on20609.outbound.protection.outlook.com ([2a01:111:f403:2408::609] helo=NAM04-BN8-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubyrr-0006gT-N1; Wed, 16 Jul 2025 05:56:06 -0400 Received: from BYAPR05CA0031.namprd05.prod.outlook.com (2603:10b6:a03:c0::44) by SN7PR12MB7881.namprd12.prod.outlook.com (2603:10b6:806:34a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8922.25; Wed, 16 Jul 2025 09:55:59 +0000 Received: from SJ5PEPF00000208.namprd05.prod.outlook.com (2603:10b6:a03:c0:cafe::4c) by BYAPR05CA0031.outlook.office365.com (2603:10b6:a03:c0::44) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.17 via Frontend Transport; Wed, 16 Jul 2025 09:55:58 +0000 Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF00000208.mail.protection.outlook.com (10.167.244.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8922.22 via Frontend Transport; Wed, 16 Jul 2025 09:55:57 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 16 Jul 2025 04:55:57 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 16 Jul 2025 04:55:56 -0500 Received: from XFR-LUMICHEL-L2.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Wed, 16 Jul 2025 04:55:55 -0500 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aFXEtHuknSu/V4v6nRwJml493g5lG78E/zm6o/arU1virHa0blirDo9SkrObV72HItdmeAJF9O8Q6yBC2i8oVJGTzJUKUUSatK7inl+w2+n8CpDkU9BIEC47QYPohuPa1AAnGuY3LEm/jpe0UV9YvVtsnWlw/ewhPUtMpsQiKMwUJfaXTdX+2Omcda9s4fRodckLcBfLC/lD0nuCM88iVPlooq6HlZKyvADYQXkqZ9T4aF7n0i7rUpwGLMf9DJRenfCW0/kt8KSHdVgURrpRYtrv9KD4z6J+/bZpyf6m3cQDyYw/TSOfsHb6phgOFU8QQAgUgxSHnbDLHQWspKJhYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XRI0Hk65XgOooBzAm1qzF4mAt2gixf9r3c6mINbJpi0=; b=eqWpFQTBEoBlVCIPKGUrCZ+0N8nDLHUKyQ2dmMGipdw0engRqYQfLf9zrylxEYBcsI5LObJTPnlSAv1ms6QQ6+I3OL3wzEIh3LOmsRmBycHrNTj91Ax0656AqurRyp3WRoLCatPFIqYTMXSubjGk8H+cVuJtmOv1QHwxryVm6ffiCkFJRo4y6yLDM3MU9dKU8LxELz7fKurVXF1UVkQ422EKQY0XvNcosGH3yaLsGTnNxzPsEDJuT86ekaxI9qQrWSJGB0RfCRR7F3lPqBX7z19wS7hTGj28hFR2HWImKyog2CCfPJprvlVNRfzz2MSwuX5wNyFp1fbvch+3VweQRg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=nongnu.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XRI0Hk65XgOooBzAm1qzF4mAt2gixf9r3c6mINbJpi0=; b=GGd3X0IvgG88r2z0DwSMCHKZD8XFEzl5cR01r2Kxz3y06t0um5iGWTR23EPesWtB+PytglbNhbhmeWKcyH6Qv008e0QAGGfzp3FXAfFlFaAOV+HHlqM4jgbssBc24KjGAau0gx4QR9MdD5PFh4VyzbiNrK8CAInhDOjrQufi8EU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Luc Michel To: , CC: Luc Michel , Peter Maydell , Francisco Iglesias , "Edgar E . Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH 29/48] hw/arm/xlnx-versal: ddr: refactor creation Date: Wed, 16 Jul 2025 11:54:11 +0200 Message-ID: <20250716095432.81923-30-luc.michel@amd.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250716095432.81923-1-luc.michel@amd.com> References: <20250716095432.81923-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000208:EE_|SN7PR12MB7881:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b80f144-a2c1-4515-5f4a-08ddc44ef6a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?m06npKsoWD9oHHFXH2KRr+vTFtXiDGo1D6JGu8b1NWoWq9L0ueqe0+TwA3W5?= =?us-ascii?Q?JwHO6CrEr6W4N1JmkwKVYHQBeDU4VSlNhYeWKk6h31vEvqd2qNbfIgrHekSg?= =?us-ascii?Q?FFNK11jr4DHZQzAX8DsPGy8NvM1qx0IjbmWEUi3MXZkortEUat6KXU5Qne0d?= =?us-ascii?Q?cP0JAX5doL58p1V+i2F94mUIlguzoigxzgJAV6oeMeL/oN62PdLIS80Jkh/l?= =?us-ascii?Q?+jM73do5FCnqWFvLGLVhYCnONRb3Qc8b2yAqHXaA5WVXqXGESAOmwGQOXv6g?= =?us-ascii?Q?xZ2hc7VRlTiZ1Yn8oshWcK3YuiE38CO6YHsL2DjDffugSvjgRv9IujumalzQ?= =?us-ascii?Q?0nhoUvlET976otY2YhpZA+2hIkvI7D1ISvEZuz0wbQMZzpcZQ0C0cuIXMMVp?= =?us-ascii?Q?xusTeaSXwAOr4Fum6SWu94lzH0811Yag+VJvDPZpEjWlDZ8E39JH66+9ZAXY?= =?us-ascii?Q?+Wj6xuOCYX7fuLBveerGEvne9fE9c4E6NdWQbywDSrTEJVCAa632U3A/VmCt?= =?us-ascii?Q?XTXkjBKXd/GcezjlOe6cdR8XpBi9uu2Yne45OZ+gQCGEain0b7+zbAkt8cvY?= =?us-ascii?Q?kpcCRSJz2UKEu0iM+PkWkWJm6udyZvRlDN7NtqAtSxMsp/5n2ZKw1S1i7Fsx?= =?us-ascii?Q?XAQJ7AMDmyKmD26VfZUOyJOFUXuTGQh9rhkKoy34zprLw7GaoUxxvDReZNuJ?= =?us-ascii?Q?2h4uDaDVRi4hU6TaaRJISsBwRmM8z3cF7DHc609K0jVElLNgwj5hQKHqetFr?= =?us-ascii?Q?af5eqJTub38B5UXpgUGeFQqmH7MMQs9bvOpKeNkByjLVtfOgGpTA9h2wRuLa?= =?us-ascii?Q?egkQ+lGDh5Hvc/IQqZDgJbHXB6JG+mGqZyE92JiR38jT/NJV279xsTAuP3yQ?= =?us-ascii?Q?oUev/v1n4dGHLsg+t/ksk+o6fElYzbbGL9VVZhSSKM/+O1aly42GSr6bryrX?= =?us-ascii?Q?9BJ94v680UzLBjd8PX5XF6d/oQ9XxmJh01lM+lBeuTpx3pnc98yQufSrD5GR?= =?us-ascii?Q?hA5EhDjLlmBBAmU63B5UKMm8+Lz/Qq2C7O3+zFpsS3EwTJ5tx7KyiBvwIIMy?= =?us-ascii?Q?iQWXf8cUyon2Iv+U1NXTfQEnXZdRp97Ki214FQVcaIqpNv/mgAOsw7DI4KaJ?= =?us-ascii?Q?vlUNAPmm0k6YsZUhvkBiYSyszw229FFNVSzBwi2KTYmwvPq9xe+P0nG582pR?= =?us-ascii?Q?6UdV6ZztWlKDdLWEAej1Vkep58AdEl6cZiqwZ0oyi+ubFDLvZLbTPSZT6ex5?= =?us-ascii?Q?4RjB3tHmyZSkewO2dd/vyOlbev18Ts6HCRKLCfveRxYXO2o1GZ1lsWCwGS+E?= =?us-ascii?Q?PufnUaywt9Jn6ZnadZDpJUWqyvfT286kndvT5AYOLkwlNxvaW86s3OcrYaar?= =?us-ascii?Q?Wz3aXrexArsoRIRwHpn18BWp9EdcieWB4pmgzqzenPrUBZ7GM5jIPkjrEXu2?= =?us-ascii?Q?cdNueMIDLBz2/Lpbod5EiztzA04iBDoqQu0x+etTYyz9UCcM5yjegBSm9zw7?= =?us-ascii?Q?ZklXlKTGNJTPpIphpJb+oEeWb07SoBRvTLDt?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 09:55:57.9722 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b80f144-a2c1-4515-5f4a-08ddc44ef6a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000208.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7881 Received-SPF: permerror client-ip=2a01:111:f403:2408::609; envelope-from=Luc.Michel@amd.com; helo=NAM04-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1752659827615116600 Content-Type: text/plain; charset="utf-8" Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 7 +--- hw/arm/xlnx-versal-virt.c | 79 +----------------------------------- hw/arm/xlnx-versal.c | 73 ++++++++++++++++++++++----------- 3 files changed, 53 insertions(+), 106 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 7be5a6ccf4d..a3bc967c352 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -41,15 +41,10 @@ struct Versal { =20 /*< public >*/ GArray *intc; MemoryRegion mr_ps; =20 - struct { - /* 4 ranges to access DDR. */ - MemoryRegion mr_ddr_ranges[4]; - } noc; - struct { uint32_t clk_25mhz; uint32_t clk_125mhz; uint32_t gic; } phandle; @@ -71,10 +66,12 @@ static inline void versal_set_fdt(Versal *s, void *fdt) { g_assert(!qdev_is_realized(DEVICE(s))); s->cfg.fdt =3D fdt; } =20 +void versal_fdt_add_memory_nodes(Versal *s, uint64_t ram_size); + void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk); void versal_efuse_attach_drive(Versal *s, BlockBackend *blk); void versal_bbram_attach_drive(Versal *s, BlockBackend *blk); void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_= mdl, BlockBackend *blk); diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index cad345b98e0..7f40c197072 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -104,92 +104,17 @@ static void fdt_nop_memory_nodes(void *fdt, Error **e= rrp) n++; } g_strfreev(node_path); } =20 -static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_si= ze) -{ - /* Describes the various split DDR access regions. */ - static const struct { - uint64_t base; - uint64_t size; - } addr_ranges[] =3D { - { MM_TOP_DDR, MM_TOP_DDR_SIZE }, - { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, - { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, - { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } - }; - uint64_t mem_reg_prop[8] =3D {0}; - uint64_t size =3D ram_size; - Error *err =3D NULL; - char *name; - int i; - - fdt_nop_memory_nodes(fdt, &err); - if (err) { - error_report_err(err); - return; - } - - name =3D g_strdup_printf("/memory@%x", MM_TOP_DDR); - for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { - uint64_t mapsize; - - mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; - - mem_reg_prop[i * 2] =3D addr_ranges[i].base; - mem_reg_prop[i * 2 + 1] =3D mapsize; - size -=3D mapsize; - } - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); - - switch (i) { - case 1: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1]); - break; - case 2: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3]); - break; - case 3: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3], - 2, mem_reg_prop[4], - 2, mem_reg_prop[5]); - break; - case 4: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3], - 2, mem_reg_prop[4], - 2, mem_reg_prop[5], - 2, mem_reg_prop[6], - 2, mem_reg_prop[7]); - break; - default: - g_assert_not_reached(); - } - g_free(name); -} - static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, void *fdt) { VersalVirt *s =3D container_of(binfo, VersalVirt, binfo); =20 - fdt_add_memory_nodes(s, fdt, binfo->ram_size); + fdt_nop_memory_nodes(s->fdt, &error_abort); + versal_fdt_add_memory_nodes(&s->soc, binfo->ram_size); } =20 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, int *fdt_size) { diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index f46c73ac8e7..bf680077e48 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -115,10 +115,15 @@ typedef struct VersalCpuClusterMap { } VersalCpuClusterMap; =20 typedef struct VersalMap { VersalMemMap ocm; =20 + struct VersalDDRMap { + VersalMemMap chan[4]; + size_t num_chan; + } ddr; + VersalCpuClusterMap apu; VersalCpuClusterMap rpu; =20 VersalSimplePeriphMap uart[2]; size_t num_uart; @@ -219,10 +224,18 @@ static const VersalMap VERSAL_MAP =3D { .ocm =3D { .addr =3D 0xfffc0000, .size =3D 0x40000, }, =20 + .ddr =3D { + .chan[0] =3D { .addr =3D 0x0, .size =3D 2 * GiB }, + .chan[1] =3D { .addr =3D 0x800000000ull, .size =3D 32 * GiB }, + .chan[2] =3D { .addr =3D 0xc00000000ull, .size =3D 256 * GiB }, + .chan[3] =3D { .addr =3D 0x10000000000ull, .size =3D 734 * GiB }, + .num_chan =3D 4, + }, + .apu =3D { .name =3D "apu", .cpu_model =3D ARM_CPU_TYPE_NAME("cortex-a72"), .num_cluster =3D 1, .num_core =3D 2, @@ -1480,50 +1493,62 @@ static inline void versal_create_crl(Versal *s) sysbus_mmio_get_region(SYS_BUS_DEVICE(dev)= , 0)); =20 versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, map->crl.irq); } =20 -/* This takes the board allocated linear DDR memory and creates aliases +/* + * This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ -static void versal_map_ddr(Versal *s) +static void versal_map_ddr(Versal *s, const struct VersalDDRMap *map) { uint64_t size =3D memory_region_size(s->cfg.mr_ddr); - /* Describes the various split DDR access regions. */ - static const struct { - uint64_t base; - uint64_t size; - } addr_ranges[] =3D { - { MM_TOP_DDR, MM_TOP_DDR_SIZE }, - { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, - { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, - { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } - }; uint64_t offset =3D 0; int i; =20 - assert(ARRAY_SIZE(addr_ranges) =3D=3D ARRAY_SIZE(s->noc.mr_ddr_ranges)= ); - for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { - char *name; + for (i =3D 0; i < map->num_chan && size; i++) { uint64_t mapsize; + MemoryRegion *alias; + + mapsize =3D MIN(size, map->chan[i].size); =20 - mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; - name =3D g_strdup_printf("noc-ddr-range%d", i); /* Create the MR alias. */ - memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), - name, s->cfg.mr_ddr, - offset, mapsize); + alias =3D g_new(MemoryRegion, 1); + memory_region_init_alias(alias, OBJECT(s), "noc-ddr-range", + s->cfg.mr_ddr, offset, mapsize); =20 /* Map it onto the NoC MR. */ - memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, - &s->noc.mr_ddr_ranges[i]); + memory_region_add_subregion(&s->mr_ps, map->chan[i].addr, alias); offset +=3D mapsize; size -=3D mapsize; - g_free(name); } } =20 +void versal_fdt_add_memory_nodes(Versal *s, uint64_t size) +{ + const struct VersalDDRMap *map =3D &versal_get_map(s)->ddr; + g_autofree char *node; + g_autofree uint64_t *reg; + int i; + + reg =3D g_new(uint64_t, map->num_chan * 2); + + for (i =3D 0; i < map->num_chan && size; i++) { + uint64_t mapsize; + + mapsize =3D MIN(size, map->chan[i].size); + + reg[i * 2] =3D cpu_to_be64(map->chan[i].addr); + reg[i * 2 + 1] =3D cpu_to_be64(mapsize); + + size -=3D mapsize; + } + + node =3D versal_fdt_add_subnode(s, "/memory", 0, "memory", sizeof("mem= ory")); + qemu_fdt_setprop(s->cfg.fdt, node, "reg", reg, sizeof(uint64_t) * i * = 2); +} + static void versal_unimp_area(Versal *s, const char *name, MemoryRegion *mr, hwaddr base, hwaddr size) { DeviceState *dev =3D qdev_new(TYPE_UNIMPLEMENTED_DEVICE); @@ -1687,11 +1712,11 @@ static void versal_realize(DeviceState *dev, Error = **errp) versal_create_trng(s, &map->trng); versal_create_rtc(s, &map->rtc); versal_create_cfu(s, &map->cfu); versal_create_crl(s); =20 - versal_map_ddr(s); + versal_map_ddr(s, &map->ddr); versal_unimp(s); =20 /* Create the On Chip Memory (OCM). */ ocm =3D g_new(MemoryRegion, 1); memory_region_init_ram(ocm, OBJECT(s), "ocm", map->ocm.size, &error_fa= tal); --=20 2.50.0