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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH 13/48] hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs Date: Wed, 16 Jul 2025 11:53:55 +0200 Message-ID: <20250716095432.81923-14-luc.michel@amd.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250716095432.81923-1-luc.michel@amd.com> References: <20250716095432.81923-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000204:EE_|IA0PR12MB8375:EE_ X-MS-Office365-Filtering-Correlation-Id: fc6bb4ff-0f57-442b-9885-08ddc44ee830 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wdxNCFPTLLGUNzqwN6wpY6eYMCIv4Uto0DCD026KSjOF+RBFhK1yXf7fOSAZ?= =?us-ascii?Q?GyKDx74+JhGBCEZqo2JTc85Cyp838XWfENRtU3Igy94louErnW5Vyn+BMw8R?= =?us-ascii?Q?nPMWxRixYuliujtGHnsqL+/p1kh2KAlMvh5KCklSxMNDFmMLJj/5/GWNnVOn?= =?us-ascii?Q?mudHruYmKBEY31PsbU9g14loa44rjwelbFYX/j70ZA+OpHNQsk6AQe2C+Bez?= =?us-ascii?Q?k1cJ1NE2RNZ1ZastjzfiBRFBydvmoBHo0ba1qyRYvC2DEf8jAE7j/ncZEIf4?= =?us-ascii?Q?Qq8HhdBsdOsVc6nb2f3D54hPFowqgmul6M+UwyL6JqQgxePCNssd30bgx383?= =?us-ascii?Q?xFnmUqCIKLGeq6bFS9wt0r4DJMjCPqsHSIZXrIf3JsljSANHz6pFwB2je5he?= =?us-ascii?Q?zHaHSlccYs673k6QAB+Y2S4GZztZ55T9ltAHe03wLvmF5PSyHPQkIwV9+Jzy?= =?us-ascii?Q?0wOxJTSxvRLCY8u5Q8ikjOQigfPYrzHwbruzR+Y+P5XpYUl/tJUEXjDYJ0fX?= =?us-ascii?Q?Dx1O+EuPBe1FUUmGzgHCiH6RRK8y7ds3n7rGgG0zODoOki/YWh19j+4Muj9I?= =?us-ascii?Q?qc7GqHi3HjCCrYkHwnvtmRJAQYSERmzHt2SYlccGbEPRBEB7b/0VJYHA/KDR?= =?us-ascii?Q?9KSCJyc9RX9hJkGiDj1NTDD1hf9wxPgR6llBkpaAnCamG6eRJgllKXrrXXTU?= =?us-ascii?Q?y3MYrY5fgHkFotAk/KN9kPv6Z1fHzOciUSbJbEiQDv+uf7VIgHAHyaLsNKuD?= =?us-ascii?Q?tAZD0e8RBzT0JbCWfWbXrSMy+Df4QZpIp6g0DLFl94Z+ArxJtSAmkXZAWrKk?= =?us-ascii?Q?IidW2Di1KUghVxxYKNLUjXWhqxY4A03xlqOJhZNWkoqm/9Xn1xUJTXWg4UUz?= =?us-ascii?Q?obzSQPmcErEAU6XZ5KTGJBMkrqZOCWH3ZHTGJtr3pYxN+50+mr07NSXRqpXF?= =?us-ascii?Q?jgUXTyEjwDN5cbij6a5Dl6OXjiFxEZzuWsEaSVONE43857B1VziPMkl5M/4z?= =?us-ascii?Q?uF7aF+gl+LCVlNd0vlrjqmXIzr1ZinUA4Ya+n3VTI8rmAhNqfLwh4Hsxp/ls?= =?us-ascii?Q?uNNDAyRMQG32iLnWN256dJ5TaqSRpbPf6Yp9ltGIiP50eMP2sM0H8zBsO2up?= =?us-ascii?Q?WM0TGtrrsacOFuVq17Hk/6S9nE3oN6VguLzgZWKiSbmh7vzv54L6m6cPOMc0?= =?us-ascii?Q?H7nltdl3k92gJ+bGo4YzgSly3qM2ZsWpVq/i1rzYK6MrUGK2HIzDxnaOoPRT?= =?us-ascii?Q?qVHYITFdNmGGX7BgcLJ2b2ptuLVLpNuJbI49J7AZ82iNRlI8jKnkf115fLAs?= =?us-ascii?Q?gW7vDSqgSSTfRs2BQ8fypEvxmTiJ73pFC/laGqHDFMAAgLx3/K28CuhDvBtM?= =?us-ascii?Q?5+JZgTFW6F3FBj/rwtVS4eIL86hKrqJPNU5T0YjRu6RJm8thVwBZJw0Guvj0?= =?us-ascii?Q?PP+u1JySbG/Yhwz3mIy5xT4tGd6XhOxGZfZW+AuH4ClXxMBlnM1rucz1CVp4?= =?us-ascii?Q?LOL0jjIbPDh1HH6oZDcXi0tvC56TCo0WtwHj?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2025 09:55:33.7128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc6bb4ff-0f57-442b-9885-08ddc44ee830 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000204.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8375 Received-SPF: permerror client-ip=2a01:111:f403:2413::601; envelope-from=Luc.Michel@amd.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1752659841560116600 Content-Type: text/plain; charset="utf-8" Improve the IRQ index in the VersalMap structure to turn it into a descriptor: - the lower 16 bits still represent the IRQ index - bit 18 is used to indicate a shared IRQ connected to a OR gate - bits 19 to 22 indicate the index on the OR gate. This allows to share an IRQ among multiple devices. An OR gate is created to connect the devices to the actual IRQ pin. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 62 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 58176fa11e5..89c93278336 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -41,10 +41,21 @@ #define GEM_REVISION 0x40070106 =20 #define VERSAL_NUM_PMC_APB_IRQS 18 #define NUM_OSPI_IRQ_LINES 3 =20 +/* + * IRQ descriptor to catch the following cases: + * - Multiple devices can connect to the same IRQ. They are OR'ed togeth= er. + */ +FIELD(VERSAL_IRQ, IRQ, 0, 16) +FIELD(VERSAL_IRQ, ORED, 18, 1) +FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */ + +#define OR_IRQ(irq, or_idx) \ + (R_VERSAL_IRQ_ORED_MASK | ((or_idx) << R_VERSAL_IRQ_OR_IDX_SHIFT) | (i= rq)) + typedef struct VersalSimplePeriphMap { uint64_t addr; int irq; } VersalSimplePeriphMap; =20 @@ -172,13 +183,56 @@ static inline Object *versal_get_child_idx(Versal *s,= const char *child, g_autofree char *n =3D g_strdup_printf("%s[%zu]", child, idx); =20 return versal_get_child(s, n); } =20 +/* + * When the R_VERSAL_IRQ_ORED flag is set on an IRQ descriptor, this funct= ion is + * used to return the corresponding or gate input IRQ. The or gate is crea= ted if + * not already existant. + * + * Or gates are placed under the /soc/irq-or-gates QOM container. + */ +static qemu_irq versal_get_irq_or_gate_in(Versal *s, int irq_idx, + qemu_irq target_irq) +{ + Object *container =3D versal_get_child(s, "irq-or-gates"); + DeviceState *dev; + g_autofree char *name; + int idx, or_idx; + + idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ); + or_idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, OR_IDX); + + name =3D g_strdup_printf("irq[%d]", idx); + dev =3D DEVICE(object_resolve_path_at(container, name)); + + if (dev =3D=3D NULL) { + dev =3D qdev_new(TYPE_OR_IRQ); + object_property_add_child(container, name, OBJECT(dev)); + qdev_prop_set_uint16(dev, "num-lines", 1 << R_VERSAL_IRQ_OR_IDX_LE= NGTH); + qdev_realize_and_unref(dev, NULL, &error_abort); + qdev_connect_gpio_out(dev, 0, target_irq); + } + + return qdev_get_gpio_in(dev, or_idx); +} + static qemu_irq versal_get_irq(Versal *s, int irq_idx) { - return qdev_get_gpio_in(DEVICE(&s->fpd.apu.gic), irq_idx); + qemu_irq irq; + bool ored; + + ored =3D FIELD_EX32(irq_idx, VERSAL_IRQ, ORED); + + irq =3D qdev_get_gpio_in(DEVICE(&s->fpd.apu.gic), irq_idx); + + if (ored) { + irq =3D versal_get_irq_or_gate_in(s, irq_idx, irq); + } + + return irq; } =20 static void versal_sysbus_connect_irq(Versal *s, SysBusDevice *sbd, int sbd_idx, int irq_idx) { @@ -1209,10 +1263,11 @@ static uint32_t fdt_add_clk_node(Versal *s, const c= har *name, =20 static void versal_realize(DeviceState *dev, Error **errp) { Versal *s =3D XLNX_VERSAL_BASE(dev); qemu_irq pic[XLNX_VERSAL_NR_IRQS]; + Object *container; const VersalMap *map =3D versal_get_map(s); size_t i; =20 if (s->cfg.fdt =3D=3D NULL) { int fdt_size; @@ -1223,10 +1278,15 @@ static void versal_realize(DeviceState *dev, Error = **errp) s->phandle.clk_25mhz =3D fdt_add_clk_node(s, "/clk25", 25 * 1000 * 100= 0); s->phandle.clk_125mhz =3D fdt_add_clk_node(s, "/clk125", 125 * 1000 * = 1000); =20 versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); + + container =3D object_new(TYPE_CONTAINER); + object_property_add_child(OBJECT(s), "irq-or-gates", container); + object_unref(container); + versal_create_rpu_cpus(s); =20 for (i =3D 0; i < map->num_uart; i++) { versal_create_uart(s, &map->uart[i], i); } --=20 2.50.0