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Mon, 14 Jul 2025 13:50:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFrKZjYCIq85br5O3z4hRWG3ioyf+U7l5uZEMH/Y8jgIbXIrpYSSSvHfdckzVswEa7fM5GyDA== X-Received: by 2002:a05:6a00:14ca:b0:748:eedb:902a with SMTP id d2e1a72fcca58-74ee2d5d7e8mr15675119b3a.17.1752526212464; Mon, 14 Jul 2025 13:50:12 -0700 (PDT) From: Vacha Bhavsar To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Vacha Bhavsar Subject: [PATCH v3] target/arm: Added support for SME register exposure to GDB Date: Mon, 14 Jul 2025 20:50:11 +0000 Message-Id: <20250714205011.955688-1-vacha.bhavsar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e7gGSbp/ c=1 sm=1 tr=0 ts=68756d91 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=cPBEBSeHtjnCkXsRAdUA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: nyrutAYakjphIZjhuFeaZtUAXyd7uTrl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE0MDE0MCBTYWx0ZWRfX7nj+ihv8Jg+m MGfzyzLN6DQ+jSF8t8c+Y9xO3Q1pijQ936RETSBLpb7U/CVGFOLcvxn22KtU4suzZOCdnsBLSHJ W7IigBZprVc+tcod9N3KR5pzvSlN43PdPOEbr2nGARCWwjxNiQwz0o5ZNPB+WKaxM6KbrWOnEcX F2ZzhnI16BYDmSlIGf2BW8qYumvkXQaBjC03jQIUgmOE6D/fMUEAQC5Nw1HJbbNPEOntRbSoubs slcGru3+d+jgkcEUp9vODsh6376iTibqAZ/y4Cp+5glVwcfW6adpFquGdCIjEkeSUc2G8EP5Teq 7qefzv5slRdO7891+h+7sRAhqGOIVBMyMMaFrYtK3gMcOG7y6wMwzlF1nGsTgxZg3H7ESKkYIjV Qkdsb+FI4DwKbuA0qS8ObST/MiJE6IfCkje8IVpFG7HE/G+ZK6obTRbPCzCbYa5GWJgrCRGV X-Proofpoint-ORIG-GUID: nyrutAYakjphIZjhuFeaZtUAXyd7uTrl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-14_02,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507140140 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1752531956210116600 Content-Type: text/plain; charset="utf-8" The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality in Aarch64 target, this patch registers= the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Signed-off-by: Vacha Bhavsar --- Changes since v2: - Used FIELD_EX64(env->svcr, SVCR, SM) to determine streaming mode to set value of vq in aarch64_gdb_get_sme_reg() - Changed occurrences of sve_max_vq in the new sme functions to sme_max_vq - Changed 'for (q =3D 0' to 'for (int q =3D 0' in the loop in case 2 in aarch64_gdb_get_sme_reg() - Returned 8, instead of 0, in case 0 (setting svg) in=20 aarch64_gdb_set_sme_reg() - Used ldq_le_p(buf) in the call to aarch64_set_svcr in case 1 (setting svcr) in aarch64_gdb_set_sme_reg() - Mirrored the q/vq loop from aarch64_gdb_get_sme_reg() in aarch64_gdb_set_sme_reg() target/arm/cpu.h | 1 + target/arm/gdbstub.c | 6 +++ target/arm/gdbstub64.c | 115 +++++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 3 ++ 4 files changed, 125 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dc9b6dce4c..8bd66d7049 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -933,6 +933,7 @@ struct ArchCPU { =20 DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c..9c942c77cc 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -531,6 +531,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature, 0); + if (isar_feature_aa64_sme(&cpu->isar)) { + GDBFeature *sme_feature =3D arm_gen_dynamic_smereg_feature= (cs, + cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, + aarch64_gdb_set_sme_reg, sme_feature, 0); + } } else { gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, aarch64_gdb_set_fpu_reg, diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 64ee9b3b56..c0fdac7e93 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -228,6 +228,84 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + /* Svg register */ + case 0: + { + int vq =3D 0; + if (FIELD_EX64(env->svcr, SVCR, SM)) { + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), + FIELD_EX64(env->svcr, SVCR, SM)) + 1; + } + /* svg =3D vector granules (2 * vector quardwords) in streaming mo= de */ + return gdb_get_reg64(buf, vq * 2); + } + case 1: + return gdb_get_reg64(buf, env->svcr); + case 2: + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + len +=3D gdb_get_reg128(buf, + env->za_state.za[i].d[q * 2 + 1], + env->za_state.za[i].d[q * 2]); + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: + { + /* cannot set svg via gdbstub */ + return 8; + } + case 1: + aarch64_set_svcr(env, ldq_le_p(buf), + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + return 8; + case 2: + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + uint64_t *p =3D (uint64_t *) buf; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + env->za_state.za[i].d[q * 2 + 1] =3D *p++; + env->za_state.za[i].d[q * 2] =3D *p++; + len +=3D 16; + } + } + return len; + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -392,6 +470,43 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_svereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, + "org.gnu.gdb.aarch64.sme", "sme-registers.xml", base_reg); + + + /* Create the sme_bv vector type. */ + gdb_feature_builder_append_tag(&builder, + "", + svl); + + /* Create the sme_bvv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Define the svg, svcr, and za registers. */ + + /* fpscr & status registers */ + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, + "int", NULL); + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, + "int", NULL); + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++, + "sme_bvv", NULL); + + gdb_feature_builder_end(&builder); + + return &cpu->dyn_smereg_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { diff --git a/target/arm/internals.h b/target/arm/internals.h index c4765e4489..760e1c6490 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1808,8 +1808,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) } =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); --=20 2.34.1