From nobody Sat Nov 15 12:50:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752513177; cv=none; d=zohomail.com; s=zohoarc; b=eHpYA+RnYrC/pIkazhJcx2JYAvvo/CQxs+sHtAb7BlQp7PrO02DznulrGHB3gdNddr6XDFQEIKsN5lorfXqxW2O8IrEuwFtjHOTi8gj8iD7mcwU73CgcW2cgxMRo8sqDZSO2UhbYwSOaF+sFQjuY0OgkEjKvt39eJfNp3mWWtWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752513177; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=SN5S3cgrW/V0ZTiCimL+x+5C/Q4KCwdK8HN4Gm5mDXA=; b=Xsl8Mp2BX0Og7grbuoCsBxYWgCWiph+cXbOdKMOuj9eLogV5/5/KbiZhcj/Bg4q6KU8RqRsKdYtpeBXUj5sX87kaBiNm//rJ75bmrRVArtW67sIqn6jUhffeMbkZAewAnhfFiQqNvRn/MDM4FPpFDqNvZtSbGE4PYAJbQ3qjDTo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752513177493185.32840618203477; Mon, 14 Jul 2025 10:12:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ubMht-0006xO-9i; Mon, 14 Jul 2025 13:11:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLc2-0005Cl-H5; Mon, 14 Jul 2025 12:01:09 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLc0-0008I7-46; Mon, 14 Jul 2025 12:01:05 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bgn5T0yhpz6L5M0; Mon, 14 Jul 2025 23:57:33 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 74C2B14033F; Tue, 15 Jul 2025 00:01:00 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:00:51 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Date: Mon, 14 Jul 2025 16:59:31 +0100 Message-ID: <20250714155941.22176-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513178480116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Also setup specific PCIIOMMUOps for accel SMMUv3 as accel SMMUv3 will have different handling for those ops callbacks in subsequent patches. The "accel" property is not yet added, so users cannot set it at this point. It will be introduced in a subsequent patch once the necessary support is in place. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/meson.build | 3 +- hw/arm/smmu-common.c | 6 +++- hw/arm/smmuv3-accel.c | 66 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 19 +++++++++++ include/hw/arm/smmu-common.h | 3 ++ 5 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 hw/arm/smmuv3-accel.h diff --git a/hw/arm/meson.build b/hw/arm/meson.build index dc68391305..6126eb1b64 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: ['CONFIG_ARM_SMMUV3', 'CONFIG_IOMMUFD'], if_true: files('= smmuv3-accel.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3a1080773a..6a58f574d3 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -938,7 +938,11 @@ static const PCIIOMMUOps *smmu_iommu_ops_by_type(SMMUS= tate *s) { SMMUBaseClass *sbc; =20 - sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU)); + if (s->accel) { + sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMUV3_ACCEL)= ); + } else { + sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU)); + } assert(sbc->iommu_ops); =20 return sbc->iommu_ops; diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..2eac9c6ff4 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" + +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + } else { + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(bs, sdev, bus, devfn); + } + + return accel_dev; +} + +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus; + SMMUv3AccelDevice *accel_dev; + SMMUDevice *sdev; + + sbus =3D smmu_get_sbus(bs, bus); + accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, devfn); + sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + +static const PCIIOMMUOps smmuv3_accel_ops =3D { + .get_address_space =3D smmuv3_accel_find_add_as, +}; + +static void smmuv3_accel_class_init(ObjectClass *oc, const void *data) +{ + SMMUBaseClass *sbc =3D ARM_SMMU_CLASS(oc); + + sbc->iommu_ops =3D &smmuv3_accel_ops; +} + +static const TypeInfo types[] =3D { + { + .name =3D TYPE_ARM_SMMUV3_ACCEL, + .parent =3D TYPE_ARM_SMMUV3, + .class_init =3D smmuv3_accel_class_init, + } +}; +DEFINE_TYPES(types) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..4cf30b1291 --- /dev/null +++ b/hw/arm/smmuv3-accel.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include CONFIG_DEVICES + +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index eb94623555..c459d24427 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -162,6 +162,7 @@ struct SMMUState { uint8_t bus_num; PCIBus *primary_bus; bool smmu_per_bus; /* SMMU is specific to the primary_bus */ + bool accel; /* SMMU has accelerator support */ }; =20 struct SMMUBaseClass { @@ -178,6 +179,8 @@ struct SMMUBaseClass { #define TYPE_ARM_SMMU "arm-smmu" OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) =20 +#define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" + /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 --=20 2.34.1