From nobody Sat Nov 15 12:49:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752512905; cv=none; d=zohomail.com; s=zohoarc; b=ltTP6bDwk/38alyQiIv1p4lOvIAD+AnTcdunhBAvlNyNYhRPTHDw9QFDfHRhPoCn/dTvCK/YjS3w1w1ieossIZowVv9NbVnk4p+ZbZKnYhLeYwyA/X3vmEiNm0v2UB2ix8EjZtb4VbhEvawwzmn+j0x9KkWT8i9VxFQX1HjkgeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752512905; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=xNFctIw4p16GqwzA6UlAaZ9FbURxmrCf1WzcjMXFFo4=; b=cE0F1PTFsjp2pj0x8Cy6KX15Kv3XR4++bAp/Qw5Ip/5jAnrjEr/3MTnQ/ilp9mfMh3dhBYXcUIpyrileA6RF7kh3RfxLPy8phWsxZpKdsxuFYULoIN11S7gNIWGUtYycpDs3dqz23v1LmmUq6OLjF9Nxof2DO5ff+T4BoekVqkg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752512905272123.2987870168381; Mon, 14 Jul 2025 10:08:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ubMZy-00053q-VG; Mon, 14 Jul 2025 13:03:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLd2-0005bF-Ur; Mon, 14 Jul 2025 12:02:19 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLd0-0008QQ-J9; Mon, 14 Jul 2025 12:02:08 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bgn9R1kCCz6L5jt; Tue, 15 Jul 2025 00:00:59 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 277751402FB; Tue, 15 Jul 2025 00:02:04 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:01:55 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 12/15] hw/arm/smmuv3-accel: Introduce helpers to batch and issue cache invalidations Date: Mon, 14 Jul 2025 16:59:38 +0100 Message-ID: <20250714155941.22176-13-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752512907279116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Helpers will batch the commands and issue at once to host SMMUv3. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 65 ++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 16 ++++++++++ hw/arm/smmuv3-internal.h | 12 ++++++++ 3 files changed, 93 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 04c665ccf5..1298b4f6d0 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -168,6 +168,71 @@ smmuv3_accel_install_nested_ste_range(SMMUState *bs, S= MMUSIDRange *range) g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range); } =20 +/* Update batch->ncmds to the number of execute cmds */ +bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch) +{ + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t total =3D batch->ncmds; + IOMMUFDViommu *viommu_core; + int ret; + + if (!bs->accel) { + return true; + } + + if (!s_accel->viommu) { + return true; + } + + viommu_core =3D &s_accel->viommu->core; + ret =3D iommufd_backend_invalidate_cache(viommu_core->iommufd, + viommu_core->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_AR= M_SMMUV3, + sizeof(Cmd), &batch->ncmds, + batch->cmds, NULL); + if (!ret || total !=3D batch->ncmds) { + error_report("%s failed: ret=3D%d, total=3D%d, done=3D%d", + __func__, ret, total, batch->ncmds); + return ret; + } + + batch->ncmds =3D 0; + return ret; +} + +/* + * Note: sdev can be NULL for certain invalidation commands + * e.g., SMMU_CMD_TLBI_NH_ASID, SMMU_CMD_TLBI_NH_VA etc. + */ +void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, Cmd *cmd, + uint32_t *cons) +{ + if (!bs->accel) { + return; + } + + /* + * We may end up here for any emulated PCI bridge or root port type + * devices. The batching of commands only matters for vfio-pci endpoint + * devices with Guest S1 translation enabled. Hence check that, if + * sdev is available. + */ + if (sdev) { + SMMUv3AccelDevice *accel_dev; + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + + if (!accel_dev->s1_hwpt) { + return; + } + } + + batch->cmds[batch->ncmds] =3D *cmd; + batch->cons[batch->ncmds++] =3D *cons; + return; +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 21028e60c8..d06c9664ba 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -13,6 +13,7 @@ #include "hw/arm/smmu-common.h" #include "system/iommufd.h" #include +#include "smmuv3-internal.h" #include CONFIG_DEVICES =20 typedef struct SMMUS2Hwpt { @@ -55,6 +56,10 @@ void smmuv3_accel_init(SMMUv3State *s); void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int = sid); void smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range); +bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch); +void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, struct Cmd *cmd, + uint32_t *cons); #else static inline void smmuv3_accel_init(SMMUv3State *d) { @@ -67,6 +72,17 @@ static inline void smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) { } +static inline bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, + SMMUCommandBatch *batch) +{ + return true; +} +static inline void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, + struct Cmd *cmd, uint32_t *cons) +{ + return; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 738061c6ad..8cb6a9238a 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -547,6 +547,18 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +/* + * SMMUCommandBatch - batch of invalidation commands for accel smmuv3 + * @cmds: Pointer to list of commands + * @cons: Pointer to list of CONS corresponding to the commands + * @ncmds: Number of cmds in the batch + */ +typedef struct SMMUCommandBatch { + struct Cmd *cmds; + uint32_t *cons; + uint32_t ncmds; +} SMMUCommandBatch; + int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event); void smmuv3_flush_config(SMMUDevice *sdev); --=20 2.34.1