From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752512293; cv=none; d=zohomail.com; s=zohoarc; b=OA0mJ77pxxCzAnBF9bX64omr6HjL6tABFo9CpzDTVEfNcUeZMtP3UCqsGo6uG4Thaa2/ue8ascwWgTme68S/P7HNCK6B3Hhtjkl0gjLo8k95fkwHUcPFnALuwPHsRk8G+7ylGAo5VFE/v6yGpRdMnjaG1QsFmuAzMu18JjO4O9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752512293; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=FIkKck/AAFntbDEbzSJaz1rzSDh/yrK3Ecn79gYZERA=; b=R8VJafu+3iJ1eeIMiWEmyYFGLVx1GdDhUXuGsKbwOCG811r3FBnb4lHBBd3bvXdwJC6n1xTOCt1jfCRQjhMIS9DdrlVAWKT1COGxBCYhtR52HlRZTE6FcXvfQBHUC7PGhttfOIV2Ng4IswFYimMG5D06c6tbgxDybYUSymcJMXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752512293507812.2550877720331; Mon, 14 Jul 2025 09:58:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ubMUe-0006n2-Ip; Mon, 14 Jul 2025 12:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLbW-0004vM-NM; Mon, 14 Jul 2025 12:00:36 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ubLbU-00082r-5c; Mon, 14 Jul 2025 12:00:33 -0400 Received: from mail.maildlp.com (unknown [172.18.186.31]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4bgn7W1cgPz6L5NT; Mon, 14 Jul 2025 23:59:19 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 246E8140142; Tue, 15 Jul 2025 00:00:24 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:00:15 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 01/15] backends/iommufd: Introduce iommufd_backend_alloc_viommu Date: Mon, 14 Jul 2025 16:59:27 +0100 Message-ID: <20250714155941.22176-2-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752512294947116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate a viommu object. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 25 +++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 30 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index 2a33c7ab0b..f3b95ee321 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -446,6 +446,31 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *= be, uint32_t id, return !ret; } =20 +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_viommu_id, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_viommu_alloc alloc_viommu =3D { + .size =3D sizeof(alloc_viommu), + .type =3D viommu_type, + .dev_id =3D dev_id, + .hwpt_id =3D hwpt_id, + }; + + ret =3D ioctl(fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); + + trace_iommufd_backend_alloc_viommu(fd, viommu_type, dev_id, hwpt_id, + alloc_viommu.out_viommu_id, ret); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); + return false; + } + + *out_viommu_id =3D alloc_viommu.out_viommu_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 56132d3fd2..2294af2cc8 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,3 +21,4 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t type, uint32_t dev_id, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index c9c72ffc45..9acdb20032 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -59,6 +59,10 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint= 32_t dev_id, uint32_t data_type, uint32_t data_len, void *data_ptr, uint32_t *out_hwpt, Error **errp); +bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_type, uint32_t hwpt_id, + uint32_t *out_hwpt, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752512394; cv=none; d=zohomail.com; s=zohoarc; b=U6VZ22etbZc54udwA3matyHehy2oJOLInk54oXureGQyqI9YAUQYSJtBW5BuXu4QjyOrNTCMQ6aRjdzAt9o/vnj3qwveT/SK/jYHBNrgUYvYyvfmUfLvnxM0RK5hqWKE9Oqa0/TYYtTNWirbBR0gHbOgVqgiRY3yZx9c/51NWcY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Mon, 14 Jul 2025 18:00:24 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 02/15] backends/iommufd: Introduce iommufd_vdev_alloc Date: Mon, 14 Jul 2025 16:59:28 +0100 Message-ID: <20250714155941.22176-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752512396578116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd device's virtual device (in the user space) per a viommu instance. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 26 ++++++++++++++++++++++++++ backends/trace-events | 1 + include/system/iommufd.h | 4 ++++ 3 files changed, 31 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index f3b95ee321..0cafa1a4b7 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -471,6 +471,32 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, = uint32_t dev_id, return true; } =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp) +{ + int ret, fd =3D be->fd; + struct iommu_vdevice_alloc alloc_vdev =3D { + .size =3D sizeof(alloc_vdev), + .viommu_id =3D viommu_id, + .dev_id =3D dev_id, + .virt_id =3D virt_id, + }; + + ret =3D ioctl(fd, IOMMU_VDEVICE_ALLOC, &alloc_vdev); + + trace_iommufd_backend_alloc_vdev(fd, dev_id, viommu_id, virt_id, + alloc_vdev.out_vdevice_id, ret); + + if (ret) { + error_setg_errno(errp, errno, "IOMMU_VDEVICE_ALLOC failed"); + return false; + } + + *out_vdev_id =3D alloc_vdev.out_vdevice_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 2294af2cc8..14399da111 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -22,3 +22,4 @@ iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, = bool start, int ret) " iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t page_size, int ret) " iommufd=3D%d hwpt=3D%u i= ova=3D0x%"PRIx64" size=3D0x%"PRIx64" page_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" iommufd_backend_alloc_viommu(int iommufd, uint32_t type, uint32_t dev_id, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 9acdb20032..6ab3ba3cb6 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -63,6 +63,10 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, ui= nt32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, uint32_t *out_hwpt, Error **errp); =20 +bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, + uint32_t viommu_id, uint64_t virt_id, + uint32_t *out_vdev_id, Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752513076; cv=none; d=zohomail.com; s=zohoarc; b=AtU7tDD3tEqTQgeBJcnuHQH7zCpzgnesA8QhsmvodL/8Lc1dyJUwpUDxWKaxqDVMeI+pss80HiD8A+n4XRPp+sce9zMRjEtHMNy+5ghSPUKRdkMVMKiNyTcQC9PveYQETxCKPg3Kzp7TkbblnHSYHbE5Dlxm7ZrwtmhY2ijRqk8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Mon, 14 Jul 2025 18:00:33 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 03/15] hw/arm/smmu-common: Factor out common helper functions and export Date: Mon, 14 Jul 2025 16:59:29 +0100 Message-ID: <20250714155941.22176-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513077158116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Subsequent patches for smmuv3 accel support will make use of this. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- hw/arm/smmu-common.c | 48 ++++++++++++++++++++++-------------- include/hw/arm/smmu-common.h | 6 +++++ 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index ab920717cf..0f1a06cec2 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -847,12 +847,28 @@ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8= _t bus_num) return NULL; } =20 -static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, + PCIBus *bus, int devfn) { - SMMUState *s =3D opaque; - SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); - SMMUDevice *sdev; static unsigned int index; + char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index= ++); + + sdev->smmu =3D s; + sdev->bus =3D bus; + sdev->devfn =3D devfn; + + memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), + s->mrtypename, + OBJECT(s), name, UINT64_MAX); + address_space_init(&sdev->as, + MEMORY_REGION(&sdev->iommu), name); + trace_smmu_add_mr(name); + g_free(name); +} + +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus) +{ + SMMUPciBus *sbus =3D g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus= ); =20 if (!sbus) { sbus =3D g_malloc0(sizeof(SMMUPciBus) + @@ -861,23 +877,19 @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, vo= id *opaque, int devfn) g_hash_table_insert(s->smmu_pcibus_by_busptr, bus, sbus); } =20 + return sbus; +} + +static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) +{ + SMMUDevice *sdev; + SMMUState *s =3D opaque; + SMMUPciBus *sbus =3D smmu_get_sbus(s, bus); + sdev =3D sbus->pbdev[devfn]; if (!sdev) { - char *name =3D g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, i= ndex++); - sdev =3D sbus->pbdev[devfn] =3D g_new0(SMMUDevice, 1); - - sdev->smmu =3D s; - sdev->bus =3D bus; - sdev->devfn =3D devfn; - - memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), - s->mrtypename, - OBJECT(s), name, UINT64_MAX); - address_space_init(&sdev->as, - MEMORY_REGION(&sdev->iommu), name); - trace_smmu_add_mr(name); - g_free(name); + smmu_init_sdev(s, sdev, bus, devfn); } =20 return &sdev->as; diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 80d0fecfde..c6f899e403 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -180,6 +180,12 @@ OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 +/* Return the SMMUPciBus handle associated to a PCI bus */ +SMMUPciBus *smmu_get_sbus(SMMUState *s, PCIBus *bus); + +/* Initialize SMMUDevice handle associated to a SMMUPCIBus */ +void smmu_init_sdev(SMMUState *s, SMMUDevice *sdev, PCIBus *bus, int devfn= ); + /* Return the stream ID of an SMMU device */ static inline uint16_t smmu_get_sid(SMMUDevice *sdev) { --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Jul 2025 23:59:38 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 766801402ED; Tue, 15 Jul 2025 00:00:51 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:00:42 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 04/15] hw/arm/smmu-common: Introduce smmu_iommu_ops_by_type() helper Date: Mon, 14 Jul 2025 16:59:30 +0100 Message-ID: <20250714155941.22176-5-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513060882116600 Allows to retrieve the=C2=A0PCIIOMMUOps based on the SMMU type. This will be useful when we add support for accelerated SMMUV3 in=C2=A0subsequent patches as that requires a different set of callbacks for=C2=A0iommu ops. No special handling is required for now and returns the default ops in base SMMU Class. No functional changes intended. Signed-off-by: Shameer Kolothum Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- hw/arm/smmu-common.c | 17 +++++++++++++++-- include/hw/arm/smmu-common.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 0f1a06cec2..3a1080773a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -934,6 +934,16 @@ void smmu_inv_notifiers_all(SMMUState *s) } } =20 +static const PCIIOMMUOps *smmu_iommu_ops_by_type(SMMUState *s) +{ + SMMUBaseClass *sbc; + + sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU)); + assert(sbc->iommu_ops); + + return sbc->iommu_ops; +} + static void smmu_base_realize(DeviceState *dev, Error **errp) { SMMUState *s =3D ARM_SMMU(dev); @@ -962,6 +972,7 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) */ if (pci_bus_is_express(pci_bus) && pci_bus_is_root(pci_bus) && object_dynamic_cast(OBJECT(pci_bus)->parent, TYPE_PCI_HOST_BRIDGE)= ) { + const PCIIOMMUOps *iommu_ops; /* * This condition matches either the default pcie.0, pxb-pcie, or * pxb-cxl. For both pxb-pcie and pxb-cxl, parent_dev will be set. @@ -974,10 +985,11 @@ static void smmu_base_realize(DeviceState *dev, Error= **errp) } } =20 + iommu_ops =3D smmu_iommu_ops_by_type(s); if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + pci_setup_iommu_per_bus(pci_bus, iommu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, iommu_ops, s); } return; } @@ -1018,6 +1030,7 @@ static void smmu_base_class_init(ObjectClass *klass, = const void *data) device_class_set_parent_realize(dc, smmu_base_realize, &sbc->parent_realize); rc->phases.exit =3D smmu_base_reset_exit; + sbc->iommu_ops =3D &smmu_ops; } =20 static const TypeInfo smmu_base_info =3D { diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index c6f899e403..eb94623555 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -171,6 +171,7 @@ struct SMMUBaseClass { /*< public >*/ =20 DeviceRealize parent_realize; + const PCIIOMMUOps *iommu_ops; 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Mon, 14 Jul 2025 23:57:33 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 74C2B14033F; Tue, 15 Jul 2025 00:01:00 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:00:51 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3 accel device Date: Mon, 14 Jul 2025 16:59:31 +0100 Message-ID: <20250714155941.22176-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513178480116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Also setup specific PCIIOMMUOps for accel SMMUv3 as accel SMMUv3 will have different handling for those ops callbacks in subsequent patches. The "accel" property is not yet added, so users cannot set it at this point. It will be introduced in a subsequent patch once the necessary support is in place. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/meson.build | 3 +- hw/arm/smmu-common.c | 6 +++- hw/arm/smmuv3-accel.c | 66 ++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 19 +++++++++++ include/hw/arm/smmu-common.h | 3 ++ 5 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 hw/arm/smmuv3-accel.c create mode 100644 hw/arm/smmuv3-accel.h diff --git a/hw/arm/meson.build b/hw/arm/meson.build index dc68391305..6126eb1b64 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -61,7 +61,8 @@ arm_common_ss.add(when: 'CONFIG_ARMSSE', if_true: files('= armsse.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'm= cimx7d-sabre.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: files('fsl-imx8mp.c'= )) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) -arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) +arm_ss.add(when: ['CONFIG_ARM_SMMUV3', 'CONFIG_IOMMUFD'], if_true: files('= smmuv3-accel.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 3a1080773a..6a58f574d3 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -938,7 +938,11 @@ static const PCIIOMMUOps *smmu_iommu_ops_by_type(SMMUS= tate *s) { SMMUBaseClass *sbc; =20 - sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU)); + if (s->accel) { + sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMUV3_ACCEL)= ); + } else { + sbc =3D ARM_SMMU_CLASS(object_class_by_name(TYPE_ARM_SMMU)); + } assert(sbc->iommu_ops); =20 return sbc->iommu_ops; diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c new file mode 100644 index 0000000000..2eac9c6ff4 --- /dev/null +++ b/hw/arm/smmuv3-accel.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" + +static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, + PCIBus *bus, int devfn) +{ + SMMUDevice *sdev =3D sbus->pbdev[devfn]; + SMMUv3AccelDevice *accel_dev; + + if (sdev) { + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + } else { + accel_dev =3D g_new0(SMMUv3AccelDevice, 1); + sdev =3D &accel_dev->sdev; + + sbus->pbdev[devfn] =3D sdev; + smmu_init_sdev(bs, sdev, bus, devfn); + } + + return accel_dev; +} + +static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus; + SMMUv3AccelDevice *accel_dev; + SMMUDevice *sdev; + + sbus =3D smmu_get_sbus(bs, bus); + accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, devfn); + sdev =3D &accel_dev->sdev; + + return &sdev->as; +} + +static const PCIIOMMUOps smmuv3_accel_ops =3D { + .get_address_space =3D smmuv3_accel_find_add_as, +}; + +static void smmuv3_accel_class_init(ObjectClass *oc, const void *data) +{ + SMMUBaseClass *sbc =3D ARM_SMMU_CLASS(oc); + + sbc->iommu_ops =3D &smmuv3_accel_ops; +} + +static const TypeInfo types[] =3D { + { + .name =3D TYPE_ARM_SMMUV3_ACCEL, + .parent =3D TYPE_ARM_SMMUV3, + .class_init =3D smmuv3_accel_class_init, + } +}; +DEFINE_TYPES(types) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h new file mode 100644 index 0000000000..4cf30b1291 --- /dev/null +++ b/hw/arm/smmuv3-accel.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd + * Copyright (C) 2025 NVIDIA + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_SMMUV3_ACCEL_H +#define HW_ARM_SMMUV3_ACCEL_H + +#include "hw/arm/smmu-common.h" +#include CONFIG_DEVICES + +typedef struct SMMUv3AccelDevice { + SMMUDevice sdev; +} SMMUv3AccelDevice; + +#endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index eb94623555..c459d24427 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -162,6 +162,7 @@ struct SMMUState { uint8_t bus_num; PCIBus *primary_bus; bool smmu_per_bus; /* SMMU is specific to the primary_bus */ + bool accel; /* SMMU has accelerator support */ }; =20 struct SMMUBaseClass { @@ -178,6 +179,8 @@ struct SMMUBaseClass { #define TYPE_ARM_SMMU "arm-smmu" OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) =20 +#define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" + /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); =20 --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 15 Jul 2025 00:01:09 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:01:00 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 06/15] hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints with iommufd Date: Mon, 14 Jul 2025 16:59:32 +0100 Message-ID: <20250714155941.22176-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Accelerated SMMUv3 is only useful when the device can take advantage of the host's SMMUv3 in nested mode. To keep things simple and correct, we only allow this feature for vfio-pci endpoint devices that use the iommufd backend. We also allow non-endpoint emulated devices like PCI bridges and root ports, so that users can plug in these vfio-pci devices. Another reason for this limit is to avoid problems with IOTLB invalidations. Some commands (e.g., CMD_TLBI_NH_ASID) lack an associated SID, making it difficult to trace the originating device. If we allowed emulated endpoint devices, QEMU would have to invalidate both its own software IOTLB and the host's hardware IOTLB, which could slow things down. Since vfio-pci devices in nested mode rely on the host SMMUv3's nested translation (S1+S2), their get_address_space() callback must return the system address space to enable correct S2 mappings of guest RAM. So in short: - vfio-pci devices return the system address space - bridges and root ports return the IOMMU address space Note: On ARM, MSI doorbell addresses are also translated via SMMUv3. Hence, if a vfio-pci device is behind the SMMuv3 with translation enabled, it must return the IOMMU address space for MSI. Support for this will be added in a follow-up patch. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/smmuv3-accel.c | 50 ++++++++++++++++++++++++++++- hw/arm/smmuv3-accel.h | 15 +++++++++ hw/arm/smmuv3.c | 4 +++ hw/pci-bridge/pci_expander_bridge.c | 1 - include/hw/arm/smmuv3.h | 1 + include/hw/pci/pci_bridge.h | 1 + 6 files changed, 70 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2eac9c6ff4..0b0ddb03e2 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,13 +7,19 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci-host/gpex.h" +#include "hw/vfio/pci.h" + #include "smmuv3-accel.h" =20 static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { + SMMUv3State *s =3D ARM_SMMUV3(bs); SMMUDevice *sdev =3D sbus->pbdev[devfn]; SMMUv3AccelDevice *accel_dev; =20 @@ -25,30 +31,72 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, =20 sbus->pbdev[devfn] =3D sdev; smmu_init_sdev(bs, sdev, bus, devfn); + address_space_init(&accel_dev->as_sysmem, &s->s_accel->root, + "smmuv3-accel-sysmem"); } =20 return accel_dev; } =20 +static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) +{ + + if (object_dynamic_cast(OBJECT(pdev), TYPE_PCI_BRIDGE) || + object_dynamic_cast(OBJECT(pdev), "pxb-pcie") || + object_dynamic_cast(OBJECT(pdev), "gpex-root")) { + return true; + } else if ((object_dynamic_cast(OBJECT(pdev), TYPE_VFIO_PCI) && + object_property_find(OBJECT(pdev), "iommufd"))) { + *vfio_pci =3D true; + return true; + } + return false; +} + static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque, int devfn) { + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); SMMUState *bs =3D opaque; + bool vfio_pci =3D false; SMMUPciBus *sbus; SMMUv3AccelDevice *accel_dev; SMMUDevice *sdev; =20 + if (pdev && !smmuv3_accel_pdev_allowed(pdev, &vfio_pci)) { + error_report("Device(%s) not allowed. Only PCIe root complex devic= es " + "or PCI bridge devices or vfio-pci endpoint devices w= ith " + "iommufd as backend is allowed with arm-smmuv3,accel= =3Don", + pdev->name); + exit(1); + } sbus =3D smmu_get_sbus(bs, bus); accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, devfn); sdev =3D &accel_dev->sdev; =20 - return &sdev->as; + if (vfio_pci) { + return &accel_dev->as_sysmem; + } else { + return &sdev->as; + } } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, }; =20 +void smmuv3_accel_init(SMMUv3State *s) +{ + SMMUv3AccelState *s_accel; + + s->s_accel =3D s_accel =3D g_new0(SMMUv3AccelState, 1); + memory_region_init(&s_accel->root, OBJECT(s), "root", UINT64_MAX); + memory_region_init_alias(&s_accel->sysmem, OBJECT(s), + "smmuv3-accel-sysmem", get_system_memory(), 0, + memory_region_size(get_system_memory())); + memory_region_add_subregion(&s_accel->root, 0, &s_accel->sysmem); +} + static void smmuv3_accel_class_init(ObjectClass *oc, const void *data) { SMMUBaseClass *sbc =3D ARM_SMMU_CLASS(oc); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 4cf30b1291..2cd343103f 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -9,11 +9,26 @@ #ifndef HW_ARM_SMMUV3_ACCEL_H #define HW_ARM_SMMUV3_ACCEL_H =20 +#include "hw/arm/smmuv3.h" #include "hw/arm/smmu-common.h" #include CONFIG_DEVICES =20 typedef struct SMMUv3AccelDevice { SMMUDevice sdev; + AddressSpace as_sysmem; } SMMUv3AccelDevice; =20 +typedef struct SMMUv3AccelState { + MemoryRegion root; + MemoryRegion sysmem; +} SMMUv3AccelState; + +#if defined(CONFIG_ARM_SMMUV3) && defined(CONFIG_IOMMUFD) +void smmuv3_accel_init(SMMUv3State *s); +#else +static inline void smmuv3_accel_init(SMMUv3State *d) +{ +} +#endif + #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bcf8af8dc7..2f5a8157dd 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -32,6 +32,7 @@ #include "qapi/error.h" =20 #include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" #include "smmuv3-internal.h" #include "smmu-internal.h" =20 @@ -1898,6 +1899,9 @@ static void smmu_realize(DeviceState *d, Error **errp) sysbus_init_mmio(dev, &sys->iomem); =20 smmu_init_irq(s, dev); + if (sys->accel) { + smmuv3_accel_init(s); + } } =20 static const VMStateDescription vmstate_smmuv3_queue =3D { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 1bcceddbc4..a8eb2d2426 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -48,7 +48,6 @@ struct PXBBus { char bus_path[8]; }; =20 -#define TYPE_PXB_PCIE_DEV "pxb-pcie" OBJECT_DECLARE_SIMPLE_TYPE(PXBPCIEDev, PXB_PCIE_DEV) =20 static GList *pxb_dev_list; diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d183a62766..3bdb92391a 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + struct SMMUv3AccelState *s_accel; }; =20 typedef enum { diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a055fd8d32..b61360b900 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -106,6 +106,7 @@ typedef struct PXBPCIEDev { =20 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus" #define TYPE_PXB_CXL_BUS "pxb-cxl-bus" +#define TYPE_PXB_PCIE_DEV "pxb-pcie" #define TYPE_PXB_DEV "pxb" OBJECT_DECLARE_SIMPLE_TYPE(PXBDev, PXB_DEV) =20 --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" For accelerated SMMUv3, we need nested parent domain creation. Add the callback support so that VFIO can create a nested parent. Since 'accel=3Don' for SMMUv3 requires the guest SMMUv3 to be configured in Stage 1 mode, ensure that the 'stage' property is explicitly set to Stage 1. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/smmuv3-accel.c | 15 +++++++++++++++ hw/arm/virt.c | 12 ++++++++++++ 2 files changed, 27 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 0b0ddb03e2..66cd4f5ece 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -10,6 +10,7 @@ #include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/iommu.h" #include "hw/pci/pci_bridge.h" #include "hw/pci-host/gpex.h" #include "hw/vfio/pci.h" @@ -81,8 +82,22 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bu= s, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_viommu_cap(void *opaque) +{ + /* + * Accelerated smmuv3 support only allowes Guest S1 + * configuration. Hence report VIOMMU_CAP_STAGE1 + * so that VFIO can create nested parent domain. + * The real nested support should be reported from host + * SMMUv3 and if it doesn't, the nested parent allocation + * will fail anyway. + */ + return VIOMMU_CAP_STAGE1; +} + static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, + .get_viommu_cap =3D smmuv3_accel_get_viommu_cap, }; =20 void smmuv3_accel_init(SMMUv3State *s) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 22393cf39e..fdb47eda6a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3053,6 +3053,18 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, return; } =20 + if (object_property_get_bool(OBJECT(dev), "accel", &error_abor= t)) { + char *stage; + + stage =3D object_property_get_str(OBJECT(dev), "stage", + &error_fatal); + if (*stage && strcmp("1", stage)) { + error_setg(errp, "Only stage1 is supported for SMMUV3 = with " + "accel=3Don"); + return; + } + } + create_smmuv3_dev_dtb(vms, dev, bus); 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charset="utf-8" From: Nicolin Chen Implement a set_iommu_device callback: -If found an existing viommu reuse that. (Devices behind the same physical SMMU should share an S2 HWPT) -Else, Allocate a viommu with the nested parent S2 hwpt allocated by VFIO. Allocate bypass and abort hwpt. -And add the dev to viommu device list Also add an unset_iommu_device to unwind/cleanup above. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 154 +++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 20 +++++ hw/arm/trace-events | 4 + include/system/iommufd.h | 6 ++ 4 files changed, 184 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 66cd4f5ece..fe90d48675 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "trace.h" #include "qemu/error-report.h" =20 #include "hw/arm/smmuv3.h" @@ -17,6 +18,9 @@ =20 #include "smmuv3-accel.h" =20 +#define SMMU_STE_VALID (1ULL << 0) +#define SMMU_STE_CFG_BYPASS (1ULL << 3) + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { @@ -39,6 +43,154 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, return accel_dev; } =20 +static bool +smmuv3_accel_dev_alloc_viommu(SMMUv3AccelDevice *accel_dev, + HostIOMMUDeviceIOMMUFD *idev, Error **errp) +{ + struct iommu_hwpt_arm_smmuv3 bypass_data =3D { + .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, + }; + struct iommu_hwpt_arm_smmuv3 abort_data =3D { + .ste =3D { SMMU_STE_VALID, 0x0ULL }, + }; + SMMUDevice *sdev =3D &accel_dev->sdev; + SMMUState *bs =3D sdev->smmu; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t s2_hwpt_id =3D idev->hwpt_id; + SMMUS2Hwpt *s2_hwpt; + SMMUViommu *viommu; + uint32_t viommu_id; + + if (s_accel->viommu) { + accel_dev->viommu =3D s_accel->viommu; + return true; + } + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, &viommu_id, errp)) { + return false; + } + + viommu =3D g_new0(SMMUViommu, 1); + viommu->core.viommu_id =3D viommu_id; + viommu->core.s2_hwpt_id =3D s2_hwpt_id; + viommu->core.iommufd =3D idev->iommufd; + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(abort_data), &abort_data, + &viommu->abort_hwpt_id, errp)) { + goto free_viommu; + } + + if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, 0, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(bypass_data), &bypass_data, + &viommu->bypass_hwpt_id, errp)) { + goto free_abort_hwpt; + } + + s2_hwpt =3D g_new(SMMUS2Hwpt, 1); + s2_hwpt->iommufd =3D idev->iommufd; + s2_hwpt->hwpt_id =3D s2_hwpt_id; + + viommu->iommufd =3D idev->iommufd; + viommu->s2_hwpt =3D s2_hwpt; + + s_accel->viommu =3D viommu; + accel_dev->viommu =3D viommu; + return true; + +free_abort_hwpt: + iommufd_backend_free_id(idev->iommufd, viommu->abort_hwpt_id); +free_viommu: + iommufd_backend_free_id(idev->iommufd, viommu->core.viommu_id); + g_free(viommu); + return false; +} + +static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, + HostIOMMUDevice *hiod, Error **e= rrp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(hiod); + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); + SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + SMMUDevice *sdev =3D &accel_dev->sdev; + + if (!idev) { + return true; + } + + if (accel_dev->idev) { + if (accel_dev->idev !=3D idev) { + error_report("Device 0x%x already has an associated idev", + smmu_get_sid(sdev)); + return false; + } else { + return true; + } + } + + if (!smmuv3_accel_dev_alloc_viommu(accel_dev, idev, errp)) { + error_report("Device 0x%x: Unable to alloc viommu", smmu_get_sid(s= dev)); + return false; + } + + accel_dev->idev =3D idev; + QLIST_INSERT_HEAD(&s_accel->viommu->device_list, accel_dev, next); + trace_smmuv3_accel_set_iommu_device(devfn, smmu_get_sid(sdev)); + return true; +} + +static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); + SMMUv3AccelDevice *accel_dev; + SMMUViommu *viommu; + SMMUDevice *sdev; + + if (!sbus) { + return; + } + + sdev =3D sbus->pbdev[devfn]; + if (!sdev) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + accel_dev->idev->hwpt_id, + NULL)) { + error_report("Unable to attach dev to the default HW pagetable"); + } + + accel_dev->idev =3D NULL; + QLIST_REMOVE(accel_dev, next); + trace_smmuv3_accel_unset_iommu_device(devfn, smmu_get_sid(sdev)); + + viommu =3D s->s_accel->viommu; + if (QLIST_EMPTY(&viommu->device_list)) { + iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); + iommufd_backend_free_id(viommu->iommufd, viommu->core.viommu_id); + iommufd_backend_free_id(viommu->iommufd, viommu->s2_hwpt->hwpt_id); + g_free(viommu->s2_hwpt); + g_free(viommu); + s->s_accel->viommu =3D NULL; + } +} + static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) { =20 @@ -98,6 +250,8 @@ static uint64_t smmuv3_accel_get_viommu_cap(void *opaque) static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_address_space =3D smmuv3_accel_find_add_as, .get_viommu_cap =3D smmuv3_accel_get_viommu_cap, + .set_iommu_device =3D smmuv3_accel_set_iommu_device, + .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, }; =20 void smmuv3_accel_init(SMMUv3State *s) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 2cd343103f..55a6a353fc 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -11,16 +11,36 @@ =20 #include "hw/arm/smmuv3.h" #include "hw/arm/smmu-common.h" +#include "system/iommufd.h" +#include #include CONFIG_DEVICES =20 +typedef struct SMMUS2Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; +} SMMUS2Hwpt; + +typedef struct SMMUViommu { + IOMMUFDBackend *iommufd; + IOMMUFDViommu core; + SMMUS2Hwpt *s2_hwpt; + uint32_t bypass_hwpt_id; + uint32_t abort_hwpt_id; + QLIST_HEAD(, SMMUv3AccelDevice) device_list; +} SMMUViommu; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; AddressSpace as_sysmem; + HostIOMMUDeviceIOMMUFD *idev; + SMMUViommu *viommu; + QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 typedef struct SMMUv3AccelState { MemoryRegion root; MemoryRegion sysmem; + SMMUViommu *viommu; } SMMUv3AccelState; =20 #if defined(CONFIG_ARM_SMMUV3) && defined(CONFIG_IOMMUFD) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f3386bd7ae..c4537ca1d6 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -66,6 +66,10 @@ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotif= ier node for iommu mr=3D%s smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t i= ova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=3D%s asid=3D%d vm= id=3D%d iova=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" stage=3D%d" smmu_reset_exit(void) "" =20 +#smmuv3-accel.c +smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" +smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 6ab3ba3cb6..b7ad2cf10c 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -38,6 +38,12 @@ struct IOMMUFDBackend { /*< public >*/ }; =20 +typedef struct IOMMUFDViommu { + IOMMUFDBackend *iommufd; + uint32_t s2_hwpt_id; + uint32_t viommu_id; +} IOMMUFDViommu; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752512446; cv=none; d=zohomail.com; s=zohoarc; b=eCdMzth1oYxhA3KL593m/nZCKTTOflKfFKlbNGQlJyyuAtLlLWyFmLS6yHrgds7ksk3Ym0IhCPjCd7EogUSosV+MGfythVc8UuXpT6szHn1aSjlaGc9SjimteRwk5hwv/y6ud1L90hD67U6zNRHirnbbCFOvwyNjA+rwuCsd9bk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752512446; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" From: Nicolin Chen Allocates a s1 HWPT for the Guest s1 stage and attaches that to the dev. This will be invoked when Guest issues SMMU_CMD_CFGI_STE/STE_RANGE. While at it, we are also exporting both smmu_find_ste() and smmuv3_flush_config() from smmuv3.c for use here. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 130 +++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 17 +++++ hw/arm/smmuv3-internal.h | 4 ++ hw/arm/smmuv3.c | 8 ++- hw/arm/trace-events | 1 + 5 files changed, 157 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index fe90d48675..74bf20cfaf 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,9 +18,139 @@ =20 #include "smmuv3-accel.h" =20 +#include "smmuv3-internal.h" + #define SMMU_STE_VALID (1ULL << 0) #define SMMU_STE_CFG_BYPASS (1ULL << 3) =20 +static void +smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort) +{ + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + uint32_t hwpt_id; + + if (!s1_hwpt || !accel_dev->viommu) { + return; + } + + if (abort) { + hwpt_id =3D accel_dev->viommu->abort_hwpt_id; + } else { + hwpt_id =3D accel_dev->viommu->bypass_hwpt_id; + } + + host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, &error_abort); + iommufd_backend_free_id(s1_hwpt->iommufd, s1_hwpt->hwpt_id); + accel_dev->s1_hwpt =3D NULL; + g_free(s1_hwpt); +} + +static int +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev, + uint32_t data_type, uint32_t data_len, + void *data) +{ + SMMUViommu *viommu =3D accel_dev->viommu; + SMMUS1Hwpt *s1_hwpt =3D accel_dev->s1_hwpt; + HostIOMMUDeviceIOMMUFD *idev =3D accel_dev->idev; + uint32_t flags =3D 0; + + if (!idev || !viommu) { + return -ENOENT; + } + + if (s1_hwpt) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, true); + } + + s1_hwpt =3D g_new0(SMMUS1Hwpt, 1); + s1_hwpt->iommufd =3D idev->iommufd; + iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + viommu->core.viommu_id, flags, data_type, + data_len, data, &s1_hwpt->hwpt_id, &error_a= bort); + host_iommu_device_iommufd_attach_hwpt(idev, s1_hwpt->hwpt_id, &error_a= bort); + accel_dev->s1_hwpt =3D s1_hwpt; + return 0; +} + +void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int = sid) +{ + SMMUv3AccelDevice *accel_dev; + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + struct iommu_hwpt_arm_smmuv3 nested_data =3D {}; + uint32_t config; + STE ste; + int ret; + + if (!bs->accel) { + return; + } + + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + if (!accel_dev->viommu) { + return; + } + + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); + if (ret) { + error_report("failed to find STE for sid 0x%x", sid); + return; + } + + config =3D STE_CONFIG(&ste); + if (!STE_VALID(&ste) || !STE_CFG_S1_ENABLED(config)) { + smmuv3_accel_dev_uninstall_nested_ste(accel_dev, STE_CFG_ABORT(con= fig)); + smmuv3_flush_config(sdev); + return; + } + + nested_data.ste[0] =3D (uint64_t)ste.word[0] | (uint64_t)ste.word[1] <= < 32; + nested_data.ste[1] =3D (uint64_t)ste.word[2] | (uint64_t)ste.word[3] <= < 32; + /* V | CONFIG | S1FMT | S1CTXPTR | S1CDMAX */ + nested_data.ste[0] &=3D 0xf80fffffffffffffULL; + /* S1DSS | S1CIR | S1COR | S1CSH | S1STALLD | EATS */ + nested_data.ste[1] &=3D 0x380000ffULL; + ret =3D smmuv3_accel_dev_install_nested_ste(accel_dev, + IOMMU_HWPT_DATA_ARM_SMMUV3, + sizeof(nested_data), + &nested_data); + if (ret) { + error_report("Unable to install nested STE=3D%16LX:%16LX, sid=3D0x= %x," + "ret=3D%d", nested_data.ste[1], nested_data.ste[0], + sid, ret); + } + + trace_smmuv3_accel_install_nested_ste(sid, nested_data.ste[1], + nested_data.ste[0]); +} + +static void +smmuv3_accel_ste_range(gpointer key, gpointer value, gpointer user_data) +{ + SMMUDevice *sdev =3D (SMMUDevice *)key; + uint32_t sid =3D smmu_get_sid(sdev); + SMMUSIDRange *sid_range =3D (SMMUSIDRange *)user_data; + + if (sid >=3D sid_range->start && sid <=3D sid_range->end) { + SMMUv3State *s =3D sdev->smmu; + SMMUState *bs =3D &s->smmu_state; + + smmuv3_accel_install_nested_ste(bs, sdev, sid); + } +} + +void +smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) +{ + if (!bs->accel) { + return; + } + + g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range); +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 55a6a353fc..06e81b630d 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -29,10 +29,16 @@ typedef struct SMMUViommu { QLIST_HEAD(, SMMUv3AccelDevice) device_list; } SMMUViommu; =20 +typedef struct SMMUS1Hwpt { + IOMMUFDBackend *iommufd; + uint32_t hwpt_id; +} SMMUS1Hwpt; + typedef struct SMMUv3AccelDevice { SMMUDevice sdev; AddressSpace as_sysmem; HostIOMMUDeviceIOMMUFD *idev; + SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; @@ -45,10 +51,21 @@ typedef struct SMMUv3AccelState { =20 #if defined(CONFIG_ARM_SMMUV3) && defined(CONFIG_IOMMUFD) void smmuv3_accel_init(SMMUv3State *s); +void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int = sid); +void smmuv3_accel_install_nested_ste_range(SMMUState *bs, + SMMUSIDRange *range); #else static inline void smmuv3_accel_init(SMMUv3State *d) { } +static inline void +smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int sid) +{ +} +static inline void +smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index b6b7399347..738061c6ad 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -547,6 +547,10 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, + SMMUEventInfo *event); +void smmuv3_flush_config(SMMUDevice *sdev); + /* STE fields */ =20 #define STE_VALID(x) extract32((x)->word[0], 0, 1) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2f5a8157dd..c94bfe6564 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -630,8 +630,8 @@ bad_ste: * Supports linear and 2-level stream table * Return 0 on success, -EINVAL otherwise */ -static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, - SMMUEventInfo *event) +int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, + SMMUEventInfo *event) { dma_addr_t addr, strtab_base; uint32_t log2size; @@ -900,7 +900,7 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sdev= , SMMUEventInfo *event) return cfg; } =20 -static void smmuv3_flush_config(SMMUDevice *sdev) +void smmuv3_flush_config(SMMUDevice *sdev) { SMMUv3State *s =3D sdev->smmu; SMMUState *bc =3D &s->smmu_state; @@ -1342,6 +1342,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_ste(sid); smmuv3_flush_config(sdev); + smmuv3_accel_install_nested_ste(bs, sdev, sid); =20 break; } @@ -1361,6 +1362,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) sid_range.end =3D sid_range.start + mask; =20 trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.en= d); + smmuv3_accel_install_nested_ste_range(bs, &sid_range); smmu_configs_inv_sid_range(bs, sid_range); break; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c4537ca1d6..7d232ca17c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -69,6 +69,7 @@ smmu_reset_exit(void) "" #smmuv3-accel.c smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" +smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" From: Nicolin Chen Allocate and associate a vDEVICE object for the Guest device with the vIOMMU. This will help the kernel to do the vSID --> sid translation whenever required (eg: device specific invalidations). Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 25 +++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 1 + include/system/iommufd.h | 5 +++++ 3 files changed, 31 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 74bf20cfaf..f1584dd775 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -93,6 +93,23 @@ void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMU= Device *sdev, int sid) return; } =20 + if (!accel_dev->vdev && accel_dev->idev) { + IOMMUFDVdev *vdev; + uint32_t vdev_id; + SMMUViommu *viommu =3D accel_dev->viommu; + + iommufd_backend_alloc_vdev(viommu->core.iommufd, accel_dev->idev->= devid, + viommu->core.viommu_id, sid, &vdev_id, + &error_abort); + vdev =3D g_new(IOMMUFDVdev, 1); + vdev->vdev_id =3D vdev_id; + vdev->dev_id =3D sid; + accel_dev->vdev =3D vdev; + host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, + accel_dev->viommu->bypass_hw= pt_id, + &error_abort); + } + ret =3D smmu_find_ste(sdev->smmu, sid, &ste, &event); if (ret) { error_report("failed to find STE for sid 0x%x", sid); @@ -287,6 +304,7 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus= , void *opaque, SMMUPciBus *sbus =3D g_hash_table_lookup(bs->smmu_pcibus_by_busptr, bu= s); SMMUv3AccelDevice *accel_dev; SMMUViommu *viommu; + IOMMUFDVdev *vdev; SMMUDevice *sdev; =20 if (!sbus) { @@ -310,6 +328,13 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, trace_smmuv3_accel_unset_iommu_device(devfn, smmu_get_sid(sdev)); =20 viommu =3D s->s_accel->viommu; + vdev =3D accel_dev->vdev; + if (vdev) { + iommufd_backend_free_id(viommu->iommufd, vdev->vdev_id); + g_free(vdev); + accel_dev->vdev =3D NULL; + } + if (QLIST_EMPTY(&viommu->device_list)) { iommufd_backend_free_id(viommu->iommufd, viommu->bypass_hwpt_id); iommufd_backend_free_id(viommu->iommufd, viommu->abort_hwpt_id); diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 06e81b630d..21028e60c8 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -40,6 +40,7 @@ typedef struct SMMUv3AccelDevice { HostIOMMUDeviceIOMMUFD *idev; SMMUS1Hwpt *s1_hwpt; SMMUViommu *viommu; + IOMMUFDVdev *vdev; QLIST_ENTRY(SMMUv3AccelDevice) next; } SMMUv3AccelDevice; =20 diff --git a/include/system/iommufd.h b/include/system/iommufd.h index b7ad2cf10c..8de559d448 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -44,6 +44,11 @@ typedef struct IOMMUFDViommu { uint32_t viommu_id; } IOMMUFDViommu; =20 +typedef struct IOMMUFDVdev { + uint32_t vdev_id; + uint32_t dev_id; +} IOMMUFDVdev; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752513310; cv=none; d=zohomail.com; s=zohoarc; b=Paf7MSCHPjvRJ/rUwY9PLyZO8dMMpMueUQwJP3yOFw2i06pxfEdC9hZQHybkpXb3JO+zK5fBtsEhWW6q6vmKaEaSaxH4Bwq3vuEk1H0dGKwvELioxo1F3cebIaeD+FOXtkpEANYLrdRqO1aQxgZrHCU2iAiDLU/ROpMX12FjvBU= ARC-Message-Signature: i=1; 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Mon, 14 Jul 2025 18:01:46 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 11/15] hw/pci/pci: Introduce optional get_msi_address_space() callback. Date: Mon, 14 Jul 2025 16:59:37 +0100 Message-ID: <20250714155941.22176-12-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513312281116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On ARM, when a device is behind an IOMMU, its MSI doorbell address is subject to translation by the IOMMU. This behavior affects vfio-pci passthrough devices assigned to guests using an accelerated SMMUv3. In this setup, we configure the host SMMUv3 in nested mode, where VFIO sets up the Stage-2 (S2) mappings for guest RAM, while the guest controls Stage-1 (S1). To allow VFIO to correctly configure S2 mappings, we currently return the system address space via the get_address_space() callback for vfio-pci devices. However, QEMU/KVM also uses this same callback path when resolving the address space for MSI doorbells: kvm_irqchip_add_msi_route() kvm_arch_fixup_msi_route() pci_device_iommu_address_space() This leads to problems when MSI doorbells need to be translated. To fix this, introduce an optional get_msi_address_space() callback. In the SMMUv3 accelerated case, this callback returns the IOMMU address space if the guest has set up S1 translations for the vfio-pci device. Otherwise, it returns the system address space. Suggested-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 25 +++++++++++++++++++++++++ hw/pci/pci.c | 19 +++++++++++++++++++ include/hw/pci/pci.h | 16 ++++++++++++++++ target/arm/kvm.c | 2 +- 4 files changed, 61 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f1584dd775..04c665ccf5 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -346,6 +346,30 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, } } =20 +static AddressSpace *smmuv3_accel_find_msi_as(PCIBus *bus, void *opaque, + int devfn) +{ + SMMUState *bs =3D opaque; + SMMUPciBus *sbus; + SMMUv3AccelDevice *accel_dev; + SMMUDevice *sdev; + + sbus =3D smmu_get_sbus(bs, bus); + accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, devfn); + sdev =3D &accel_dev->sdev; + + /* + * If the assigned vfio-pci dev has S1 translation enabled by + * Guest, return IOMMU address space for MSI translation. + * Otherwise, return system address space. + */ + if (accel_dev->s1_hwpt) { + return &sdev->as; + } else { + return &accel_dev->as_sysmem; + } +} + static bool smmuv3_accel_pdev_allowed(PCIDevice *pdev, bool *vfio_pci) { =20 @@ -407,6 +431,7 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_viommu_cap =3D smmuv3_accel_get_viommu_cap, .set_iommu_device =3D smmuv3_accel_set_iommu_device, .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, + .get_msi_address_space =3D smmuv3_accel_find_msi_as, }; =20 void smmuv3_accel_init(SMMUv3State *s) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 13de0e2809..404aeb643d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2957,6 +2957,25 @@ AddressSpace *pci_device_iommu_address_space(PCIDevi= ce *dev) return &address_space_memory; } =20 +AddressSpace *pci_device_iommu_msi_address_space(PCIDevice *dev) +{ + PCIBus *bus; + PCIBus *iommu_bus; + int devfn; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); + if (iommu_bus) { + if (iommu_bus->iommu_ops->get_msi_address_space) { + return iommu_bus->iommu_ops->get_msi_address_space(bus, + iommu_bus->iommu_opaque, devfn); + } else { + return iommu_bus->iommu_ops->get_address_space(bus, + iommu_bus->iommu_opaque, devfn); + } + } + return &address_space_memory; +} + int pci_iommu_init_iotlb_notifier(PCIDevice *dev, IOMMUNotifier *n, IOMMUNotify fn, void *opaque) { diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index d1d43e9fb9..55138c406e 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -639,12 +639,28 @@ typedef struct PCIIOMMUOps { uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is= _read, bool is_write); + /** + * @get_msi_address_space: get the address space for MSI doorbell addr= ess + * for devices + * + * Optional callback which returns a pointer to an #AddressSpace. This + * is required if MSI doorbell also gets translated through IOMMU(eg: = ARM) + * + * @bus: the #PCIBus being accessed. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * @devfn: device and function number + */ + AddressSpace * (*get_msi_address_space)(PCIBus *bus, void *opaque, + int devfn); } PCIIOMMUOps; =20 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); +AddressSpace *pci_device_iommu_msi_address_space(PCIDevice *dev); =20 /** * pci_device_get_viommu_cap: get vIOMMU capabilities. diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6672344855..c78d0d59bb 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1535,7 +1535,7 @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, in= t level) int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, uint64_t address, uint32_t data, PCIDevice *d= ev) { - AddressSpace *as =3D pci_device_iommu_address_space(dev); + AddressSpace *as =3D pci_device_iommu_msi_address_space(dev); hwaddr xlat, len, doorbell_gpa; MemoryRegionSection mrs; MemoryRegion *mr; --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752512905; cv=none; d=zohomail.com; s=zohoarc; b=ltTP6bDwk/38alyQiIv1p4lOvIAD+AnTcdunhBAvlNyNYhRPTHDw9QFDfHRhPoCn/dTvCK/YjS3w1w1ieossIZowVv9NbVnk4p+ZbZKnYhLeYwyA/X3vmEiNm0v2UB2ix8EjZtb4VbhEvawwzmn+j0x9KkWT8i9VxFQX1HjkgeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752512905; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" From: Nicolin Chen Helpers will batch the commands and issue at once to host SMMUv3. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 65 ++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 16 ++++++++++ hw/arm/smmuv3-internal.h | 12 ++++++++ 3 files changed, 93 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 04c665ccf5..1298b4f6d0 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -168,6 +168,71 @@ smmuv3_accel_install_nested_ste_range(SMMUState *bs, S= MMUSIDRange *range) g_hash_table_foreach(bs->configs, smmuv3_accel_ste_range, range); } =20 +/* Update batch->ncmds to the number of execute cmds */ +bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch) +{ + SMMUv3State *s =3D ARM_SMMUV3(bs); + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t total =3D batch->ncmds; + IOMMUFDViommu *viommu_core; + int ret; + + if (!bs->accel) { + return true; + } + + if (!s_accel->viommu) { + return true; + } + + viommu_core =3D &s_accel->viommu->core; + ret =3D iommufd_backend_invalidate_cache(viommu_core->iommufd, + viommu_core->viommu_id, + IOMMU_VIOMMU_INVALIDATE_DATA_AR= M_SMMUV3, + sizeof(Cmd), &batch->ncmds, + batch->cmds, NULL); + if (!ret || total !=3D batch->ncmds) { + error_report("%s failed: ret=3D%d, total=3D%d, done=3D%d", + __func__, ret, total, batch->ncmds); + return ret; + } + + batch->ncmds =3D 0; + return ret; +} + +/* + * Note: sdev can be NULL for certain invalidation commands + * e.g., SMMU_CMD_TLBI_NH_ASID, SMMU_CMD_TLBI_NH_VA etc. + */ +void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, Cmd *cmd, + uint32_t *cons) +{ + if (!bs->accel) { + return; + } + + /* + * We may end up here for any emulated PCI bridge or root port type + * devices. The batching of commands only matters for vfio-pci endpoint + * devices with Guest S1 translation enabled. Hence check that, if + * sdev is available. + */ + if (sdev) { + SMMUv3AccelDevice *accel_dev; + accel_dev =3D container_of(sdev, SMMUv3AccelDevice, sdev); + + if (!accel_dev->s1_hwpt) { + return; + } + } + + batch->cmds[batch->ncmds] =3D *cmd; + batch->cons[batch->ncmds++] =3D *cons; + return; +} + static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUState *bs, SMMUPciBus *= sbus, PCIBus *bus, int devfn) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 21028e60c8..d06c9664ba 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -13,6 +13,7 @@ #include "hw/arm/smmu-common.h" #include "system/iommufd.h" #include +#include "smmuv3-internal.h" #include CONFIG_DEVICES =20 typedef struct SMMUS2Hwpt { @@ -55,6 +56,10 @@ void smmuv3_accel_init(SMMUv3State *s); void smmuv3_accel_install_nested_ste(SMMUState *bs, SMMUDevice *sdev, int = sid); void smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range); +bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch); +void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, struct Cmd *cmd, + uint32_t *cons); #else static inline void smmuv3_accel_init(SMMUv3State *d) { @@ -67,6 +72,17 @@ static inline void smmuv3_accel_install_nested_ste_range(SMMUState *bs, SMMUSIDRange *range) { } +static inline bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, + SMMUCommandBatch *batch) +{ + return true; +} +static inline void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, + SMMUCommandBatch *batch, + struct Cmd *cmd, uint32_t *cons) +{ + return; +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 738061c6ad..8cb6a9238a 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -547,6 +547,18 @@ typedef struct CD { uint32_t word[16]; } CD; =20 +/* + * SMMUCommandBatch - batch of invalidation commands for accel smmuv3 + * @cmds: Pointer to list of commands + * @cons: Pointer to list of CONS corresponding to the commands + * @ncmds: Number of cmds in the batch + */ +typedef struct SMMUCommandBatch { + struct Cmd *cmds; + uint32_t *cons; + uint32_t ncmds; +} SMMUCommandBatch; + int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, SMMUEventInfo *event); void smmuv3_flush_config(SMMUDevice *sdev); --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1752513292; cv=none; d=zohomail.com; s=zohoarc; b=fvdQr/R+otP04gCdXYSzZGIQT3JowwEOGcRvC9VnjM65VM72pb6lbpaH+ms9Q7z6z8mnHEY02EtkDxxYDBvEdwbH2BLNuThtmAUkiwL7hqRLDJk0NPRSjh8oN5v2N3tfiHXst80cNE7dxZHzuYrtUAZFDhB5VvcCdp/O7wUb51k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752513292; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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charset="utf-8" From: Nicolin Chen Use the provided smmuv3-accel helper functions to issue the invalidation commands to host SMMUv3. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-internal.h | 11 +++++++++++ hw/arm/smmuv3.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 8cb6a9238a..f3aeaf6375 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -233,6 +233,17 @@ static inline bool smmuv3_gerror_irq_enabled(SMMUv3Sta= te *s) #define Q_CONS_WRAP(q) (((q)->cons & WRAP_MASK(q)) >> (q)->log2size) #define Q_PROD_WRAP(q) (((q)->prod & WRAP_MASK(q)) >> (q)->log2size) =20 +static inline int smmuv3_q_ncmds(SMMUQueue *q) +{ + uint32_t prod =3D Q_PROD(q); + uint32_t cons =3D Q_CONS(q); + + if (Q_PROD_WRAP(q) =3D=3D Q_CONS_WRAP(q)) + return prod - cons; + else + return WRAP_MASK(q) - cons + prod; +} + static inline bool smmuv3_q_full(SMMUQueue *q) { return ((q->cons ^ q->prod) & WRAP_INDEX_MASK(q)) =3D=3D WRAP_MASK(q); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c94bfe6564..97ecca0764 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1285,10 +1285,17 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; SMMUQueue *q =3D &s->cmdq; SMMUCommandType type =3D 0; + SMMUCommandBatch batch =3D {}; + uint32_t ncmds; =20 if (!smmuv3_cmdq_enabled(s)) { return 0; } + + ncmds =3D smmuv3_q_ncmds(q); + batch.cmds =3D g_new0(Cmd, ncmds); + batch.cons =3D g_new0(uint32_t, ncmds); + /* * some commands depend on register values, typically CR0. In case tho= se * register values change while handling the command, spec says it @@ -1383,6 +1390,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) =20 trace_smmuv3_cmdq_cfgi_cd(sid); smmuv3_flush_config(sdev); + smmuv3_accel_batch_cmd(sdev->smmu, sdev, &batch, &cmd, &q->con= s); break; } case SMMU_CMD_TLBI_NH_ASID: @@ -1406,6 +1414,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nh_asid(asid); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + smmuv3_accel_batch_cmd(bs, NULL, &batch, &cmd, &q->cons); break; } case SMMU_CMD_TLBI_NH_ALL: @@ -1433,6 +1442,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); smmu_iotlb_inv_all(bs); + smmuv3_accel_batch_cmd(bs, NULL, &batch, &cmd, &q->cons); break; case SMMU_CMD_TLBI_NH_VAA: case SMMU_CMD_TLBI_NH_VA: @@ -1441,6 +1451,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) break; } smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + smmuv3_accel_batch_cmd(bs, NULL, &batch, &cmd, &q->cons); break; case SMMU_CMD_TLBI_S12_VMALL: { @@ -1499,12 +1510,29 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) queue_cons_incr(q); } =20 + qemu_mutex_lock(&s->mutex); + if (!cmd_error && batch.ncmds) { + if (!smmuv3_accel_issue_cmd_batch(bs, &batch)) { + if (batch.ncmds) { + q->cons =3D batch.cons[batch.ncmds - 1]; + } else { + q->cons =3D batch.cons[0]; /* FIXME: Check */ + } + qemu_log_mask(LOG_GUEST_ERROR, "Illegal command type: %d\n", + CMD_TYPE(&batch.cmds[batch.ncmds])); + cmd_error =3D SMMU_CERROR_ILL; + } + } + qemu_mutex_unlock(&s->mutex); + if (cmd_error) { trace_smmuv3_cmdq_consume_error(smmu_cmd_string(type), cmd_error); smmu_write_cmdq_err(s, cmd_error); smmuv3_trigger_irq(s, SMMU_IRQ_GERROR, R_GERROR_CMDQ_ERR_MASK); } =20 + g_free(batch.cmds); + g_free(batch.cons); trace_smmuv3_cmdq_consume_out(Q_PROD(q), Q_CONS(q), Q_PROD_WRAP(q), Q_CONS_WRAP(q)); =20 --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Jul 2025 23:58:54 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 5290214038F; Tue, 15 Jul 2025 00:02:22 +0800 (CST) Received: from A2303104131.china.huawei.com (10.203.177.241) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 14 Jul 2025 18:02:13 +0200 To: , CC: , , , , , , , , , , , , , , , Subject: [RFC PATCH v3 14/15] Read and validate host SMMUv3 feature bits Date: Mon, 14 Jul 2025 16:59:40 +0100 Message-ID: <20250714155941.22176-15-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> References: <20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.241] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=shameerali.kolothum.thodi@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Shameer Kolothum From: Shameer Kolothum via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752513350733116600 From: Nicolin Chen Not all fields in the SMMU IDR registers are meaningful for userspace. Only the following fields can be used: =C2=A0 - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, T= TF =C2=A0 =C2=A0 - IDR1: SIDSIZE, SSIDSIZE =C2=A0 =C2=A0 - IDR3: BBML, RIL =C2=A0 =C2=A0 - IDR5: VAX, GRAN64K, GRAN16K, GRAN4K Use the relevant fields from these to check whether the host and emulated SMMUv3 features are sufficiently aligned to enable accelerated SMMUv3 support. To retrieve this information from the host, at least one vfio-pci device must be assigned with "arm-smmuv3,accel=3Don" usage. Add a check to enforce this. Note: ATS, PASID, and PRI features are currently not supported. Only devices that do not require or make use of these features are expected to work. Also, requiring at least one vfio-pci device to be cold-plugged complicates hot-unplug and replug scenarios. For example, if all devices behind the vSMMUv3 are unplugged after the guest boots, and a new device is later hot-plugged into the same PCI bus, there is no guarantee that the underlying host SMMUv3 will expose the same feature set as the one originally used when the vSMMU was initialized. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 103 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/smmuv3-accel.h | 5 ++ hw/arm/smmuv3.c | 4 ++ hw/arm/trace-events | 2 +- 4 files changed, 113 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 1298b4f6d0..3b2f45bd88 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -23,6 +23,109 @@ #define SMMU_STE_VALID (1ULL << 0) #define SMMU_STE_CFG_BYPASS (1ULL << 3) =20 +static int +smmuv3_accel_host_hw_info(SMMUv3AccelDevice *accel_dev, uint32_t *data_typ= e, + uint32_t data_len, void *data) +{ + uint64_t caps; + + if (!accel_dev || !accel_dev->idev) { + return -ENOENT; + } + + return !iommufd_backend_get_device_info(accel_dev->idev->iommufd, + accel_dev->idev->devid, + data_type, data, + data_len, &caps, NULL); +} + +void smmuv3_accel_init_regs(SMMUv3State *s) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + SMMUv3AccelDevice *accel_dev; + uint32_t data_type; + uint32_t val; + int ret; + + if (s_accel->info.idr[0]) { + /* We already got this */ + return; + } + + if (!s_accel->viommu || QLIST_EMPTY(&s_accel->viommu->device_list)) { + error_report("For arm-smmuv3,accel=3Don case, atleast one cold-plu= gged " + "vfio-pci dev needs to be assigned"); + goto out_err; + } + + accel_dev =3D QLIST_FIRST(&s_accel->viommu->device_list); + ret =3D smmuv3_accel_host_hw_info(accel_dev, &data_type, + sizeof(s_accel->info), &s_accel->info); + if (ret) { + error_report("Failed to get Host SMMU device info"); + goto out_err; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { + error_report("Wrong data type (%d) for Host SMMU device info", + data_type); + goto out_err; + } + + trace_smmuv3_accel_host_hw_info(s_accel->info.idr[0], s_accel->info.id= r[1], + s_accel->info.idr[3], s_accel->info.id= r[5]); + /* + * QEMU SMMUv3 supports both linear and 2-level stream tables. If host + * SMMUv3 supports only linear stream table, report that to Guest. + */ + val =3D FIELD_EX32(s_accel->info.idr[0], IDR0, STLEVEL); + if (val < FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STLEVEL, val); + } + + /* + * QEMU SMMUv3 supports little-endian support for translation table wa= lks. + * If host SMMUv3 supports only big-endian, report error. + */ + val =3D FIELD_EX32(s_accel->info.idr[0], IDR0, TTENDIAN); + if (val > FIELD_EX32(s->idr[0], IDR0, TTENDIAN)) { + error_report("Host SUUMU device translation table walk endianess " + "not supported"); + goto out_err; + } + + /* + * QEMU SMMUv3 supports AArch64 Translation table format. + * If host SMMUv3 supports only AArch32, report error. + */ + val =3D FIELD_EX32(s_accel->info.idr[0], IDR0, TTF); + if (val < FIELD_EX32(s->idr[0], IDR0, TTF)) { + error_report("Host SMMU device Translation table format not suppor= ted"); + goto out_err; + } + + /* + * QEMU SMMUv3 supports 4K/16K/64K translation granules. If host SMMUv3 + * does't support any of these, report the supported ones only to Gues= t. + */ + val =3D FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN4K); + if (val < FIELD_EX32(s->idr[5], IDR5, GRAN4K)) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, val); + } + val =3D FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN16K); + if (val < FIELD_EX32(s->idr[5], IDR5, GRAN16K)) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, val); + } + val =3D FIELD_EX32(s_accel->info.idr[5], IDR5, GRAN64K); + if (val < FIELD_EX32(s->idr[5], IDR5, GRAN64K)) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, val); + } + return; + +out_err: + exit(1); +} + static void smmuv3_accel_dev_uninstall_nested_ste(SMMUv3AccelDevice *accel_dev, bool a= bort) { diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index d06c9664ba..e1e99598b4 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -49,6 +49,7 @@ typedef struct SMMUv3AccelState { MemoryRegion root; MemoryRegion sysmem; SMMUViommu *viommu; + struct iommu_hw_info_arm_smmuv3 info; } SMMUv3AccelState; =20 #if defined(CONFIG_ARM_SMMUV3) && defined(CONFIG_IOMMUFD) @@ -60,6 +61,7 @@ bool smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUComm= andBatch *batch); void smmuv3_accel_batch_cmd(SMMUState *bs, SMMUDevice *sdev, SMMUCommandBatch *batch, struct Cmd *cmd, uint32_t *cons); +void smmuv3_accel_init_regs(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *d) { @@ -83,6 +85,9 @@ static inline void smmuv3_accel_batch_cmd(SMMUState *bs, = SMMUDevice *sdev, { return; } +static inline void smmuv3_accel_init_regs(SMMUv3State *s) +{ +} #endif =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 97ecca0764..100e3c8929 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1894,6 +1894,7 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevic= e *dev) */ static void smmu_reset_exit(Object *obj, ResetType type) { + SMMUState *sys =3D ARM_SMMU(obj); SMMUv3State *s =3D ARM_SMMUV3(obj); SMMUv3Class *c =3D ARM_SMMUV3_GET_CLASS(s); =20 @@ -1903,6 +1904,9 @@ static void smmu_reset_exit(Object *obj, ResetType ty= pe) } =20 smmuv3_init_regs(s); + if (sys->accel) { + smmuv3_accel_init_regs(s); + } } =20 static void smmu_realize(DeviceState *d, Error **errp) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 7d232ca17c..37ecab10a0 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -70,7 +70,7 @@ smmu_reset_exit(void) "" smmuv3_accel_set_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (sid= =3D0x%x)" smmuv3_accel_unset_iommu_device(int devfn, uint32_t sid) "devfn=3D0x%x (si= d=3D0x%x" smmuv3_accel_install_nested_ste(uint32_t sid, uint64_t ste_1, uint64_t ste= _0) "sid=3D%d ste=3D%"PRIx64":%"PRIx64 - +smmuv3_accel_host_hw_info(uint32_t idr0, uint32_t idr1, uint32_t idr3, uin= t32_t idr5) "idr0=3D0x%x idr1=3D0x%x idr3=3D0x%x idr5=3D0x%x" # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.34.1 From nobody Sat Nov 15 10:56:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Now user can set "accel=3Don". Have fun! Signed-off-by: Shameer Kolothum Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen --- hw/arm/smmu-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 6a58f574d3..3e8783670a 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -1022,6 +1022,7 @@ static const Property smmu_dev_properties[] =3D { DEFINE_PROP_BOOL("smmu_per_bus", SMMUState, smmu_per_bus, false), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), + DEFINE_PROP_BOOL("accel", SMMUState, accel, false), }; =20 static void smmu_base_class_init(ObjectClass *klass, const void *data) --=20 2.34.1