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These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson --- target/arm/cpu-features.h | 5 ++ target/arm/cpu.h | 15 ++++++ target/arm/internals.h | 1 + target/arm/cpu.c | 3 ++ target/arm/helper.c | 88 +++++++++++++++++++++++++++++++++-- target/arm/tcg/cpu64.c | 5 +- docs/system/arm/emulation.rst | 1 + 7 files changed, 112 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428..e372543bf3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dc9b6dce4c..dda5f275fb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -337,6 +337,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1420,6 +1421,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8 /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1712,6 +1726,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index c4765e4489..fcaad39371 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -232,6 +232,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 08c43f674a..2ee895fbc4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -645,6 +645,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + env->cp15.scr_el3 |=3D SCR_SCTLR2EN; + } } =20 if (target_el =3D=3D 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c1299ff84..d0cfef1dd6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -741,6 +741,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + valid_mask |=3D SCR_SCTLR2EN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -3907,23 +3910,21 @@ static void hcrx_write(CPUARMState *env, const ARMC= PRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 - /* FEAT_MOPS adds MSCEn and MCE2 */ if (cpu_isar_feature(aa64_mops, cpu)) { valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; } - - /* FEAT_NMI adds TALLINT, VINMI and VFNMI */ if (cpu_isar_feature(aa64_nmi, cpu)) { valid_mask |=3D HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; } - /* FEAT_CMOW adds CMOW */ if (cpu_isar_feature(aa64_cmow, cpu)) { valid_mask |=3D HCRX_CMOW; } - /* FEAT_XS adds FGTnXS, FnXS */ if (cpu_isar_feature(aa64_xs, cpu)) { valid_mask |=3D HCRX_FGTNXS | HCRX_FNXS; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + valid_mask |=3D HCRX_SCTLR2EN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -4513,6 +4514,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), + "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), "CPACR", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), @@ -5994,6 +5997,77 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_el2_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult sctlr2_el1_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_SCTLR2EN= )) { + return CP_ACCESS_TRAP_EL2; + } + return sctlr2_el2_access(env, ri, isread); +} + +static void sctlr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, + .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_el2_access, + .writefn =3D sctlr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7223,6 +7297,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 35cddbafa4..f4efff03a5 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,7 +1247,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 - FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 890dc6fee2..66043b0747 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) --=20 2.43.0 From nobody Sat Nov 15 10:52:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752512925; cv=none; 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These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 2 ++ target/arm/internals.h | 19 ++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 1 + 7 files changed, 99 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e372543bf3..8ec8c3feb3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) !=3D 0; +} + static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dda5f275fb..0e247f50c7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -366,6 +366,7 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ uint64_t tcr_el[4]; + uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ @@ -1726,6 +1727,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/internals.h b/target/arm/internals.h index fcaad39371..b4cd03df69 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -201,6 +201,24 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +#define TCR2_PNCH (1ULL << 0) +#define TCR2_PIE (1ULL << 1) +#define TCR2_E0POE (1ULL << 2) +#define TCR2_POE (1ULL << 3) +#define TCR2_AIE (1ULL << 4) +#define TCR2_D128 (1ULL << 5) +#define TCR2_PTTWI (1ULL << 10) +#define TCR2_HAFT (1ULL << 11) +#define TCR2_AMEC0 (1ULL << 12) +#define TCR2_AMEC1 (1ULL << 13) +#define TCR2_DISCH0 (1ULL << 14) +#define TCR2_DISCH1 (1ULL << 15) +#define TCR2_A2 (1ULL << 16) +#define TCR2_FNG0 (1ULL << 17) +#define TCR2_FNG1 (1ULL << 18) +#define TCR2_FNGNA0 (1ULL << 20) +#define TCR2_FNGNA1 (1ULL << 21) + FIELD(VTCR, T0SZ, 0, 6) FIELD(VTCR, SL0, 6, 2) FIELD(VTCR, IRGN0, 8, 2) @@ -232,6 +250,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2ee895fbc4..e709ca74da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -645,6 +645,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + env->cp15.scr_el3 |=3D SCR_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index d0cfef1dd6..1e0e747146 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -741,6 +741,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + valid_mask |=3D SCR_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D SCR_SCTLR2EN; } @@ -3922,6 +3925,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_xs, cpu)) { valid_mask |=3D HCRX_FGTNXS | HCRX_FNXS; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + valid_mask |=3D HCRX_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } @@ -4524,6 +4530,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), + "TCR2_EL1", "TCR2_EL2", "TCR2_EL12", isar_feature_aa64_tcr2 }, { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), @@ -6068,6 +6076,62 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 +static CPAccessResult tcr2_el2_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_TCR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult tcr2_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= { + return CP_ACCESS_TRAP_EL2; + } + return tcr2_el2_access(env, ri, isread); +} + +static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo tcr2_reginfo[] =3D { + { .name =3D "TCR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, + .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, + { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D tcr2_el2_access, + .writefn =3D tcr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7301,6 +7365,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, sctlr2_reginfo); } =20 + if (cpu_isar_feature(aa64_tcr2, cpu)) { + define_arm_cp_regs(cpu, tcr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f4efff03a5..4eb51420ef 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1248,6 +1248,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 66043b0747..1c597d8673 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -149,6 +149,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage= 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage= 1) --=20 2.43.0 From nobody Sat Nov 15 10:52:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Enable access to the registers via the SCTLR2 and TCR2 control bits. Add the two new cache management instructions, which are nops in QEMU because we do not model caches. Signed-off-by: Gustavo Romero Message-ID: <20250711140828.1714666-3-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson [rth: Squash 3 patches to add all registers at once.] Signed-off-by: Richard Henderson --- target/arm/cpu-features.h | 5 ++ target/arm/cpu.h | 10 ++++ target/arm/internals.h | 3 ++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 103 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 124 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 8ec8c3feb3..9579d93cec 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -914,6 +914,11 @@ static inline bool isar_feature_aa64_sctlr2(const ARMI= SARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e247f50c7..5156120b50 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -578,6 +578,15 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -1730,6 +1739,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index b4cd03df69..6c1112e641 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -2007,4 +2007,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); bool arm_pan_enabled(CPUARMState *env); =20 +/* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 regist= er. */ +#define MECID_WIDTH 16 + #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e709ca74da..34638ea100 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -651,6 +651,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_mec, cpu)) { + env->cp15.scr_el3 |=3D SCR_MECEN; + } } =20 if (target_el =3D=3D 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e0e747146..dd7beba079 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5207,6 +5207,93 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 2) { + if (arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + + if (!(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value =3D extract64(value, 0, MECID_WIDTH); + raw_write(env, ri, value); +} + +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .access =3D PL2_R, .type =3D ARM_CP_CONST, .resetvalue =3D MECID_WID= TH - 1 }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL3_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + #ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 @@ -6045,6 +6132,9 @@ static void sctlr2_el2_write(CPUARMState *env, const = ARMCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6054,6 +6144,9 @@ static void sctlr2_el3_write(CPUARMState *env, const = ARMCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6114,6 +6207,9 @@ static void tcr2_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, { uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -7369,6 +7465,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, tcr2_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.43.0 From nobody Sat Nov 15 10:52:42 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752512319; cv=none; d=zohomail.com; s=zohoarc; b=c1Gck8h5nz7KQu6bvw/Ml01E0/KijtK+ZrraeBlkWGqwi7fKeuO7RXggNAaOhP1w9K8OHSskSVPaQLEm716uxfapa9QgX+CIT5U6Gzhgn7fWEgQ/NdZ4kqZXHrlt1xqnPH9NZv2FuK/ZfG1YGR6h1nIogjJxjhofHYlXqqJCPFI= ARC-Message-Signature: i=1; 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The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption is supported, but software stacks that rely on FEAT_MEC should work properly. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Message-ID: <20250711140828.1714666-7-gustavo.romero@linaro.org> Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 4eb51420ef..c54aa528c6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1250,6 +1250,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 1c597d8673..d207a9f266 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -89,6 +89,9 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) + + * This is a register-only implementation without encryption. - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) --=20 2.43.0