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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752492675759116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu At present, all cases using the cache model (CPUID 0x2, 0x4, 0x80000005, 0x80000006 and 0x8000001D leaves) have been verified to be able to select either cache_info_intel or cache_info_amd based on the vendor. Therefore, further merge cache_info_intel and cache_info_amd into a unified cache_info in X86CPUState, and during its initialization, set different legacy cache models based on the vendor. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-19-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 5 +- target/i386/cpu.c | 150 ++++++++-------------------------------------- 2 files changed, 27 insertions(+), 128 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 20499a82a54..f977fc49a77 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2073,11 +2073,12 @@ typedef struct CPUArchState { /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; - /* Cache information for CPUID. When legacy-cache=3Don, the cache data + /* + * Cache information for CPUID. When legacy-cache=3Don, the cache data * on each CPUID leaf will be different, because we keep compatibility * with old QEMU versions. */ - CPUCaches cache_info_cpuid4, cache_info_amd; + CPUCaches cache_info; bool enable_legacy_cpuid2_cache; bool enable_legacy_vendor_cache; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5b969743bcc..ca6e4120242 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7474,27 +7474,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } else if (env->enable_legacy_vendor_cache) { caches =3D &legacy_intel_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't use l= egacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD - * CPU will use cache_info_amd. But this doesn't matter for= AMD - * CPU, because this leaf encodes all-0 for AMD whatever it= s cache - * model is. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -7513,27 +7493,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_intel_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't use l= egacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. Non-AMD CPUs use cache_info_cpuid4 like before an= d AMD - * CPU will use cache_info_amd. But this doesn't matter for= AMD - * CPU, because this leaf encodes all-0 for AMD whatever it= s cache - * model is. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 /* cache info: needed for Core compatibility */ @@ -7942,27 +7902,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_amd_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't uses = legacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. AMD CPUs use cache_info_amd like before and non-A= MD - * CPU will use cache_info_cpuid4. But this doesn't matter, - * because for Intel CPU, it will get all-0 leaf, and Zhaox= in CPU - * will get correct cache info. Both are expected. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -7989,25 +7929,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, if (env->enable_legacy_vendor_cache) { caches =3D &legacy_amd_cache_info; } else { - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * This condition covers the following cases (with - * enable_legacy_vendor_cache=3Dfalse): - * - When CPU model has its own cache model and doesn't uses = legacy - * cache model (legacy_model=3Doff). Then cache_info_amd and - * cache_info_cpuid4 are the same. - * - * - For v10.1 and newer machines, when CPU model uses legacy= cache - * model. AMD CPUs use cache_info_amd like before and non-A= MD - * CPU (Intel & Zhaoxin) will use cache_info_cpuid4 as expe= cted. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } + caches =3D &env->cache_info; } =20 if (cpu->cache_info_passthrough) { @@ -8080,22 +8002,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; - case 0x8000001D: { - const CPUCaches *caches; - - /* - * FIXME: Temporarily select cache info model here based on - * vendor, and merge these 2 cache info models later. - * - * Intel doesn't support this leaf so that Intel Guests don't - * have this leaf. This change is harmless to Intel CPUs. - */ - if (IS_AMD_CPU(env)) { - caches =3D &env->cache_info_amd; - } else { - caches =3D &env->cache_info_cpuid4; - } - + case 0x8000001D: *eax =3D 0; if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -8103,19 +8010,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(caches->l1d_cache, + encode_cache_cpuid8000001d(env->cache_info.l1d_cache, topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(caches->l1i_cache, + encode_cache_cpuid8000001d(env->cache_info.l1i_cache, topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(caches->l2_cache, + encode_cache_cpuid8000001d(env->cache_info.l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(caches->l3_cache, + encode_cache_cpuid8000001d(env->cache_info.l3_cache, topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -8126,7 +8033,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *edx &=3D CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; } break; - } case 0x8000001E: if (cpu->core_id <=3D 255) { encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); @@ -8825,46 +8731,34 @@ static bool x86_cpu_update_smp_cache_topo(MachineSt= ate *ms, X86CPU *cpu, =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l1d_cache->share_level =3D level; - env->cache_info_amd.l1d_cache->share_level =3D level; + env->cache_info.l1d_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, - env->cache_info_cpuid4.l1d_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, - env->cache_info_amd.l1d_cache->share_level); + env->cache_info.l1d_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l1i_cache->share_level =3D level; - env->cache_info_amd.l1i_cache->share_level =3D level; + env->cache_info.l1i_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, - env->cache_info_cpuid4.l1i_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, - env->cache_info_amd.l1i_cache->share_level); + env->cache_info.l1i_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l2_cache->share_level =3D level; - env->cache_info_amd.l2_cache->share_level =3D level; + env->cache_info.l2_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, - env->cache_info_cpuid4.l2_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, - env->cache_info_amd.l2_cache->share_level); + env->cache_info.l2_cache->share_level); } =20 level =3D machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); if (level !=3D CPU_TOPOLOGY_LEVEL_DEFAULT) { - env->cache_info_cpuid4.l3_cache->share_level =3D level; - env->cache_info_amd.l3_cache->share_level =3D level; + env->cache_info.l3_cache->share_level =3D level; } else { machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, - env->cache_info_cpuid4.l3_cache->share_level); - machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, - env->cache_info_amd.l3_cache->share_level); + env->cache_info.l3_cache->share_level); } =20 if (!machine_check_smp_cache(ms, errp)) { @@ -9101,7 +8995,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) "CPU model '%s' doesn't support legacy-cache=3Doff"= , name); return; } - env->cache_info_cpuid4 =3D env->cache_info_amd =3D *cache_info; + env->cache_info =3D *cache_info; } else { /* Build legacy cache information */ if (!cpu->consistent_cache) { @@ -9111,8 +9005,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) if (!cpu->vendor_cpuid_only_v2) { env->enable_legacy_vendor_cache =3D true; } - env->cache_info_cpuid4 =3D legacy_intel_cache_info; - env->cache_info_amd =3D legacy_amd_cache_info; + + if (IS_AMD_CPU(env)) { + env->cache_info =3D legacy_amd_cache_info; + } else { + env->cache_info =3D legacy_intel_cache_info; + } } =20 #ifndef CONFIG_USER_ONLY --=20 2.50.0