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Mon, 14 Jul 2025 04:06:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXYOQcsuR9pPrQE0ZA1C9s7bm6CtiFo3XQuydkWlqEZQP2WRamsUR4Wnd51C1cqQ72QtRpWA== X-Received: by 2002:a5d:5f55:0:b0:3a4:dcfb:3118 with SMTP id ffacd0b85a97d-3b5f187599dmr10358488f8f.10.1752491187658; Mon, 14 Jul 2025 04:06:27 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , EwanHai , Yi Lai Subject: [PULL 54/77] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005 Date: Mon, 14 Jul 2025 13:03:43 +0200 Message-ID: <20250714110406.117772-55-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752493008018116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x80000005 leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model like before, otherwise, select legacy Intel cache model (in cache_info_cpuid4). To ensure compatibility is not broken, add an enable_legacy_vendor_cache flag based on x-vendor-only-v2 to indicate cases where the legacy cache model should be used regardless of the vendor. For CPUID 0x80000005 leaf, enable_legacy_vendor_cache flag indicates to pick legacy AMD cache model, which is for compatibility with the behavior of PC machine v10.0 and older. The following explains how current vendor-based default legacy cache model ensures correctness without breaking compatibility. * For the PC machine v6.0 and older, vendor_cpuid_only=3Dfalse, and vendor_cpuid_only_v2=3Dfalse. - If the named CPU model has its own cache model, and doesn't use legacy cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 and cache_info_amd are same, so 0x80000005 leaf uses its own cache model regardless of the vendor. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is true, they will use legacy AMD cache model just like their previous behavior. * For the PC machine v10.0 and older (to v6.1), vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dfalse. - No change, since this leaf doesn't aware vendor_cpuid_only. * For the PC machine v10.1 and newer, vendor_cpuid_only=3Dtrue, and vendor_cpuid_only_v2=3Dtrue. - If the named CPU model has its own cache model (legacy_cache=3Dfalse), then cache_info_cpuid4 & cache_info_amd both equal to its own cache model, so it uses its own cache model in 0x80000005 leaf regardless of the vendor. Only Intel CPUs have all-0 leaf due to vendor_cpuid_only_2=3Dtrue, and this is exactly the expected behavior. - For max/host/named CPU (without its own cache model), then the flag enable_legacy_vendor_cache is false, the legacy cache model is selected based on vendor. For AMD CPU, it will use legacy AMD cache as expected. For Intel CPU, it will use legacy Intel cache but still get all-0 leaf due to vendor_cpuid_only_2=3Dtrue as expected. (Note) And for Zhaoxin CPU, it will use legacy Intel cache model instead of AMD's. This is the difference brought by this change! But it's correct since then Zhaoxin could have the consistent cache info in CPUID 0x2, 0x4 and 0x80000005 leaves. Here, except Zhaoxin, selecting the legacy cache model based on the vendor does not change the previous (before the change) behavior. And the change for Zhaoxin is also a good improvement. Therefore, the above analysis proves that, with the help of the flag enable_legacy_vendor_cache, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x80000005 leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Cc: EwanHai Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-16-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 565eaf0071c..e98ffb11c31 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7935,8 +7935,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx =3D env->cpuid_model[(index - 0x80000002) * 4 + 2]; *edx =3D env->cpuid_model[(index - 0x80000002) * 4 + 3]; break; - case 0x80000005: + case 0x80000005: { /* cache info (L1 cache/TLB Associativity Field) */ + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches =3D &legacy_amd_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=3Dfalse): + * - When CPU model has its own cache model and doesn't uses = legacy + * cache model (legacy_model=3Doff). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy= cache + * model. AMD CPUs use cache_info_amd like before and non-A= MD + * CPU will use cache_info_cpuid4. But this doesn't matter, + * because for Intel CPU, it will get all-0 leaf, and Zhaox= in CPU + * will get correct cache info. Both are expected. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -7951,9 +7979,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); - *ecx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); - *edx =3D encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); + *ecx =3D encode_cache_cpuid80000005(caches->l1d_cache); + *edx =3D encode_cache_cpuid80000005(caches->l1i_cache); break; + } case 0x80000006: /* cache info (L2 cache/TLB/L3 cache) */ if (cpu->cache_info_passthrough) { --=20 2.50.0