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Mon, 14 Jul 2025 04:06:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE3ufuEwfxJQ0v8ZKiVpw7HEJ9R+h/x+rD/MLQaVKNrkJpRbm35nGRWyOLs3VBb/xOiWR351Q== X-Received: by 2002:a5d:5d85:0:b0:3b5:f6f9:e803 with SMTP id ffacd0b85a97d-3b5f6f9e812mr8051359f8f.14.1752491180557; Mon, 14 Jul 2025 04:06:20 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Dapeng Mi , Yi Lai Subject: [PULL 51/77] i386/cpu: Add legacy_amd_cache_info cache model Date: Mon, 14 Jul 2025 13:03:40 +0200 Message-ID: <20250714110406.117772-52-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752493481152116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Based on legacy_l1d_cachei_amd, legacy_l1i_cache_amd, legacy_l2_cache_amd and legacy_l3_cache, build a complete legacy AMD cache model, which can clarify the purpose of these trivial legacy cache models, simplify the initialization of cache info in X86CPUState, and make it easier to handle compatibility later. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-13-zhao1.liu@intel.c= om Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 112 ++++++++++++++++++++++------------------------ 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d265dc81563..92d21ce64c3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -640,60 +640,58 @@ static void encode_topo_cpuid8000001e(X86CPU *cpu, X8= 6CPUTopoInfo *topo_info, * These are legacy cache values. If there is a need to change any * of these values please use builtin_x86_defs */ -static CPUCacheInfo legacy_l1d_cache_amd =3D { - .type =3D DATA_CACHE, - .level =3D 1, - .size =3D 64 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 2, - .sets =3D 512, - .partitions =3D 1, - .lines_per_tag =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -static CPUCacheInfo legacy_l1i_cache_amd =3D { - .type =3D INSTRUCTION_CACHE, - .level =3D 1, - .size =3D 64 * KiB, - .self_init =3D 1, - .line_size =3D 64, - .associativity =3D 2, - .sets =3D 512, - .partitions =3D 1, - .lines_per_tag =3D 1, - .no_invd_sharing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -static CPUCacheInfo legacy_l2_cache_amd =3D { - .type =3D UNIFIED_CACHE, - .level =3D 2, - .size =3D 512 * KiB, - .line_size =3D 64, - .lines_per_tag =3D 1, - .associativity =3D 16, - .sets =3D 512, - .partitions =3D 1, - .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, -}; - -/* Level 3 unified cache: */ -static CPUCacheInfo legacy_l3_cache =3D { - .type =3D UNIFIED_CACHE, - .level =3D 3, - .size =3D 16 * MiB, - .line_size =3D 64, - .associativity =3D 16, - .sets =3D 16384, - .partitions =3D 1, - .lines_per_tag =3D 1, - .self_init =3D true, - .inclusive =3D true, - .complex_indexing =3D true, - .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, +static const CPUCaches legacy_amd_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 2, + .sets =3D 512, + .partitions =3D 1, + .lines_per_tag =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .self_init =3D 1, + .line_size =3D 64, + .associativity =3D 2, + .sets =3D 512, + .partitions =3D 1, + .lines_per_tag =3D 1, + .no_invd_sharing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .lines_per_tag =3D 1, + .associativity =3D 16, + .sets =3D 512, + .partitions =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .sets =3D 16384, + .partitions =3D 1, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .complex_indexing =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, }; =20 /* @@ -8991,11 +8989,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 env->cache_info_cpuid4 =3D legacy_intel_cache_info; - - env->cache_info_amd.l1d_cache =3D &legacy_l1d_cache_amd; - env->cache_info_amd.l1i_cache =3D &legacy_l1i_cache_amd; - env->cache_info_amd.l2_cache =3D &legacy_l2_cache_amd; - env->cache_info_amd.l3_cache =3D &legacy_l3_cache; + env->cache_info_amd =3D legacy_amd_cache_info; } =20 #ifndef CONFIG_USER_ONLY --=20 2.50.0