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Mon, 14 Jul 2025 04:06:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzZwsANSptTigDo6JPnjSG8BVa/qdPOxY9LPt6ZVFYEMHq48AF5379W2T4eUTYtBB3gPqnkQ== X-Received: by 2002:a05:600c:1da7:b0:456:1b8b:b8c6 with SMTP id 5b1f17b1804b1-4561b8bbbf3mr27416765e9.14.1752491171311; Mon, 14 Jul 2025 04:06:11 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Yi Lai Subject: [PULL 47/77] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Date: Mon, 14 Jul 2025 13:03:36 +0200 Message-ID: <20250714110406.117772-48-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752493406084116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Per SDM, 0x80000005 leaf is reserved for Intel CPU, and its current "assert" check blocks adding new cache model for non-AMD CPUs. And please note, although Zhaoxin mostly follows Intel behavior, this leaf is an exception [1]. So, with the compat property "x-vendor-cpuid-only-v2", for the machine since v10.1, check the vendor and encode this leaf as all-0 only for Intel CPU. In addition, drop lines_per_tag assertion in encode_cache_cpuid80000005(), since Zhaoxin will use legacy Intel cache model in this leaf - which doesn't have this field. This fix also resolves 2 FIXMEs of legacy_l1d_cache_amd and legacy_l1i_cache_amd: /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ In addition, per AMD's APM, update the comment of CPUID[0x80000005]. [1]: https://lore.kernel.org/qemu-devel/fa16f7a8-4917-4731-9d9f-7d4c1097716= 8@zhaoxin.com/ Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-9-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 630a40d72be..2abcb5acffc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -499,7 +499,6 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint3= 2_t count, static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) { assert(cache->size % 1024 =3D=3D 0); - assert(cache->lines_per_tag > 0); assert(cache->associativity > 0); assert(cache->line_size > 0); return ((cache->size / 1024) << 24) | (cache->associativity << 16) | @@ -657,7 +656,6 @@ static CPUCacheInfo legacy_l1d_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l1d_cache_amd =3D { .type =3D DATA_CACHE, .level =3D 1, @@ -686,7 +684,6 @@ static CPUCacheInfo legacy_l1i_cache =3D { .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, }; =20 -/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ static CPUCacheInfo legacy_l1i_cache_amd =3D { .type =3D INSTRUCTION_CACHE, .level =3D 1, @@ -7884,11 +7881,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *edx =3D env->cpuid_model[(index - 0x80000002) * 4 + 3]; break; case 0x80000005: - /* cache info (L1 cache) */ + /* cache info (L1 cache/TLB Associativity Field) */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; } + + if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + *eax =3D (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); *ebx =3D (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | @@ -9478,6 +9481,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, tru= e), + DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v= 2, true), DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_fe= atures_only, true), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), --=20 2.50.0