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Mon, 14 Jul 2025 04:06:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEyfT5lVSL5La+qRe6r0wBd2hXC09EXivpjtDrdt0XxI0V3wtxzODpSi4/VDmYyCO3qds9YzA== X-Received: by 2002:a05:600c:1c83:b0:43e:bdf7:7975 with SMTP id 5b1f17b1804b1-455e7135bbdmr86658095e9.32.1752491163746; Mon, 14 Jul 2025 04:06:03 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Dapeng Mi , Yi Lai Subject: [PULL 44/77] i386/cpu: Consolidate CPUID 0x4 leaf Date: Mon, 14 Jul 2025 13:03:33 +0200 Message-ID: <20250714110406.117772-45-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752492772841116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Modern Intel CPUs use CPUID 0x4 leaf to describe cache information and leave space in 0x2 for prefetch and TLBs (even TLB has its own leaf CPUID 0x18). And 0x2 leaf provides a descriptor 0xFF to instruct software to check cache information in 0x4 leaf instead. Therefore, follow this behavior to encode 0xFF when Intel CPU has 0x4 leaf with "x-consistent-cache=3Dtrue" for compatibility. In addition, for older CPUs without 0x4 leaf, still enumerate the cache descriptor in 0x2 leaf, except the case that there's no descriptor matching the cache model, then directly encode 0xFF in 0x2 leaf. This makes sense, as in the 0x2 leaf era, all supported caches should have the corresponding descriptor. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-6-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 48 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1f27fcf3ee0..812e85b952f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -225,7 +225,7 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descripto= rs[] =3D { * Return a CPUID 2 cache descriptor for a given cache. * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE */ -static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) +static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache, bool *unmacthe= d) { int i; =20 @@ -242,9 +242,44 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *c= ache) } } =20 + *unmacthed |=3D true; return CACHE_DESCRIPTOR_UNAVAILABLE; } =20 +/* Encode cache info for CPUID[2] */ +static void encode_cache_cpuid2(X86CPU *cpu, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) +{ + CPUX86State *env =3D &cpu->env; + CPUCaches *caches =3D &env->cache_info_cpuid2; + int l1d, l1i, l2, l3; + bool unmatched =3D false; + + *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ + *ebx =3D *ecx =3D *edx =3D 0; + + l1d =3D cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); + l1i =3D cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); + l2 =3D cpuid2_cache_descriptor(caches->l2_cache, &unmatched); + l3 =3D cpuid2_cache_descriptor(caches->l3_cache, &unmatched); + + if (!cpu->consistent_cache || + (env->cpuid_min_level < 0x4 && !unmatched)) { + /* + * Though SDM defines code 0x40 for cases with no L2 or L3. It's + * also valid to just ignore l3's code if there's no l2. + */ + if (cpu->enable_l3_cache) { + *ecx =3D l3; + } + *edx =3D (l1d << 16) | (l1i << 8) | l2; + } else { + *ecx =3D 0; + *edx =3D CACHE_DESCRIPTOR_UNAVAILABLE; + } +} + /* CPUID Leaf 4 constants: */ =20 /* EAX: */ @@ -7446,16 +7481,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } - *eax =3D 1; /* Number of CPUID[EAX=3D2] calls required */ - *ebx =3D 0; - if (!cpu->enable_l3_cache) { - *ecx =3D 0; - } else { - *ecx =3D cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cac= he); - } - *edx =3D (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache= ) << 16) | - (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) = << 8) | - (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); + encode_cache_cpuid2(cpu, eax, ebx, ecx, edx); break; case 4: /* cache info: needed for Core compatibility */ --=20 2.50.0