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Mon, 14 Jul 2025 04:05:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEng2ALQiQcclffqdjxyYchlIAMr7NEzhnsIKAkQtPbbwVT/TCRO0GPJXkTYXNigqqSY1yA+Q== X-Received: by 2002:a05:600c:3481:b0:456:1442:86e with SMTP id 5b1f17b1804b1-45614420b46mr36807935e9.21.1752491156284; Mon, 14 Jul 2025 04:05:56 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Dapeng Mi , Yi Lai Subject: [PULL 41/77] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding Date: Mon, 14 Jul 2025 13:03:30 +0200 Message-ID: <20250714110406.117772-42-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752491974078116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The legacy_l2_cache (2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size) corresponds to descriptor 0x49, but at present cpuid2_cache_descriptors doesn't support descriptor 0x49 because it has multiple meanings. The 0x49 is necessary when CPUID 0x2 and 0x4 leaves have the consistent cache model, and use legacy_l2_cache as the default L2 cache. Therefore, add descriptor 0x49 to represent general L2 cache. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f107e586734..4386b60ff6c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -129,7 +129,18 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descript= ors[] =3D { .associativity =3D 8, .line_size =3D 64, }, [0x48] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 3 = * MiB, .associativity =3D 12, .line_size =3D 64, }, - /* Descriptor 0x49 depends on CPU family/model, so it is not included = */ + /* + * Descriptor 0x49 has 2 cases: + * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line s= ize. + * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size + * (Intel Xeon processor MP, Family 0FH, Model 06H). + * + * When it represents L3, then it depends on CPU family/model. Fortuna= tely, + * the legacy cache/CPU models don't have such special L3. So, just ad= d it + * to represent the general L2 case. + */ + [0x49] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 4 = * MiB, + .associativity =3D 16, .line_size =3D 64, }, [0x4A] =3D { .level =3D 3, .type =3D UNIFIED_CACHE, .size =3D 6 = * MiB, .associativity =3D 12, .line_size =3D 64, }, [0x4B] =3D { .level =3D 3, .type =3D UNIFIED_CACHE, .size =3D 8 = * MiB, --=20 2.50.0