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Mon, 14 Jul 2025 04:05:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGxZCI6whCGuhwZJQbFjNVK4kWfAqulRs1wLCzTC1CnQkSpF9Konh5oajRVqAwnAib+rOso6g== X-Received: by 2002:a05:6000:4012:b0:3a4:c8c1:aed8 with SMTP id ffacd0b85a97d-3b5f2e229a9mr8767475f8f.39.1752491154358; Mon, 14 Jul 2025 04:05:54 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Zhao Liu , Dapeng Mi , Yi Lai Subject: [PULL 40/77] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Date: Mon, 14 Jul 2025 13:03:29 +0200 Message-ID: <20250714110406.117772-41-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250714110406.117772-1-pbonzini@redhat.com> References: <20250714110406.117772-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752491797944116600 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Refer to SDM vol.3 table 1-21, add the notes about the missing descriptor, and fix the typo and comment format. Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu Link: https://lore.kernel.org/r/20250711102143.1622339-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f9e6bc8d0e6..f107e586734 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -68,6 +68,7 @@ struct CPUID2CacheDescriptorInfo { =20 /* * Known CPUID 2 cache descriptors. + * TLB, prefetch and sectored cache related descriptors are not included. * From Intel SDM Volume 2A, CPUID instruction */ struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] =3D { @@ -89,18 +90,29 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descripto= rs[] =3D { .associativity =3D 2, .line_size =3D 64, }, [0x21] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, .associativity =3D 8, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x22, 0x23 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x22, 0x23 are not included + */ [0x24] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 16, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x25, 0x20 are not included - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x25, 0x29 are not included + */ [0x2C] =3D { .level =3D 1, .type =3D DATA_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, [0x30] =3D { .level =3D 1, .type =3D INSTRUCTION_CACHE, .size =3D 32 = * KiB, .associativity =3D 8, .line_size =3D 64, }, + /* + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid + * to just ignore L3's code if there's no L3. + * + * This already covers all the cases in QEMU, so code 0x40 is not + * included. + */ [0x41] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 128 = * KiB, .associativity =3D 4, .line_size =3D 32, }, [0x42] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 256 = * KiB, @@ -138,9 +150,10 @@ struct CPUID2CacheDescriptorInfo cpuid2_cache_descript= ors[] =3D { .associativity =3D 4, .line_size =3D 64, }, [0x78] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 1 = * MiB, .associativity =3D 4, .line_size =3D 64, }, - /* lines per sector is not supported cpuid2_cache_descriptor(), - * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. - */ + /* + * lines per sector is not supported cpuid2_cache_descriptor(), + * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. + */ [0x7D] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 2 = * MiB, .associativity =3D 8, .line_size =3D 64, }, [0x7F] =3D { .level =3D 2, .type =3D UNIFIED_CACHE, .size =3D 512 = * KiB, --=20 2.50.0