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Mon, 14 Jul 2025 03:47:43 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2025 00:47:36 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 14 Jul 2025 00:47:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752479260; x=1784015260; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rAK1cNES//VTulXNgnL3pRWZtHvlKpyYfxsqm/cm01E=; b=KyYgqkl7IhUA2DK0p2/a6AiQ/2HBw3cfOJja0GOZzukkB8jYi+l+H+Nc RW7V28ANRdp7jzW/dhCZKpmbth1nKS+1F1Iwn8z+NOzFK7gkXUBQs+abF +e3qwqf0ry6ztV+LSpNfsYLDjMWumgt6XuQBFBQzSo7egF+t+lkUxP6Kg j/Comhv61/OS3WrKTz3NRNTeQfuaF2cfI95ufvl0Qx2loBkD4IrpTLTeL cVFjov8BlndFc11ivF+LWKA+f71ZtWVpdwMYgLoaOTGgT2gnYdB4iX/IH FkfGTPtgOmbThKzynSA08VRlhfI95GGjxKa4Fph0Va921JK/YoySIXm62 w==; X-CSE-ConnectionGUID: btqI5TFzQRCaMVjEy4XlYQ== X-CSE-MsgGUID: lHHaq7/LQdiXsLLGCIyeEA== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="58324645" X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="58324645" X-CSE-ConnectionGUID: e50Lk58dQFOxAl+J24uy5Q== X-CSE-MsgGUID: HMSFVuL6QoCea0EqMfWzew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="156952190" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Tao Su Subject: [PATCH v2 1/7] i386/cpu: Mark EBX/ECX/EDX in CPUID 0x80000000 leaf as reserved for Intel Date: Mon, 14 Jul 2025 16:08:53 +0800 Message-Id: <20250714080859.1960104-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480590266116600 Content-Type: text/plain; charset="utf-8" Per SDM, 80000000H EAX Maximum Input Value for Extended Function CPUID Information. EBX Reserved. ECX Reserved. EDX Reserved. EBX/ECX/EDX in CPUID 0x80000000 leaf are reserved. Intel and Zhaoxin are already using 0x0 leaf to encode vendor. Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- Changes Since v1: * Consider Zhaoxin CPU. (Ewan) --- target/i386/cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8d67cadec2f2..37e4bf51d890 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8278,9 +8278,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, break; case 0x80000000: *eax =3D env->cpuid_xlevel; - *ebx =3D env->cpuid_vendor1; - *edx =3D env->cpuid_vendor2; - *ecx =3D env->cpuid_vendor3; + + if (cpu->vendor_cpuid_only_v2 && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *ebx =3D *ecx =3D *edx =3D 0; + } else { + *ebx =3D env->cpuid_vendor1; + *edx =3D env->cpuid_vendor2; + *ecx =3D env->cpuid_vendor3; + } break; case 0x80000001: *eax =3D env->cpuid_version; --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="156952193" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Tao Su Subject: [PATCH v2 2/7] i386/cpu: Mark CPUID 0x80000008 ECX bits[0:7] & [12:15] as reserved for Intel/Zhaoxin Date: Mon, 14 Jul 2025 16:08:54 +0800 Message-Id: <20250714080859.1960104-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480701523116600 Content-Type: text/plain; charset="utf-8" Per SDM, 80000008H EAX Linear/Physical Address size. Bits 07-00: #Physical Address Bits*. Bits 15-08: #Linear Address Bits. Bits 31-16: Reserved =3D 0. EBX Bits 08-00: Reserved =3D 0. Bit 09: WBNOINVD is available if 1. Bits 31-10: Reserved =3D 0. ECX Reserved =3D 0. EDX Reserved =3D 0. ECX/EDX in CPUID 0x80000008 leaf are reserved. Currently, in QEMU, only ECX bits[0:7] and ECX bits[12:15] are encoded, and both are emulated in QEMU. Considering that Intel and Zhaoxin are already using the 0x1f leaf to describe CPU topology, which includes similar information, Intel and Zhaoxin will not implement ECX bits[0:7] and bits[12:15] of 0x80000008. Therefore, mark these two fields as reserved and clear them for Intel and Zhaoxin guests. Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * Consider Zhaoxin (Ewan). * Only clear ECX bits[0:7] and bits[12:15] for Intel/Zhaoxin, and do not cover other bits. --- target/i386/cpu.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 37e4bf51d890..abd529d587ba 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8387,15 +8387,25 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *eax |=3D (cpu->guest_phys_bits << 16); } *ebx =3D env->features[FEAT_8000_0008_EBX]; + if (threads_per_pkg > 1) { /* - * Bits 15:12 is "The number of bits in the initial - * Core::X86::Apic::ApicId[ApicId] value that indicate - * thread ID within a package". - * Bits 7:0 is "The number of threads in the package is NC+1" + * Don't emulate Bits [7:0] & Bits [15:12] for Intel/Zhaoxin, = since + * they're using 0x1f leaf. */ - *ecx =3D (apicid_pkg_offset(topo_info) << 12) | - (threads_per_pkg - 1); + if (cpu->vendor_cpuid_only_v2 && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *ecx =3D 0; + } else { + /* + * Bits 15:12 is "The number of bits in the initial + * Core::X86::Apic::ApicId[ApicId] value that indicate + * thread ID within a package". + * Bits 7:0 is "The number of threads in the package is NC= +1" + */ + *ecx =3D (apicid_pkg_offset(topo_info) << 12) | + (threads_per_pkg - 1); + } } else { *ecx =3D 0; } --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752480531; cv=none; d=zohomail.com; s=zohoarc; b=IQ1rdbIBnfN4mKfgQtD/SetVfg5KKxrOQ6psWGIFrkbdClMnDSlDr6wuLxH52Hs6xvvdZAc6GjD3A7vhX/j5EFeroRj0ISl1UkyBUSxPfDlNwdq87fA1nFI6WfKvxKJw49lbxD+NsehVaqMPPm6G21I/1guQ4oG4pS2d9+gDGJQ= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480533729116600 Content-Type: text/plain; charset="utf-8" Sort the CPUID leaves strictly by index to facilitate checking and changing. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 60 +++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index abd529d587ba..9e110e49ab8a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8050,21 +8050,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, assert(!(*eax & ~0x1f)); *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ break; - case 0x1C: - if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { - x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); - *edx =3D 0; - } - break; - case 0x1F: - /* V2 Extended Topology Enumeration Leaf */ - if (!x86_has_cpuid_0x1f(cpu)) { - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - break; - } - - encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); - break; case 0xD: { /* Processor Extended State */ *eax =3D 0; @@ -8205,6 +8190,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1C: + if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_ED= X_ARCH_LBR)) { + x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); + *edx =3D 0; + } + break; case 0x1D: { /* AMX TILE, for now hardcoded for Sapphire Rapids*/ *eax =3D 0; @@ -8242,6 +8233,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1F: + /* V2 Extended Topology Enumeration Leaf */ + if (!x86_has_cpuid_0x1f(cpu)) { + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + break; + } + + encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); + break; case 0x24: { *eax =3D 0; *ebx =3D 0; @@ -8465,6 +8465,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; + case 0x8000001F: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + if (sev_enabled()) { + *eax =3D 0x2; + *eax |=3D sev_es_enabled() ? 0x8 : 0; + *eax |=3D sev_snp_enabled() ? 0x10 : 0; + *ebx =3D sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ + *ebx |=3D (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11= :6] */ + } + break; + case 0x80000021: + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; + *eax =3D env->features[FEAT_8000_0021_EAX]; + *ebx =3D env->features[FEAT_8000_0021_EBX]; + break; case 0x80000022: *eax =3D *ebx =3D *ecx =3D *edx =3D 0; /* AMD Extended Performance Monitoring and Debug */ @@ -8497,21 +8512,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ecx =3D 0; *edx =3D 0; break; - case 0x8000001F: - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - if (sev_enabled()) { - *eax =3D 0x2; - *eax |=3D sev_es_enabled() ? 0x8 : 0; - *eax |=3D sev_snp_enabled() ? 0x10 : 0; - *ebx =3D sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ - *ebx |=3D (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11= :6] */ - } - break; - case 0x80000021: - *eax =3D *ebx =3D *ecx =3D *edx =3D 0; - *eax =3D env->features[FEAT_8000_0021_EAX]; - *ebx =3D env->features[FEAT_8000_0021_EBX]; - break; default: /* reserved values: zero */ *eax =3D 0; --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Jul 2025 03:47:51 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2025 00:47:46 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 14 Jul 2025 00:47:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752479268; x=1784015268; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=46Zv6ouztE1Lvhxo7s0FPuq1ew+8otHrJ05oqC+ySy8=; b=fAGVCLVj3DN47MHnHw2m0WauYS2z+Gq38UMzNC9Qi9okuf1S1InVr/BZ GSKa3040djYpq63NV/vnyId90wklkkI0s8jyU5xIRf0YLQt/EwdF7T90U P/5PTXch8iEdMRjuTXt2KPQQQ39hbyjNM7EX55Wn1fq9htobrChcDDIOD zl3/Banw2hYRzNRQUJXfOOBDJWSIGZYKbA8fy9k0qTcQupIiR1kWhw14F BWvHTlOdfafpvQMjzMuWPlpT1CITfxs+2OP0WA0xNL1RuUSl7FMtv0dRP EIhaSrNz4RyW0VgDhZZBiosK4gfXTV9v6agQwTCAMPcxAO/XpSMCbefCV A==; X-CSE-ConnectionGUID: 8cy2KsvVTWiLXcI4Law19A== X-CSE-MsgGUID: 1nsimMk0SuqNOL35fzjSGw== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="58324672" X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="58324672" X-CSE-ConnectionGUID: yvuy8wuYSgWQ6CpMM8BvPg== X-CSE-MsgGUID: n1oU+dSgSNqq5Rxgi0GvtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="156952213" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Chuang Xu , Guixiong Wei , Yipeng Yin Subject: [PATCH v2 4/7] i386/cpu: Fix number of addressable IDs field for CPUID.01H.EBX[23:16] Date: Mon, 14 Jul 2025 16:08:56 +0800 Message-Id: <20250714080859.1960104-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480701561116600 Content-Type: text/plain; charset="utf-8" From: Chuang Xu When QEMU is started with: -cpu host,migratable=3Don,host-cache-info=3Don,l3-cache=3Doff -smp 180,sockets=3D2,dies=3D1,cores=3D45,threads=3D2 On Intel platform: CPUID.01H.EBX[23:16] is defined as "max number of addressable IDs for logical processors in the physical package". When executing "cpuid -1 -l 1 -r" in the guest, we obtain a value of 90 for CPUID.01H.EBX[23:16], whereas the expected value is 128. Additionally, executing "cpuid -1 -l 4 -r" in the guest yields a value of 63 for CPUID.04H.EAX[31:26], which matches the expected result. As (1+CPUID.04H.EAX[31:26]) rounds up to the nearest power-of-2 integer, it's necessary to round up CPUID.01H.EBX[23:16] to the nearest power-of-2 integer too. Otherwise there would be unexpected results in guest with older kernel. For example, when QEMU is started with CLI above and xtopology is disabled, guest kernel 5.15.120 uses CPUID.01H.EBX[23:16]/(1+CPUID.04H.EAX[31:26]) to calculate threads-per-core in detect_ht(). Then guest will get "90/(1+63)= =3D1" as the result, even though threads-per-core should actually be 2. And on AMD platform: CPUID.01H.EBX[23:16] is defined as "Logical processor count". Current result meets our expectation. So round up CPUID.01H.EBX[23:16] to the nearest power-of-2 integer only for Intel platform to solve the unexpected result. Use the "x-vendor-cpuid-only-v2" compat option to fix this issue. Reviewed-by: Zhao Liu Signed-off-by: Guixiong Wei Signed-off-by: Yipeng Yin Signed-off-by: Chuang Xu Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- Changes Since New v1 [**]: * Drop Igor's Acked-by since this version uses the newly added x-vendor-cpuid-only-v2. * Add Zhaoxin since this is the behavior defined in SDM. Changes Since original v6 [*] : * Rebase on the b69801dd6b1e ("Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging"). * Polish the comment in code. * Explain the change doesn't need extra compat property. [*] original v6: https://lore.kernel.org/qemu-devel/20241009035638.59330-1-= xuchuangxclwt@bytedance.com/ [**] new v1: https://lore.kernel.org/qemu-devel/20250227062523.124601-2-zha= o1.liu@intel.com/ --- target/i386/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9e110e49ab8a..7fcb6c144d94 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7869,7 +7869,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } *edx =3D env->features[FEAT_1_EDX]; if (threads_per_pkg > 1) { - *ebx |=3D threads_per_pkg << 16; + /* + * For CPUID.01H.EBX[Bits 23-16], AMD requires logical process= or + * count, but Intel needs maximum number of addressable IDs for + * logical processors per package. + */ + if (cpu->vendor_cpuid_only_v2 && + (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { + *ebx |=3D 1 << apicid_pkg_offset(topo_info) << 16; + } else { + *ebx |=3D threads_per_pkg << 16; + } } break; case 2: { /* cache info: needed for Pentium Pro compatibility */ --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="156952218" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Qian Wen , qemu-stable@nongnu.org Subject: [PATCH v2 5/7] i386/cpu: Fix cpu number overflow in CPUID.01H.EBX[23:16] Date: Mon, 14 Jul 2025 16:08:57 +0800 Message-Id: <20250714080859.1960104-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480734126116600 Content-Type: text/plain; charset="utf-8" From: Qian Wen The legacy topology enumerated by CPUID.1.EBX[23:16] is defined in SDM Vol2: Bits 23-16: Maximum number of addressable IDs for logical processors in this physical package. When threads_per_socket > 255, it will 1) overwrite bits[31:24] which is apic_id, 2) bits [23:16] get truncated. Specifically, if launching the VM with -smp 256, the value written to EBX[23:16] is 0 because of data overflow. If the guest only supports legacy topology, without V2 Extended Topology enumerated by CPUID.0x1f or Extended Topology enumerated by CPUID.0x0b to support over 255 CPUs, the return of the kernel invoking cpu_smt_allowed() is false and APs (application processors) will fail to bring up. Then only CPU 0 is online, and others are offline. For example, launch VM via: qemu-system-x86_64 -M q35,accel=3Dkvm,kernel-irqchip=3Dsplit \ -cpu qemu64,cpuid-0xb=3Doff -smp 256 -m 32G \ -drive file=3Dguest.img,if=3Dnone,id=3Dvirtio-disk0,format=3Draw \ -device virtio-blk-pci,drive=3Dvirtio-disk0,bootindex=3D1 --nographic The guest shows: CPU(s): 256 On-line CPU(s) list: 0 Off-line CPU(s) list: 1-255 To avoid this issue caused by overflow, limit the max value written to EBX[23:16] to 255 as the HW does. Cc: qemu-stable@nongnu.org Reviewed-by: Xiaoyao Li Signed-off-by: Qian Wen Signed-off-by: Zhao Liu --- Changes Since New v1 [**]: * Rebase. Changes Since Original v4 [*]: * Rebase on addressable ID fixup. * Drop R/b tags since the code base changes. [*] original v4: https://lore.kernel.org/qemu-devel/20230829042405.932523-2= -qian.wen@intel.com/ [**]: new v1: https://lore.kernel.org/qemu-devel/20250227062523.124601-3-zh= ao1.liu@intel.com/ --- target/i386/cpu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7fcb6c144d94..67a371e23b22 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7869,6 +7869,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } *edx =3D env->features[FEAT_1_EDX]; if (threads_per_pkg > 1) { + uint32_t num; + /* * For CPUID.01H.EBX[Bits 23-16], AMD requires logical process= or * count, but Intel needs maximum number of addressable IDs for @@ -7876,10 +7878,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, */ if (cpu->vendor_cpuid_only_v2 && (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { - *ebx |=3D 1 << apicid_pkg_offset(topo_info) << 16; + num =3D 1 << apicid_pkg_offset(topo_info); } else { - *ebx |=3D threads_per_pkg << 16; + num =3D threads_per_pkg; } + + /* Fixup overflow: max value for bits 23-16 is 255. */ + *ebx |=3D MIN(num, 255) << 16; } break; case 2: { /* cache info: needed for Pentium Pro compatibility */ --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752480783; cv=none; d=zohomail.com; s=zohoarc; b=bSkqgvLwpJztFLzbB0bOnrt40Ot9EihCaXXWIhao4jl/noulFF9KaY3/jcDegWKqTJmdkkofSG6yLF8vyZ9v9gc20gTkKH1NOZcrj6QDzrQ/5eYW+Z4Ode5wYXGaYs+KES+f8M9qQPjeCRMzNdOSPiG8aIe+D2gdeCJ8P7x1dnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752480783; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: HfHqeAq5RKijs7IpMqGNHQ== X-CSE-MsgGUID: 6qfClBuLRTalEN2ABCQLmQ== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="58324682" X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="58324682" X-CSE-ConnectionGUID: KK0kA3mBTRmvxSXc9gwxSw== X-CSE-MsgGUID: OM6wARDFQTi/hWtqCiNzpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="156952225" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Qian Wen Subject: [PATCH v2 6/7] i386/cpu: Fix overflow of cache topology fields in CPUID.04H Date: Mon, 14 Jul 2025 16:08:58 +0800 Message-Id: <20250714080859.1960104-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480784825116600 Content-Type: text/plain; charset="utf-8" From: Qian Wen According to SDM, CPUID.0x4:EAX[31:26] indicates the Maximum number of addressable IDs for processor cores in the physical package. If we launch over 64 cores VM, the 6-bit field will overflow, and the wrong core_id number will be reported. Since the HW reports 0x3f when the intel processor has over 64 cores, limit the max value written to EAX[31:26] to 63, so max num_cores should be 64. For EAX[14:25], though at present Q35 supports up to 4096 CPUs, by constructing a specific topology, the width of the APIC ID can be extended beyond 12 bits. For example, using `-smp threads=3D33,cores=3D9, modules=3D9` results in a die level offset of 6 + 4 + 4 =3D 14 bits, which can also cause overflow. check and honor the maximum value for EAX[14:25] as well. In addition, for host-cache-info case, also apply the same checks and fixes. Reviewed-by: Xiaoyao Li Signed-off-by: Qian Wen Signed-off-by: Zhao Liu --- Changes Since New v1 [**]: * Provide an overflow example of EAX[14:25]. Changes Since Original v4 [*]: * Rebase on addressable ID fixup. * Drop R/b tags since the code base changes. * Teak bits 25-14 as well and add the comment. * Fix overflow for host-cache-info case. [*]: original v4: https://lore.kernel.org/qemu-devel/20230829042405.932523-= 3-qian.wen@intel.com/ [**]: new v1: https://lore.kernel.org/qemu-devel/20250227062523.124601-4-zh= ao1.liu@intel.com/ --- target/i386/cpu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 67a371e23b22..fedeeea151ee 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -347,11 +347,17 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache, assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 + /* + * The following fields have bit-width limitations, so consider the + * maximum values to avoid overflow: + * Bits 25-14: maximum 4095. + * Bits 31-26: maximum 63. + */ *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - (max_core_ids_in_package(topo_info) << 26) | - (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); + (MIN(max_core_ids_in_package(topo_info), 63) << 26) | + (MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4= 095) << 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -7928,13 +7934,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); =20 *eax &=3D ~0xFC000000; - *eax |=3D max_core_ids_in_package(topo_info) << 26; + *eax |=3D MIN(max_core_ids_in_package(topo_info), 63) << 2= 6; if (host_vcpus_per_cache > threads_per_pkg) { *eax &=3D ~0x3FFC000; =20 /* Share the cache at package level. */ - *eax |=3D max_thread_ids_for_cache(topo_info, - CPU_TOPOLOGY_LEVEL_SOCKET) << 14; + *eax |=3D MIN(max_thread_ids_for_cache(topo_info, + CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { --=20 2.34.1 From nobody Sun Dec 14 01:53:26 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Jul 2025 03:47:57 -0400 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2025 00:47:55 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 14 Jul 2025 00:47:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752479276; x=1784015276; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KWmh+nOlncMmEQC89o+Q3i7UNZgMqD2lsLZ/ETngSXM=; b=dEY7ZiITllXoMf2r6WPGpLRbacdAQ9asyPQh1+NOtRuszRRW8vMpO9C6 K7cDjPNdAvkD6FlQMcdbmty9JLf505KxTkq8qfEMxS53DoKzPWcVpt2g5 iJoP+v9sVU98dEPeCnh7fOLUgwFIs4eKjNc701ecWuC+XnGTii4SOxv/j 7EUN6IZt22XRet0Qo8rxsU6bOGWLpsyaZ6faTsc8BzoeQWJRCL4HtHeyP 6TOqvOCiifDeC12FEFabeyRg+AIlGk07105955TxDMU6LGhllUnGaeqFo v6pg6hKWdGq8fL10UrofHVoKf/lrwPOuBe/tkAj8X/tkNrfBZ3NP+XaOK Q==; X-CSE-ConnectionGUID: /hA30Cm0Tlq+BdGRm38zRQ== X-CSE-MsgGUID: q93AHBEnTnGvLW4BvUpFbw== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="58324685" X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="58324685" X-CSE-ConnectionGUID: eMe8W2QcS/+eKNVOV+We3g== X-CSE-MsgGUID: sUdgvKc2S7qSd/wvbLrQjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,310,1744095600"; d="scan'208";a="156952231" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov Cc: Ewan Hai , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, Zhao Liu , Babu Moger Subject: [PATCH v2 7/7] i386/cpu: Honor maximum value for CPUID.8000001DH.EAX[25:14] Date: Mon, 14 Jul 2025 16:08:59 +0800 Message-Id: <20250714080859.1960104-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250714080859.1960104-1-zhao1.liu@intel.com> References: <20250714080859.1960104-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.15; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752480637222116600 Content-Type: text/plain; charset="utf-8" CPUID.8000001DH:EAX[25:14] is "NumSharingCache", and the number of logical processors sharing this cache is the value of this field incremented by 1. Because of its width limitation, the maximum value currently supported is 4095. Though at present Q35 supports up to 4096 CPUs, by constructing a specific topology, the width of the APIC ID can be extended beyond 12 bits. For example, using `-smp threads=3D33,cores=3D9,modules=3D9` results = in a die level offset of 6 + 4 + 4 =3D 14 bits, which can also cause overflow. Check and honor the maximum value as CPUID.04H did. Cc: Babu Moger Signed-off-by: Zhao Liu Reviewed-by: Babu Moger --- Changes Since RFC v1 [*]: * Correct the RFC's description, now there's the overflow case. Provide an overflow example. RFC: * Although there are currently no overflow cases, to avoid any potential issue, add the overflow check, just as I did for Intel. [*]: https://lore.kernel.org/qemu-devel/20250227062523.124601-5-zhao1.liu@i= ntel.com/ --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fedeeea151ee..eceda9865b8f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -558,7 +558,8 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, =20 *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - *eax |=3D max_thread_ids_for_cache(topo_info, cache->share_level) << 1= 4; + /* Bits 25:14 - NumSharingCache: maximum 4095. */ + *eax |=3D MIN(max_thread_ids_for_cache(topo_info, cache->share_level),= 4095) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1