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Because QEMU does not model the cache topology, all cache maintenance instructions are implemented as NOPs, hence these new instructions are implemented as NOPs too. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 973b276d90..ce981191b3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5225,6 +5225,18 @@ static void mecid_write(CPUARMState *env, const ARMC= PRegInfo *ri, raw_write(env, ri, value); } =20 +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + static const ARMCPRegInfo mec_reginfo[] =3D { { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, @@ -5264,6 +5276,15 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D mecid_access, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, }; =20 #ifndef CONFIG_USER_ONLY @@ -7425,6 +7446,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (cpu_isar_feature(aa64_mec, cpu)) { define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } } =20 if (cpu_isar_feature(aa64_sctlr2, cpu)) { --=20 2.34.1