From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241130; cv=none; d=zohomail.com; s=zohoarc; b=iWOAvRtNflEvJ1f6t77PS284h0KYd/Eyv8pX1LgiRe3YzGHdRi+UGn3DtRc6asGVF5xefT3h37zJzITDDypfz5O4q59dn5qLKHQM6FUoo8JCU+bZyaNPXvBBCYMsGjtonCf/d07fgXgonZkYuYM1qIByJ3gCnT3vk258b4Isft4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241130; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+fIo7ns6uCAix0AltPNo97lGn4MZUVvmPFiOKdHZbR8=; b=FAUHbY57LoI9jiBTZl7VRQTZtMOGd9drxrWL9K+TDmkgw+g2qgLsTko26tYtS7V7Xh3BafBNOVY9NyRUjHhcC8j+mRgUuLUhzK5kJb0RpabSSuXQUkLQtMMVKz4jNsAicSpKCUPc82N2EjV3+BPK08OOE9rt5D81Z0dqtp0G5yc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241130308462.14150362532473; Fri, 11 Jul 2025 06:38:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuu-0006Uw-Li; Fri, 11 Jul 2025 09:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDte-0004MB-5Y for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:39 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtb-0002vc-30 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:37 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-451e2f0d9c2so18648525e9.1 for ; Fri, 11 Jul 2025 06:34:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240873; x=1752845673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+fIo7ns6uCAix0AltPNo97lGn4MZUVvmPFiOKdHZbR8=; b=pacl7G/cO72sITjUhUVvryHem2cPa78+pDtZ6hWTqy3BgtLHZ1Fh7PzuxFCwi9Mnad sO5clO9MpMn0aaHVOdfwuSSQ0G1R/dw4uaCNQlC0LMa1bsxp5IprgKyu/ztvzskq/0YL JiIWxlTy89rtV8HGwbXQsH8YjBCu+UbAxSe69sDXR9IhU03dJlLLYzlSjkB5dAGcpSqq Cflsc4f2XSmj8H8/SrIIM73nGfeHPcYmnGI8wZRSeTf7n01ETH2Ax/M6Oyh6CR4UM0qC jj52fEVAePd/LaugE/HrIikXXp9Oeq2qa1jIDrgBrHeRTusQNxRL0EO73qWwetRSsTtS EuWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240873; x=1752845673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+fIo7ns6uCAix0AltPNo97lGn4MZUVvmPFiOKdHZbR8=; b=mqCE/1czWFmcMOG2u/r3e8SJizb+iSQHIG62e65mtObFGWoRIvUWQzpEwyqe+f4BjR BbQ88wbwRYNLXZ5Q4KIuo9eqc7Q4hMtLxuRDKNeWq/n/42dIRD3TDoB3FVwBExWHN9NB SeV9D1peRa4bjmIK4vnwnwM0XrZk24NaV4jaLdC0Djatd58zGNwdQX0rODCr1toLVucw vk5vQ8GMSY2s6pba+Ph8LEo3FP2spoYrBGHlLdfHY0UK8U0Ccl6YkIvYAMPUgPSrq7su 50HdNptpXFgG6kzD9MnJE5YBl4vWxD0eX9Uj5l+rGn39CuPOcUCCs6GWVh4KYvbiWel3 p+xQ== X-Gm-Message-State: AOJu0Yz6R3gdasA8+t+wACrRE6GCKTwfOpTc1MTPXRtlGHnJAP/hjBzJ 3xtx7XIcUiJJ9EQyDyjWL+32/hE1qMyKQQ9wWKbtU9NfIxFVdWOgBnEujmnrTtjWEioQgbSCEVZ joQmC X-Gm-Gg: ASbGncu2V2mYtnTQ9Va2IcUQX3DgTyABs7gJ+lwgQI2ICSJWNKAd0JGhYAYrppW6tAo 8IHhtWi+QPm+p4RPU5TKZ0TF3RmJo5lOywqifVCymtbjej1KL+7MJ9p6lDNCrRdFzBPrvaiXJ1w rzHAs7br6SetyCKBW3cHo95KSmGyqK/Q+cmX8PaEPLsSV1xadBv0F6AhcgYzgSNnfaPvuE09VAb Awf0fFNjJOs90PJwXmE8il11L3ERsqY4UDzL8EunwtLiMGS2YXq4XQPoVTCyNYkGOpRWntdavyx AgctlUIjU1ZeJwkGL4Cx4aJ7zU29jFxGiQO02ZKIPKoZpKnBk9+KVrOXQAUf/ynN90FAy0G5Qo/ 3wYHwyiq7/lfXAyFlbXkV0ajY8rVq X-Google-Smtp-Source: AGHT+IHAB+xq2TlvoCvWVuv5sQeD4eWRO+LTyI4qEalDhNdaN8lkoy3oeM2nsUX7TK6pVrxzDivGzQ== X-Received: by 2002:a05:600c:4746:b0:453:7713:476c with SMTP id 5b1f17b1804b1-455bd8e63aemr21962615e9.2.1752240872811; Fri, 11 Jul 2025 06:34:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/36] MAX78000: Add MAX78000FTHR Machine Date: Fri, 11 Jul 2025 14:33:54 +0100 Message-ID: <20250711133429.1423030-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241132086116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This patch adds support for the MAX78000FTHR machine. The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch implements only the MAX78000, which is Cortex-M4 based. Details can be found at: https://www.analog.com/media/en/technical-documentation/user-guides/max7800= 0-user-guide.pdf Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-2-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 35 +++++++ hw/arm/max78000_soc.c | 172 ++++++++++++++++++++++++++++++++++ hw/arm/max78000fthr.c | 50 ++++++++++ hw/arm/Kconfig | 10 ++ hw/arm/meson.build | 2 + 5 files changed, 269 insertions(+) create mode 100644 include/hw/arm/max78000_soc.h create mode 100644 hw/arm/max78000_soc.c create mode 100644 hw/arm/max78000fthr.c diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h new file mode 100644 index 00000000000..97bf4099c99 --- /dev/null +++ b/include/hw/arm/max78000_soc.h @@ -0,0 +1,35 @@ +/* + * MAX78000 SOC + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_MAX78000_SOC_H +#define HW_ARM_MAX78000_SOC_H + +#include "hw/or-irq.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_MAX78000_SOC "max78000-soc" +OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) + +#define FLASH_BASE_ADDRESS 0x10000000 +#define FLASH_SIZE (512 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (128 * 1024) + +struct MAX78000State { + SysBusDevice parent_obj; + + ARMv7MState armv7m; + + MemoryRegion sram; + MemoryRegion flash; + + Clock *sysclk; +}; + +#endif diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c new file mode 100644 index 00000000000..9676ada6a27 --- /dev/null +++ b/hw/arm/max78000_soc.c @@ -0,0 +1,172 @@ +/* + * MAX78000 SOC + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Implementation based on stm32f205 and Max78000 user guide at + * https://www.analog.com/media/en/technical-documentation/user-guides/max= 78000-user-guide.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "system/address-spaces.h" +#include "system/system.h" +#include "hw/arm/max78000_soc.h" +#include "hw/qdev-clock.h" +#include "hw/misc/unimp.h" + +static void max78000_soc_initfn(Object *obj) +{ + MAX78000State *s =3D MAX78000_SOC(obj); + + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); + + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); +} + +static void max78000_soc_realize(DeviceState *dev_soc, Error **errp) +{ + MAX78000State *s =3D MAX78000_SOC(dev_soc); + MemoryRegion *system_memory =3D get_system_memory(); + DeviceState *armv7m; + Error *err =3D NULL; + + if (!clock_has_source(s->sysclk)) { + error_setg(errp, "sysclk clock must be wired up by the board code"= ); + return; + } + + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "MAX78000.flash", + FLASH_SIZE, &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); + + memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, + &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); + + armv7m =3D DEVICE(&s->armv7m); + + /* + * The MAX78000 user guide's Interrupt Vector Table section + * suggests that there are 120 IRQs in the text, while only listing + * 104 in table 5-1. Implement the more generous of the two. + * This has not been tested in hardware. + */ + qdev_prop_set_uint32(armv7m, "num-irq", 120); + qdev_prop_set_uint8(armv7m, "num-prio-bits", 3); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"= )); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); + object_property_set_link(OBJECT(&s->armv7m), "memory", + OBJECT(system_memory), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { + return; + } + + create_unimplemented_device("globalControl", 0x40000000, 0x400); + create_unimplemented_device("systemInterface", 0x40000400, 0x400); + create_unimplemented_device("functionControl", 0x40000800, 0x400); + create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); + create_unimplemented_device("dynamicVoltScale", 0x40003c00, 0x40); + create_unimplemented_device("SIMO", 0x40004400, 0x400); + create_unimplemented_device("trimSystemInit", 0x40005400, 0x400); + create_unimplemented_device("generalCtrlFunc", 0x40005800, 0x400); + create_unimplemented_device("wakeupTimer", 0x40006400, 0x400); + create_unimplemented_device("powerSequencer", 0x40006800, 0x400); + create_unimplemented_device("miscControl", 0x40006c00, 0x400); + + create_unimplemented_device("aes", 0x40007400, 0x400); + create_unimplemented_device("aesKey", 0x40007800, 0x400); + + create_unimplemented_device("gpio0", 0x40008000, 0x1000= ); + create_unimplemented_device("gpio1", 0x40009000, 0x1000= ); + + create_unimplemented_device("parallelCamInterface", 0x4000e000, 0x1000= ); + create_unimplemented_device("CRC", 0x4000f000, 0x1000= ); + + create_unimplemented_device("timer0", 0x40010000, 0x1000= ); + create_unimplemented_device("timer1", 0x40011000, 0x1000= ); + create_unimplemented_device("timer2", 0x40012000, 0x1000= ); + create_unimplemented_device("timer3", 0x40013000, 0x1000= ); + + create_unimplemented_device("i2c0", 0x4001d000, 0x1000= ); + create_unimplemented_device("i2c1", 0x4001e000, 0x1000= ); + create_unimplemented_device("i2c2", 0x4001f000, 0x1000= ); + + create_unimplemented_device("standardDMA", 0x40028000, 0x1000= ); + create_unimplemented_device("flashController0", 0x40029000, 0x400); + + create_unimplemented_device("icc0", 0x4002a000, 0x800); + create_unimplemented_device("icc1", 0x4002a800, 0x800); + + create_unimplemented_device("adc", 0x40034000, 0x1000= ); + create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); + create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); + create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); + + create_unimplemented_device("uart0", 0x40042000, 0x1000= ); + create_unimplemented_device("uart1", 0x40043000, 0x1000= ); + create_unimplemented_device("uart2", 0x40044000, 0x1000= ); + + create_unimplemented_device("spi1", 0x40046000, 0x2000= ); + create_unimplemented_device("trng", 0x4004d000, 0x1000= ); + create_unimplemented_device("i2s", 0x40060000, 0x1000= ); + create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); + create_unimplemented_device("gpio2", 0x40080400, 0x200); + create_unimplemented_device("lowPowerWatchdogTimer", 0x40080800, 0x= 400); + create_unimplemented_device("lowPowerTimer4", 0x40080c00, 0x400); + + create_unimplemented_device("lowPowerTimer5", 0x40081000, 0x400); + create_unimplemented_device("lowPowerUART0", 0x40081400, 0x400); + create_unimplemented_device("lowPowerComparator", 0x40088000, 0x400); + + create_unimplemented_device("spi0", 0x400be000, 0x400); + + /* + * The MAX78000 user guide's base address map lists the CNN TX FIFO as + * beginning at 0x400c0400 and ending at 0x400c0400. Given that CNN_FI= FO + * is listed as having data accessible up to offset 0x1000, the user + * guide is likely incorrect. + */ + create_unimplemented_device("cnnTxFIFO", 0x400c0400, 0x2000= ); + + create_unimplemented_device("cnnGlobalControl", 0x50000000, 0x1000= 0); + create_unimplemented_device("cnnx16quad0", 0x50100000, 0x4000= 0); + create_unimplemented_device("cnnx16quad1", 0x50500000, 0x4000= 0); + create_unimplemented_device("cnnx16quad2", 0x50900000, 0x4000= 0); + create_unimplemented_device("cnnx16quad3", 0x50d00000, 0x4000= 0); + +} + +static void max78000_soc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D max78000_soc_realize; +} + +static const TypeInfo max78000_soc_info =3D { + .name =3D TYPE_MAX78000_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MAX78000State), + .instance_init =3D max78000_soc_initfn, + .class_init =3D max78000_soc_class_init, +}; + +static void max78000_soc_types(void) +{ + type_register_static(&max78000_soc_info); +} + +type_init(max78000_soc_types) diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c new file mode 100644 index 00000000000..c4f6b5b1b04 --- /dev/null +++ b/hw/arm/max78000fthr.c @@ -0,0 +1,50 @@ +/* + * MAX78000FTHR Evaluation Board + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" +#include "qemu/error-report.h" +#include "hw/arm/max78000_soc.h" +#include "hw/arm/boot.h" + +/* 60MHz is the default, but other clocks can be selected. */ +#define SYSCLK_FRQ 60000000ULL +static void max78000_init(MachineState *machine) +{ + DeviceState *dev; + Clock *sysclk; + + sysclk =3D clock_new(OBJECT(machine), "SYSCLK"); + clock_set_hz(sysclk, SYSCLK_FRQ); + + dev =3D qdev_new(TYPE_MAX78000_SOC); + object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); + qdev_connect_clock_in(dev, "sysclk", sysclk); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + 0x00000000, FLASH_SIZE); +} + +static void max78000_machine_init(MachineClass *mc) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), + NULL + }; + + mc->desc =3D "MAX78000FTHR Board (Cortex-M4 / (Unimplemented) RISC-V)"; + mc->init =3D max78000_init; + mc->valid_cpu_types =3D valid_cpu_types; +} + +DEFINE_MACHINE("max78000fthr", max78000_machine_init) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 6ea86534d52..44815af41f5 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -95,6 +95,12 @@ config INTEGRATOR select PL181 # display select SMC91C111 =20 +config MAX78000FTHR + bool + default y + depends on TCG && ARM + select MAX78000_SOC + config MPS3R bool default y @@ -357,6 +363,10 @@ config ALLWINNER_R40 select USB_EHCI_SYSBUS select SD =20 +config MAX78000_SOC + bool + select ARM_V7M + config RASPI bool default y diff --git a/hw/arm/meson.build b/hw/arm/meson.build index d90be8f4c94..dc68391305f 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -27,6 +27,7 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('om= ap1.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-= a10.c', 'cubieboard.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h= 3.c', 'orangepi.c')) arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-= r40.c', 'bananapi_m2u.c')) +arm_common_ss.add(when: 'CONFIG_MAX78000_SOC', if_true: files('max78000_so= c.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c')) arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files= ('bcm2838.c', 'raspi4b.c')) arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_= soc.c')) @@ -71,6 +72,7 @@ arm_ss.add(when: 'CONFIG_XEN', if_true: files( arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c= ')) arm_common_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_common_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c= ')) +arm_common_ss.add(when: 'CONFIG_MAX78000FTHR', if_true: files('max78000fth= r.c')) arm_common_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripheral= s.c')) arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2838_peripheral= s.c')) --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240921; cv=none; d=zohomail.com; s=zohoarc; b=mMzq+sFSlrllc3MVugxww0wfdBZJEoh1jQBBEGAi7snRwSNh3uEuFmvexkLzd/HqvXpxBtUuILi/XEyXhfp13xW920aOqLCXzE6FN3d3tEyS1oyHutzp6Yl3xAUQsIRK8f9WH0Bcw2O1rRugubzE3yrdC6JsDELX152hQ2TVvH4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240921; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=C5aEQ8IqDu8YxF4SP4TfNZxTFSEpR0LJNTlVcVb/ZfI=; b=jbfBOjFP1G5oVklnPccNDkVFS+Oyoh/O7AcYQT7YvsuPDOOmW/1JCwvIHUvjMKVqQKvxBhujFxmoP3PKriXcP9igObEyfqXcXN2hPIMSQK6iLN82LNQySYQKUkpMrMiZMxsCSj+ciNcYuvtU2sQFkxhIrgLxnNIGejfHJRhEFpA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240921207719.9583321276415; Fri, 11 Jul 2025 06:35:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDtr-0004Pu-Te; Fri, 11 Jul 2025 09:34:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDte-0004MC-61 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:39 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtb-0002w1-Ku for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:37 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-454f426b3e5so3490175e9.0 for ; Fri, 11 Jul 2025 06:34:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240874; x=1752845674; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=C5aEQ8IqDu8YxF4SP4TfNZxTFSEpR0LJNTlVcVb/ZfI=; b=v0tGUeXd2BzuLTTH7zZjIq0PeXM4NqHC8FMU7y68SyWPFdYWql35pfvqoNT413okYm EqFOpRmRvbeUDX3gsC3mgh8osOxOOS89xjebhBxki00gwerCi2PuwolgSS2A0/ICHdFT nmC9JI5Lfn15wl2qBUM0Hlumgp+Wbikn/esnXdyHs7eIJ8aTv+8byDc9cwD5TTQV/pFV WlrF8bh46KlKoaq3ReveHcMeRsZuQV5lW+IbvUdR4qWwIQEwWNX6+8Ea5o7X8Q+ObkoC 0Sjk9JqFYvA41biup+nbAlpIjh+jLSD/shUMNfs+MRn668nEVRlOVal/CcXW7Pc/rVSE d70A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240874; x=1752845674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C5aEQ8IqDu8YxF4SP4TfNZxTFSEpR0LJNTlVcVb/ZfI=; b=gCd2agL6vCskH6P2Kws4gJUE6qR1W98jXZB/1bBDiRfbIZLFHENU6JK5K1kYVGY9Td 0BeHQ7cz0h7Np/oDUEb3x8YLH6r7t0GHrbq9/DRztnSpy1WDjo/IyYRltdvLuV24b+Ez ZS7+IOS7e4tg1A9XFYnCLWuHK97MM6yrZb1sAIp4BrPQLb1xVgRzyKbxzbjtkeAprFWK ldAlZrIcU3Et34UrDqNvbwYvkdAez8GRUYFcHLvbrOmNcOhhENIvVkOO68Hs21pelbLM 2E/iZdAV7kWYK4PhHN/vgtK3bd0tUnRhUXCwgJI1tJpVys+G/ysZzdOjdFiksc5pwUQU Bcaw== X-Gm-Message-State: AOJu0YyBqNEgqOEq9uXKItcVBlVWkr7NRth4LbouWoE8BQP0u4eZPZIa xq1p3ONtOKOlrx6MauMNG25fixV7z7L8O3QfXaDAjbloyD10MnpK/QfKgeZk9yYL2BfV3UHFIyW CYz5W X-Gm-Gg: ASbGnctaVrDH8G1jcyt5jFzzCu/idkUH2oVLu79Tra8Nw4r2AEQJu/+ck+4SL/ry0n+ qi60jcnhm0LdBJv6N1Q5jJAIXNwjm5/I65eEG5CoRBaKxjHBKbfNV94mDbWer/UFUQHP9ob7Pip EzBtdySmWV69wAKOwGt/9Ds36HuPrS5CmIKkiglUSX4u4w8QektLXb0FyWTZpez/MioKK0S5xIW 56MWjOjt8XGhhRf3r6J2lKQp2CDzUHQpRVkYSCzKVyonDWLfHHxMjHDi5xQxdrswcbzyAp7CeOz ARbry3lQC+E6V1ZsCuvufg3/JYzfCqVWgO93YQnGpGDh4l1FLJ+LtWrLpCOziO0I6LiBjtQgyew ryJD/7TKnf+wW9Pk7RsA5jLvCJE6h X-Google-Smtp-Source: AGHT+IHF30OCZR525rEuWSloObZXsw1nss40gRjKuOpDo4OZ8Pt/K1egOsrJOQThAF6zNYJCfZWPqA== X-Received: by 2002:a05:6000:2089:b0:3a6:e1bb:a083 with SMTP id ffacd0b85a97d-3b5f2dd2e52mr2847340f8f.25.1752240873919; Fri, 11 Jul 2025 06:34:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/36] MAX78000: ICC Implementation Date: Fri, 11 Jul 2025 14:33:55 +0100 Message-ID: <20250711133429.1423030-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240923306116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit implements the Instruction Cache Controller for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-3-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/misc/max78000_icc.h | 33 +++++++++ hw/misc/max78000_icc.c | 120 +++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + 5 files changed, 158 insertions(+) create mode 100644 include/hw/misc/max78000_icc.h create mode 100644 hw/misc/max78000_icc.c diff --git a/include/hw/misc/max78000_icc.h b/include/hw/misc/max78000_icc.h new file mode 100644 index 00000000000..6fe2bb7a156 --- /dev/null +++ b/include/hw/misc/max78000_icc.h @@ -0,0 +1,33 @@ +/* + * MAX78000 Instruction Cache + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MAX78000_ICC_H +#define HW_MAX78000_ICC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_ICC "max78000-icc" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000IccState, MAX78000_ICC) + +#define ICC_INFO 0x0 +#define ICC_SZ 0x4 +#define ICC_CTRL 0x100 +#define ICC_INVALIDATE 0x700 + +struct Max78000IccState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t info; + uint32_t sz; + uint32_t ctrl; +}; + +#endif diff --git a/hw/misc/max78000_icc.c b/hw/misc/max78000_icc.c new file mode 100644 index 00000000000..6f7d2b20bf5 --- /dev/null +++ b/hw/misc/max78000_icc.c @@ -0,0 +1,120 @@ +/* + * MAX78000 Instruction Cache + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_icc.h" + + +static uint64_t max78000_icc_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000IccState *s =3D opaque; + switch (addr) { + case ICC_INFO: + return s->info; + + case ICC_SZ: + return s->sz; + + case ICC_CTRL: + return s->ctrl; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; + + } +} + +static void max78000_icc_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000IccState *s =3D opaque; + + switch (addr) { + case ICC_CTRL: + s->ctrl =3D 0x10000 | (val64 & 1); + break; + + case ICC_INVALIDATE: + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", + __func__, addr); + break; + } +} + +static const MemoryRegionOps max78000_icc_ops =3D { + .read =3D max78000_icc_read, + .write =3D max78000_icc_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription max78000_icc_vmstate =3D { + .name =3D TYPE_MAX78000_ICC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(info, Max78000IccState), + VMSTATE_UINT32(sz, Max78000IccState), + VMSTATE_UINT32(ctrl, Max78000IccState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_icc_reset_hold(Object *obj, ResetType type) +{ + Max78000IccState *s =3D MAX78000_ICC(obj); + s->info =3D 0; + s->sz =3D 0x10000010; + s->ctrl =3D 0x10000; +} + +static void max78000_icc_init(Object *obj) +{ + Max78000IccState *s =3D MAX78000_ICC(obj); + + memory_region_init_io(&s->mmio, obj, &max78000_icc_ops, s, + TYPE_MAX78000_ICC, 0x800); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void max78000_icc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D max78000_icc_reset_hold; + dc->vmsd =3D &max78000_icc_vmstate; +} + +static const TypeInfo max78000_icc_info =3D { + .name =3D TYPE_MAX78000_ICC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000IccState), + .instance_init =3D max78000_icc_init, + .class_init =3D max78000_icc_class_init, +}; + +static void max78000_icc_register_types(void) +{ + type_register_static(&max78000_icc_info); +} + +type_init(max78000_icc_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 44815af41f5..035568a085e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -366,6 +366,7 @@ config ALLWINNER_R40 config MAX78000_SOC bool select ARM_V7M + select MAX78000_ICC =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index ec0fa5aa9f8..781bcf74ccc 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_ICC + bool + config MOS6522 bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c5..a21a994ff83 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', 'npcm_gcr.c', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240921; cv=none; d=zohomail.com; s=zohoarc; b=jZOwsTu0BgzP11eeB0ehVeNmjSCVqk41RAjxrFdnQLC1EEwF1uu2i2Id8nGuU6G59bCQgW05qeDa/UsP75IWSRyRBCaGZ6Pu4nBiZgzOetJ30L4wdw/ioiNZxoxtWSoaweRNwuZm7o/ED+ckQcXaU5XfLSgosfhq24pMUAeiQKs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240921; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DcshZRdHA+R2F5c57grtYhzclejkjBGcvQNzRFYXK7E=; b=kdJzBBhO9lUdCLyjN/X+YY5Ph+yvy7f1EAHCUtq6CbIYuEacyS0aheMGvKBNVIj3hDs/ooCExpCR6i39V2QrnwB3SRolLlrzToq2bXYDaa3F2ICaSnIynVgDZ3UbD6jvNTw0OZk1CDeuPkeg5b9rObLoOS/3845WGzMJHGc17Jo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240921312291.8186482220581; Fri, 11 Jul 2025 06:35:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDtk-0004Nr-2l; Fri, 11 Jul 2025 09:34:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDte-0004MH-P1 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:39 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtc-0002wT-EX for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:38 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4537deebb01so11863515e9.0 for ; Fri, 11 Jul 2025 06:34:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240875; x=1752845675; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DcshZRdHA+R2F5c57grtYhzclejkjBGcvQNzRFYXK7E=; b=n6+C4eqaEDaHZHSCHXFp0IO3+isVBteTQlrRaEPhnkbWAB2U+BY8hyS3UKnMHKWNxf gEUlVxjds/lGubBMeRIe4pnZKzsKNjvLyBzm3JazzeomOUFxam8dwkObacW0JQeO46oi XrMJVwyoT0s+uFVHErZur9gbEFilojOn17gcoJuJGpaqtRFp5+58TjOj4cdOKVx6ga28 /aFchE/umJnXYbW53xRDp4teBlUC3FiG+ZbxtxIefcgjQTNHlW/fP+A/g8JvgMcxT1Zj 3PBbxzaKGG6TVWf06KGnklM2SyQ+RB5tcGkdlrLoB/GV6ccNviIm+/C11Uh/dzBGjEk5 JZgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240875; x=1752845675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DcshZRdHA+R2F5c57grtYhzclejkjBGcvQNzRFYXK7E=; b=IrOTga+g9gHQqiN5gY39ddk9hVrvyHgHMMCuuG3XqRcExOovucgMR/u0qfitHzX8V+ qfksxVGJ9nVjG4U+xyeqY/cG4OllIuDJQMV2JhR4jkNQW7l6KpczmnFD9u6kjwS502re nogn3/lXn1vDZgzoSDqCUZ9tlMjDBl6FZaVKepn096pPOS7gjI8JGqiAWPL/WC54LLuf DulTEHZBCY7TS8YIMLAg6dsjr0errqCC6oI4q8rkZBBHTgqOuc8yokaiS/Qa2Zz5P8jN /B4rgSALv8DsUstZAiq88BcCzr86lUPVYeSqGb5dL7LfLarBbXqA01e1cevPl3aHZGhb eZqQ== X-Gm-Message-State: AOJu0YzosxO9go9gIdbJFYfECu5JuSGQP3uE52OcTq8LOHs99kz8Qhxt 5TDdJL7eWGxdayVEo3P2sIKROrXokVgqcL1s81j/nTM6q8S3v+uwQXkwOsipxZBUlY48EX4oyyf YGw8B X-Gm-Gg: ASbGncvtQ8R57ueuzHc7vNbOqYMHhmEkLZDCClXcZIrSFCOfDC9EGf2EejQ4sSrCqyT 0Jksbj+zFwcPdHkCpTTQZQVmmB8FGVacvWZ43hORbBU4ZcJvXU0GIjzgqa8bTlsk+E8/TCMeUK9 NU1gy9jFELIc5TV82/YyJ4FisQtjxRcUiLgmkiBfFd9msR98gyG/e6YA4fV/EAdWJt0qk8sAE81 D453HzC33u9mz0WxXfMvb9arcWuXI9YbxR51oc4dnUmz3Ri3UnT0ZHZF8NHrj5amSRmUwMxOepC +atdvmLFdDT2G+Ircr9f/dapJZEnXVfzecyS/fx1Fmv4WWwYkrNoBqscYOP9xABQryySupuWV29 ad/038rehejCURKwtymED4Y2llIMx X-Google-Smtp-Source: AGHT+IG2c7UofLpeu7O5NPvj24unMbofNRJiU5V4VLQNPyTbQhLSBXm70qAlLlSte+9ytav8JDiHNQ== X-Received: by 2002:a05:600c:3d89:b0:450:d30e:ff96 with SMTP id 5b1f17b1804b1-455f30bfc7dmr11257655e9.0.1752240874865; Fri, 11 Jul 2025 06:34:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/36] MAX78000: Add ICC to SOC Date: Fri, 11 Jul 2025 14:33:56 +0100 Message-ID: <20250711133429.1423030-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240923085116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-4-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 6 ++++++ hw/arm/max78000_soc.c | 20 ++++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 97bf4099c99..27b506d6eeb 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_icc.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -21,6 +22,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (128 * 1024) =20 +/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RIS= C */ +#define MAX78000_NUM_ICC 2 + struct MAX78000State { SysBusDevice parent_obj; =20 @@ -29,6 +33,8 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; =20 + Max78000IccState icc[MAX78000_NUM_ICC]; + Clock *sysclk; }; =20 diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 9676ada6a27..0c83b08eca0 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -17,12 +17,20 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 +static const uint32_t max78000_icc_addr[] =3D {0x4002a000, 0x4002a800}; + static void max78000_soc_initfn(Object *obj) { MAX78000State *s =3D MAX78000_SOC(obj); + int i; =20 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + g_autofree char *name =3D g_strdup_printf("icc%d", i); + object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -30,8 +38,9 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) { MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *armv7m; + DeviceState *dev, *armv7m; Error *err =3D NULL; + int i; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -74,6 +83,12 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) return; } =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + dev =3D DEVICE(&(s->icc[i])); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); + } + create_unimplemented_device("globalControl", 0x40000000, 0x400); create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); @@ -107,9 +122,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("standardDMA", 0x40028000, 0x1000= ); create_unimplemented_device("flashController0", 0x40029000, 0x400); =20 - create_unimplemented_device("icc0", 0x4002a000, 0x800); - create_unimplemented_device("icc1", 0x4002a800, 0x800); - create_unimplemented_device("adc", 0x40034000, 0x1000= ); create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241465; cv=none; d=zohomail.com; s=zohoarc; b=V9VVVCUOQhyrZhIhQ2IiElSgRUL6xoMEZZ6XtzoQiC4FEb2djoo7j3cLdAdkz5mh2keeTson5U/34RyUr+a+/MTFSgM+mpyf2OPxKPlFeAQKDlXQMNUHraD9sjybtJYtWOxt0/k82A+STbq147Lp/HiKMxy97enGDRnxOuIgO9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241465; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wK0R7sFv53iD9d97HEP4+jyy3hoUoi+aPZFmxHOWO04=; b=FZ1bVqCMKSDZJJfzM2GED7mIDjn8WrFeUX7+rVlFL7dlaGRid5V0H87OPrkbCPprP7HJAZEjK1Lex9HWxawA317YUmapiIfZ4M9ZiZ8GBYKcVM0TvHOQBt0vN69pKevAd//ua3ckVrefA02tuJIbJ4ReDAk8SGe8mmzp717uQco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241465517278.33219761564226; Fri, 11 Jul 2025 06:44:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuf-0005aF-Ud; Fri, 11 Jul 2025 09:35:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtg-0004Mu-7U for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:40 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtd-0002xH-Hz for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:39 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-453398e90e9so16213885e9.1 for ; Fri, 11 Jul 2025 06:34:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240876; x=1752845676; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wK0R7sFv53iD9d97HEP4+jyy3hoUoi+aPZFmxHOWO04=; b=YRJRIjjmKu7Nk/uh3+5+qUvIAF2Le1fSImKnd8dXnOk0tZTQ0tBKimfhewRep1ziQL eYUg6AK0dwVcx9PW6F9fX9uZRX3ferRzCjOpgcMf3G/C4ieU7wyh4dhV3xUedWBCOmYy TN7akYpU2jRKHYl7F3ZtttCblN1gzCa9skspBjQge4tM16QnGtAFCi7ihjixRtUgDXkO 3S65dryY6E6azpvNE2nnK0TSgrleh9iCd18kdhn9laO7huAs4SPuvbKrHP8nRhxHunZc PmLc8Ziv43RuteF0x1KVtNaTZ+c56bOqXlPysPFEK+1MowRnZnLJtVy7QTcN6MDPZW1U BjQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240876; x=1752845676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wK0R7sFv53iD9d97HEP4+jyy3hoUoi+aPZFmxHOWO04=; b=bOBVNEYv7QVf2g3wFAJRIt1YFxNb0POSsfvH73VyjWAZAbGN+u1snI0VroFUDFRCAL F1pwnIeYF+0FUVdet3783u3Gj8tK5O9p72hVM96HKEicqERarrOXeWKXUYRLqWJYUtgY W5j1Qc8MGbu0gIBcuYeeTLINPkkzTIl/OLiM4rc/CTdxc7MW+mcdViuKgtlZD25Q/r8G zihdPYCOL9U3W93RtdRnvlWFmg3x5Py/gTstFKLC+kcG6sOeXuw1PoA8Wiv26eSspttL CQ6kJpmvmIr4HCk7rGlU74Q0wlYz9UHn4JRDddyXEuSUenGpOsmfJFbdUa9FNU5oqQEt 91VA== X-Gm-Message-State: AOJu0YxcgagCZrajiYo4WHWC264FDoIvSLE5qpFvmbNFL56BQehcJA3c Aga8dMtOYM8WqZDVrrXvm2VmJc/5X9160vi/OksGy/DrnmZ+KFr4Ee/F82V2Lh5ZofzBIG+y3AS TuaUQ X-Gm-Gg: ASbGncuB0+NmCXTW6oUX45SwwphPhZUNm5350+XKL/MhfWLn/Jl6v5B9rlPtstT2o+B p+5Olpl9NzXLLDvnsxYkbvyAo+LJXeIvCPIPcK/pwWjpyJUzquH7m4GIo8DarWoslQC3/iCvnR6 Mo8AOpCoTbZpxzmfoAxTpY+Hh2oo1j8rhG426waGfpt8PWH19t+nHBFnscDSZNYfYW7+TQ60F10 7nmxjfIIDu49mmXy9gv4fk9zpU3zjbXXqSjcGEuzr6JBsDvN6/BiN18teEDwfTI0rIKTY2qOIRy PHs9BOcMXQ7d464q+S9Xiv/NwFt1RNEHAvWYI71uJ5zY6+n3VeV2OngeKXyxQkRGbjKpJtXgOBF uLn3xZBqljDkmE6L9dcrRFeub2jdg X-Google-Smtp-Source: AGHT+IEwq7yAfVMaXpTHS2+i57yjJLJdPMgTl2peEw7NYc+mqwcxOhqHj/knU5xTTvXHtC/nprAs6w== X-Received: by 2002:a05:600c:8483:b0:43d:563:6fef with SMTP id 5b1f17b1804b1-455bd879b86mr20466615e9.21.1752240875802; Fri, 11 Jul 2025 06:34:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/36] MAX78000: UART Implementation Date: Fri, 11 Jul 2025 14:33:57 +0100 Message-ID: <20250711133429.1423030-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241466645116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit implements UART support for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-5-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/char/max78000_uart.h | 78 +++++++++ hw/char/max78000_uart.c | 285 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/char/Kconfig | 3 + hw/char/meson.build | 1 + 5 files changed, 368 insertions(+) create mode 100644 include/hw/char/max78000_uart.h create mode 100644 hw/char/max78000_uart.c diff --git a/include/hw/char/max78000_uart.h b/include/hw/char/max78000_uar= t.h new file mode 100644 index 00000000000..cf90d51dbfa --- /dev/null +++ b/include/hw/char/max78000_uart.h @@ -0,0 +1,78 @@ +/* + * MAX78000 UART + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MAX78000_UART_H +#define HW_MAX78000_UART_H + +#include "hw/sysbus.h" +#include "chardev/char-fe.h" +#include "qemu/fifo8.h" +#include "qom/object.h" + +#define UART_CTRL 0x0 +#define UART_STATUS 0x4 +#define UART_INT_EN 0x8 +#define UART_INT_FL 0xc +#define UART_CLKDIV 0x10 +#define UART_OSR 0x14 +#define UART_TXPEEK 0x18 +#define UART_PNR 0x1c +#define UART_FIFO 0x20 +#define UART_DMA 0x30 +#define UART_WKEN 0x34 +#define UART_WKFL 0x38 + +/* CTRL */ +#define UART_CTF_DIS (1 << 7) +#define UART_FLUSH_TX (1 << 8) +#define UART_FLUSH_RX (1 << 9) +#define UART_BCLKEN (1 << 15) +#define UART_BCLKRDY (1 << 19) + +/* STATUS */ +#define UART_RX_LVL 8 +#define UART_TX_EM (1 << 6) +#define UART_RX_FULL (1 << 5) +#define UART_RX_EM (1 << 4) + +/* PNR (Pin Control Register) */ +#define UART_CTS 1 +#define UART_RTS (1 << 1) + +/* INT_EN / INT_FL */ +#define UART_RX_THD (1 << 4) +#define UART_TX_HE (1 << 6) + +#define UART_RXBUFLEN 0x100 +#define TYPE_MAX78000_UART "max78000-uart" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000UartState, MAX78000_UART) + +struct Max78000UartState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t int_en; + uint32_t int_fl; + uint32_t clkdiv; + uint32_t osr; + uint32_t txpeek; + uint32_t pnr; + uint32_t fifo; + uint32_t dma; + uint32_t wken; + uint32_t wkfl; + + Fifo8 rx_fifo; + + CharBackend chr; + qemu_irq irq; +}; +#endif /* HW_STM32F2XX_USART_H */ diff --git a/hw/char/max78000_uart.c b/hw/char/max78000_uart.c new file mode 100644 index 00000000000..19506d52ef9 --- /dev/null +++ b/hw/char/max78000_uart.c @@ -0,0 +1,285 @@ +/* + * MAX78000 UART + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/char/max78000_uart.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "migration/vmstate.h" +#include "trace.h" + + +static int max78000_uart_can_receive(void *opaque) +{ + Max78000UartState *s =3D opaque; + if (!(s->ctrl & UART_BCLKEN)) { + return 0; + } + return fifo8_num_free(&s->rx_fifo); +} + +static void max78000_update_irq(Max78000UartState *s) +{ + int interrupt_level; + + interrupt_level =3D s->int_fl & s->int_en; + qemu_set_irq(s->irq, interrupt_level); +} + +static void max78000_uart_receive(void *opaque, const uint8_t *buf, int si= ze) +{ + Max78000UartState *s =3D opaque; + + assert(size <=3D fifo8_num_free(&s->rx_fifo)); + + fifo8_push_all(&s->rx_fifo, buf, size); + + uint32_t rx_threshold =3D s->ctrl & 0xf; + + if (fifo8_num_used(&s->rx_fifo) >=3D rx_threshold) { + s->int_fl |=3D UART_RX_THD; + } + + max78000_update_irq(s); +} + +static void max78000_uart_reset_hold(Object *obj, ResetType type) +{ + Max78000UartState *s =3D MAX78000_UART(obj); + + s->ctrl =3D 0; + s->status =3D UART_TX_EM | UART_RX_EM; + s->int_en =3D 0; + s->int_fl =3D 0; + s->osr =3D 0; + s->txpeek =3D 0; + s->pnr =3D UART_RTS; + s->fifo =3D 0; + s->dma =3D 0; + s->wken =3D 0; + s->wkfl =3D 0; + fifo8_reset(&s->rx_fifo); +} + +static uint64_t max78000_uart_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000UartState *s =3D opaque; + uint64_t retvalue =3D 0; + switch (addr) { + case UART_CTRL: + retvalue =3D s->ctrl; + break; + case UART_STATUS: + retvalue =3D (fifo8_num_used(&s->rx_fifo) << UART_RX_LVL) | + UART_TX_EM | + (fifo8_is_empty(&s->rx_fifo) ? UART_RX_EM : 0); + break; + case UART_INT_EN: + retvalue =3D s->int_en; + break; + case UART_INT_FL: + retvalue =3D s->int_fl; + break; + case UART_CLKDIV: + retvalue =3D s->clkdiv; + break; + case UART_OSR: + retvalue =3D s->osr; + break; + case UART_TXPEEK: + if (!fifo8_is_empty(&s->rx_fifo)) { + retvalue =3D fifo8_peek(&s->rx_fifo); + } + break; + case UART_PNR: + retvalue =3D s->pnr; + break; + case UART_FIFO: + if (!fifo8_is_empty(&s->rx_fifo)) { + retvalue =3D fifo8_pop(&s->rx_fifo); + max78000_update_irq(s); + } + break; + case UART_DMA: + /* DMA not implemented */ + retvalue =3D s->dma; + break; + case UART_WKEN: + retvalue =3D s->wken; + break; + case UART_WKFL: + retvalue =3D s->wkfl; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); + break; + } + + return retvalue; +} + +static void max78000_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000UartState *s =3D opaque; + + uint32_t value =3D val64; + uint8_t data; + + switch (addr) { + case UART_CTRL: + if (value & UART_FLUSH_RX) { + fifo8_reset(&s->rx_fifo); + } + if (value & UART_BCLKEN) { + value =3D value | UART_BCLKRDY; + } + s->ctrl =3D value & ~(UART_FLUSH_RX | UART_FLUSH_TX); + + /* + * Software can manage UART flow control manually by setting hfc_en + * in UART_CTRL. This would require emulating uart at a lower leve= l, + * and is currently unimplemented. + */ + + return; + case UART_STATUS: + /* UART_STATUS is read only */ + return; + case UART_INT_EN: + s->int_en =3D value; + return; + case UART_INT_FL: + s->int_fl =3D s->int_fl & ~(value); + max78000_update_irq(s); + return; + case UART_CLKDIV: + s->clkdiv =3D value; + return; + case UART_OSR: + s->osr =3D value; + return; + case UART_PNR: + s->pnr =3D value; + return; + case UART_FIFO: + data =3D value & 0xff; + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ + qemu_chr_fe_write_all(&s->chr, &data, 1); + + /* TX is always empty */ + s->int_fl |=3D UART_TX_HE; + max78000_update_irq(s); + + return; + case UART_DMA: + /* DMA not implemented */ + s->dma =3D value; + return; + case UART_WKEN: + s->wken =3D value; + return; + case UART_WKFL: + s->wkfl =3D value; + return; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + } +} + +static const MemoryRegionOps max78000_uart_ops =3D { + .read =3D max78000_uart_read, + .write =3D max78000_uart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const Property max78000_uart_properties[] =3D { + DEFINE_PROP_CHR("chardev", Max78000UartState, chr), +}; + +static const VMStateDescription max78000_uart_vmstate =3D { + .name =3D TYPE_MAX78000_UART, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000UartState), + VMSTATE_UINT32(status, Max78000UartState), + VMSTATE_UINT32(int_en, Max78000UartState), + VMSTATE_UINT32(int_fl, Max78000UartState), + VMSTATE_UINT32(clkdiv, Max78000UartState), + VMSTATE_UINT32(osr, Max78000UartState), + VMSTATE_UINT32(txpeek, Max78000UartState), + VMSTATE_UINT32(pnr, Max78000UartState), + VMSTATE_UINT32(fifo, Max78000UartState), + VMSTATE_UINT32(dma, Max78000UartState), + VMSTATE_UINT32(wken, Max78000UartState), + VMSTATE_UINT32(wkfl, Max78000UartState), + VMSTATE_FIFO8(rx_fifo, Max78000UartState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_uart_init(Object *obj) +{ + Max78000UartState *s =3D MAX78000_UART(obj); + fifo8_create(&s->rx_fifo, 8); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_uart_ops, s, + TYPE_MAX78000_UART, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void max78000_uart_realize(DeviceState *dev, Error **errp) +{ + Max78000UartState *s =3D MAX78000_UART(dev); + + qemu_chr_fe_set_handlers(&s->chr, max78000_uart_can_receive, + max78000_uart_receive, NULL, NULL, + s, NULL, true); +} + +static void max78000_uart_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D max78000_uart_reset_hold; + + device_class_set_props(dc, max78000_uart_properties); + dc->realize =3D max78000_uart_realize; + + dc->vmsd =3D &max78000_uart_vmstate; +} + +static const TypeInfo max78000_uart_info =3D { + .name =3D TYPE_MAX78000_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000UartState), + .instance_init =3D max78000_uart_init, + .class_init =3D max78000_uart_class_init, +}; + +static void max78000_uart_register_types(void) +{ + type_register_static(&max78000_uart_info); +} + +type_init(max78000_uart_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 035568a085e..7e3610dca8f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -367,6 +367,7 @@ config MAX78000_SOC bool select ARM_V7M select MAX78000_ICC + select MAX78000_UART =20 config RASPI bool diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 9d517f3e287..020c0a84bb6 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -48,6 +48,9 @@ config VIRTIO_SERIAL default y depends on VIRTIO =20 +config MAX78000_UART + bool + config STM32F2XX_USART bool =20 diff --git a/hw/char/meson.build b/hw/char/meson.build index 4e439da8b9e..a9e1dc26c0f 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -26,6 +26,7 @@ system_ss.add(when: 'CONFIG_AVR_USART', if_true: files('a= vr_usart.c')) system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c')) system_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic-uart.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c')) +system_ss.add(when: 'CONFIG_MAX78000_UART', if_true: files('max78000_uart.= c')) system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c')) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240921; cv=none; d=zohomail.com; s=zohoarc; b=dSvgeirur/Z7Uvi1w9tMn0awjuNzAWg1ZPD/d/NfFF/dwUFY3fpyD/4rckhF0YwlJLdN2Ni5b4fKSvOVfTkDyEQldr0KA0yyLgB6kbOKGxVnsRyu3C8SD/gQf/RaGU9QHNQsO6RugBrJLKmzvWMDB9S9NX5r8Iwl7TdlMGGdKD8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240921; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Rpu6tGMLacwKLQnq2DPWdLYq4LlbwJy217T8KX+yI1s=; b=agMvHHRQpjDbVQGh6wuIGG4QRde6Fbl4oVxTbzX7ixnxO7YueTjyZfpFLccVKtNs+6uHtpbiNOjGSqF+OoKWh3AIHMQSrrIkFMo24dlTVwNcLvH5jABrXZZ9UEUsr/fegVtraIaXgWR06dLdPbL05RVJHtSvqdvniGWhhYDoXcw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240921239308.26423387647003; Fri, 11 Jul 2025 06:35:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDto-0004Of-54; Fri, 11 Jul 2025 09:34:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtg-0004N3-F5 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:41 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDte-0002xm-Hm for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:40 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3a575a988f9so1361126f8f.0 for ; Fri, 11 Jul 2025 06:34:38 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240877; x=1752845677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Rpu6tGMLacwKLQnq2DPWdLYq4LlbwJy217T8KX+yI1s=; b=Rq4jrFklx7mVxnamH4bmXEz1g8UCHqEYJC2pyC3oSfDNQ57O/GEmv+4ySDeG4jUQ/S HrqmQiOrVehIi+sEHZfkLjRjJjUGtB5nK0YsFg7yqBnMRkSIcbmrPYK3clyAWT6yUvXJ Eu0wFrL/QPI9KcMx9xE3Hq2zHD2mPsRgcWjX3ZkDJaWyy1whSjk3ZOacITshsblyBjjU nWG3YglhezKxSumFGZwJMvMdQFxct/+iJ7CHCG9b5bTGzqerJzDDHZSN2SKBHsRlV5lE XEh828MzBVsfZ4pFHo2kfjUz2IuqmjRB1jcwGqBzWl4dCiWo6jBiCfgspqqielx7/iBz 5u6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240877; x=1752845677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rpu6tGMLacwKLQnq2DPWdLYq4LlbwJy217T8KX+yI1s=; b=e5M3lMWKkXShsgg030InC94JtpyABQI5uJmVyqB83zRBN8QpEm5j3qttjdLv2ZfvvC fWj2ORTLhahA355qWjuWYDUxJYCoHLI8qT3teyNBw44nOQCSyRk+S9HGCYvWOw4baF/n j2FDBiRO5UOyLaY7Z3e2+rt6jqqflqbESM7SiplJFq8mDU+UL/79zqlUFQBgIRsILXWF bft3Tf0zTPKAnAsW1lfOczCkCNPSJsgItDtKGmohz3yS6+KpRdvurYilXxpjthSQwFQ4 0QwX9ATpBE3Lts2qtEpaxsxzlgShbVYxvXVWYxY3QbsUEdUoLx7gsH5cbdv02w0KSYid OnAA== X-Gm-Message-State: AOJu0Yy3+Z1/0noTBfAsp3V/aE7LLZ9Pu99TVRSEpY1sZ8S1/0IN4QnJ rCPVjQ1H6Q/zNDpyzd7Ynf55KjMDfYaijIcplG938HRCtq8IbvTJT5VK7RsTQje02rCbMRwFV9R Kqj4T X-Gm-Gg: ASbGncs25g1RX6dI0f6QHZydcmywL26ACrSRGoviIEwuSPw7mYk0KQ9jDrVX5GenNNF s/KKFo3oDwBv9YgVBcBO8917kGdyjkLyy+oLso3avcdi6UeqJGV3TUMML/zbEHXX7H2zUSEhnhh pvYpyyZ1BeQcblVDoZISEo0rdajJxL5RZdy/LzuN0E5NA59Bjn3ZscMEX9F0o0hUCIuPHdR0PZo Pj/8xSBpDx6rZJHOz8e3TT3nVqeuTLddDxzklkayQFnAF9/nRAD6n1hMfgc+SLMX2LIEjmdtE5w x7a5rtohhcW2aqnZ6pXQ84YcenCejjHtf35E6QVmSI16ZODHKu/UyQvOlTfO18u9genyCiRCFP3 Og1m2G/jncJugghTgvKjyH0pOTJss X-Google-Smtp-Source: AGHT+IGYnFDECpBpJFxq7J5dltHJi/iphKjN6GrGF0v0p0DbduoiL1f8MMpk88qDMhPMPdVZIZlkzg== X-Received: by 2002:adf:a347:0:b0:3a4:ec32:e4da with SMTP id ffacd0b85a97d-3b5f18806eemr2433669f8f.15.1752240876823; Fri, 11 Jul 2025 06:34:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/36] MAX78000: Add UART to SOC Date: Fri, 11 Jul 2025 14:33:58 +0100 Message-ID: <20250711133429.1423030-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240923241116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit adds UART to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-6-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 3 +++ hw/arm/max78000_soc.c | 28 ++++++++++++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 27b506d6eeb..57894f00359 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -12,6 +12,7 @@ #include "hw/or-irq.h" #include "hw/arm/armv7m.h" #include "hw/misc/max78000_icc.h" +#include "hw/char/max78000_uart.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -24,6 +25,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) =20 /* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RIS= C */ #define MAX78000_NUM_ICC 2 +#define MAX78000_NUM_UART 3 =20 struct MAX78000State { SysBusDevice parent_obj; @@ -34,6 +36,7 @@ struct MAX78000State { MemoryRegion flash; =20 Max78000IccState icc[MAX78000_NUM_ICC]; + Max78000UartState uart[MAX78000_NUM_UART]; =20 Clock *sysclk; }; diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 0c83b08eca0..2f93ab882d4 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -18,6 +18,10 @@ #include "hw/misc/unimp.h" =20 static const uint32_t max78000_icc_addr[] =3D {0x4002a000, 0x4002a800}; +static const uint32_t max78000_uart_addr[] =3D {0x40042000, 0x40043000, + 0x40044000}; + +static const int max78000_uart_irq[] =3D {14, 15, 34}; =20 static void max78000_soc_initfn(Object *obj) { @@ -31,6 +35,12 @@ static void max78000_soc_initfn(Object *obj) object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); } =20 + for (i =3D 0; i < MAX78000_NUM_UART; i++) { + g_autofree char *name =3D g_strdup_printf("uart%d", i); + object_initialize_child(obj, name, &s->uart[i], + TYPE_MAX78000_UART); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -39,6 +49,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *dev, *armv7m; + SysBusDevice *busdev; Error *err =3D NULL; int i; =20 @@ -89,6 +100,19 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); } =20 + for (i =3D 0; i < MAX78000_NUM_UART; i++) { + dev =3D DEVICE(&(s->uart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, + max78000_uart_irq[i= ])); + } + create_unimplemented_device("globalControl", 0x40000000, 0x400); create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); @@ -127,10 +151,6 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); =20 - create_unimplemented_device("uart0", 0x40042000, 0x1000= ); - create_unimplemented_device("uart1", 0x40043000, 0x1000= ); - create_unimplemented_device("uart2", 0x40044000, 0x1000= ); - create_unimplemented_device("spi1", 0x40046000, 0x2000= ); create_unimplemented_device("trng", 0x4004d000, 0x1000= ); create_unimplemented_device("i2s", 0x40060000, 0x1000= ); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241254; cv=none; d=zohomail.com; s=zohoarc; b=MEhjExzLKfc+CSZulfZeZQBO6QnTE9JRG1KLiI/gMyNLXh4AVvj9v2prYX5Zz7JVtuykPKzPIHztptOB/iunG3PspS1fEi9eTIzqKY3NZahhLiCTEYokIloTmPmzdDxuid+6FckYvnhcNpKC0euf10HQIqwIJ3tvok/5D3jMJeo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241254; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=FwMEP6QOJhHNmph44EFhOUTB7iSOMcPrWvEdOrffXxE=; b=JImg3HDgmVT2fUepdfF4hDakU05HIanyWSiYnQxfJgPHDfwv5QsuPBrRox0WvVs0O02hWn+gl2w9VztyAVnpqLWxfGLEpBoipEJwZMk5pbCfZ7Ws3yXYtCtp4tiuIEW3q+68SlTFIouDoc3p/GyV6PsNA0KoBqVvHnrb66eotGE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241254991664.1030831266863; Fri, 11 Jul 2025 06:40:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDub-0005RM-2o; Fri, 11 Jul 2025 09:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDti-0004Nt-CN for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:44 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtf-0002yT-Pl for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:42 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3a582e09144so1374795f8f.1 for ; Fri, 11 Jul 2025 06:34:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240878; x=1752845678; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FwMEP6QOJhHNmph44EFhOUTB7iSOMcPrWvEdOrffXxE=; b=FDpZf3PloCeM08DzX1XfKv5Pqah8brwyY37zYq+mUfuCERH7m8ynAJmNs9Bg/TdB98 VFtomM0gESYY7eGw+aZpl2bEZSyNzsn4DcpJJgbqXPmBJT73G8tsW7MVh2QG6VyI2OPk UmO89UgMYzk2XkPLYnkO278V5os93htbHcxR3HE+iamkRwYTnBZqC5RhDFNBgOd16jil p+4Ofz2XJVz/vuAWCxphMSe9j8d5FQE4ziNghEgPbJVmax8QSrHg960QEmXIINp/+cr+ O+J3zIZdSv96i482IGjZhdj9l71YhD4xQorkEQ6seIg/c3d7K3LAUdcOjmlsw79Jd8cl iclA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240878; x=1752845678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FwMEP6QOJhHNmph44EFhOUTB7iSOMcPrWvEdOrffXxE=; b=UiBkjcrKcebV5RvCM1HrsytL2JumMDO3HGmFPwpSEqaPOwOQfAHQ8nQ/ExnbmsStYC GFo/ebqEEA5TQ6N+KmehC/8+x+ZHqasBZWQB6Qs4R6kHbBX5EYXhRsQ2qoFRxVUcMZ2Y RB3QWOd9R/xqwLUG/ZlC90mzErDseX+zXPTY/iY7853tN0819TrTZK69urt7uI98P0Ty PwgVyZ8u2L+b6XzIEPTAAyU9LqcpySExER0M+78VPgCD0EVqbXrQtSBGjempL1VMxW6H 5A/xQvT81MYyW2G78V+HpGLANUWyV8QGBeSt0T2fxCDRt4f8QQRSsCwcYN1RvjwcYvj8 fQsw== X-Gm-Message-State: AOJu0YxXiwpz+Ogbig+tDQ/xptnlZTj/s/yWu7EoQ6Cu+Hmg+bae+9ym tSS9RDnYqIS8zfYJ+EurInu2iSuUk7BUKP4dkgj4ECSmaj0F/OV6wYhMb6JcY3KjAm1UqF7tBIW sNR2Y X-Gm-Gg: ASbGnctGK4rkVoprkHdwRd+mZvxQ4dpEMQ+//Ebx6QP9BGJSEMrin7uY4k05OiX2cDq pnkpRmFqysfvk5Cmj929hHaJl+MHY6Vzl9ldaxioL5qDaZuIcodNXQfh+nVmAIKqOjmFhlCwfsE JdAzQvOvoCDJLWHcu/8mRwD9x/8MSwRJXcxTuL/lxER0cFVtttrxFUXdFSLEcQoA48Q/HVycY65 rPATBUaseKLbmjM3jxVj/zveiIY3fIQRBEgxTR5Daic6aomQB6MbB09QPtSDSwTq61WIITNOU1c 5u8ngKdHeEt1l/i6OUoELIgCPd99TO00aYG56kUh8v5PxfNn+2poxCu54DmEuKh2sfxylwSS9FM F3/6N2e5R/MI34ja0vR4sWttoM3a3 X-Google-Smtp-Source: AGHT+IGeDAXR5XlzMVG9/AQggapUn4Kbs3uxa3IhDSfarhpkjo/5sniESqCdOECqqME8VsoLLkvDOQ== X-Received: by 2002:a05:6000:1a87:b0:3a5:3930:f57 with SMTP id ffacd0b85a97d-3b5f2e3722amr2557111f8f.51.1752240877795; Fri, 11 Jul 2025 06:34:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/36] MAX78000: GCR Implementation Date: Fri, 11 Jul 2025 14:33:59 +0100 Message-ID: <20250711133429.1423030-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241255893116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit implements the Global Control Register for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-7-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/misc/max78000_gcr.h | 129 +++++++++++++ hw/misc/max78000_gcr.c | 339 +++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + 5 files changed, 473 insertions(+) create mode 100644 include/hw/misc/max78000_gcr.h create mode 100644 hw/misc/max78000_gcr.c diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h new file mode 100644 index 00000000000..f04c8a3ee7b --- /dev/null +++ b/include/hw/misc/max78000_gcr.h @@ -0,0 +1,129 @@ +/* + * MAX78000 Global Control Register + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_GCR_H +#define HW_MAX78000_GCR_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_GCR "max78000-gcr" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR) + +#define SYSCTRL 0x0 +#define RST0 0x4 +#define CLKCTRL 0x8 +#define PM 0xc +#define PCLKDIV 0x18 +#define PCLKDIS0 0x24 +#define MEMCTRL 0x28 +#define MEMZ 0x2c +#define SYSST 0x40 +#define RST1 0x44 +#define PCKDIS1 0x48 +#define EVENTEN 0x4c +#define REVISION 0x50 +#define SYSIE 0x54 +#define ECCERR 0x64 +#define ECCED 0x68 +#define ECCIE 0x6c +#define ECCADDR 0x70 + +/* RST0 */ +#define SYSTEM_RESET (1 << 31) +#define PERIPHERAL_RESET (1 << 30) +#define SOFT_RESET (1 << 29) +#define UART2_RESET (1 << 28) + +#define ADC_RESET (1 << 26) +#define CNN_RESET (1 << 25) +#define TRNG_RESET (1 << 24) + +#define RTC_RESET (1 << 17) +#define I2C0_RESET (1 << 16) + +#define SPI1_RESET (1 << 13) +#define UART1_RESET (1 << 12) +#define UART0_RESET (1 << 11) + +#define TMR3_RESET (1 << 8) +#define TMR2_RESET (1 << 7) +#define TMR1_RESET (1 << 6) +#define TMR0_RESET (1 << 5) + +#define GPIO1_RESET (1 << 3) +#define GPIO0_RESET (1 << 2) +#define WDT0_RESET (1 << 1) +#define DMA_RESET (1 << 0) + +/* CLKCTRL */ +#define SYSCLK_RDY (1 << 13) + +/* MEMZ */ +#define ram0 (1 << 0) +#define ram1 (1 << 1) +#define ram2 (1 << 2) +#define ram3 (1 << 3) + +/* RST1 */ +#define CPU1_RESET (1 << 31) + +#define SIMO_RESET (1 << 25) +#define DVS_RESET (1 << 24) + +#define I2C2_RESET (1 << 20) +#define I2S_RESET (1 << 19) + +#define SMPHR_RESET (1 << 16) + +#define SPI0_RESET (1 << 11) +#define AES_RESET (1 << 10) +#define CRC_RESET (1 << 9) + +#define PT_RESET (1 << 1) +#define I2C1_RESET (1 << 0) + + +#define SYSRAM0_START 0x20000000 +#define SYSRAM1_START 0x20008000 +#define SYSRAM2_START 0x20010000 +#define SYSRAM3_START 0x2001C000 + +struct Max78000GcrState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t sysctrl; + uint32_t rst0; + uint32_t clkctrl; + uint32_t pm; + uint32_t pclkdiv; + uint32_t pclkdis0; + uint32_t memctrl; + uint32_t memz; + uint32_t sysst; + uint32_t rst1; + uint32_t pckdis1; + uint32_t eventen; + uint32_t revision; + uint32_t sysie; + uint32_t eccerr; + uint32_t ecced; + uint32_t eccie; + uint32_t eccaddr; + + MemoryRegion *sram; + AddressSpace sram_as; + + DeviceState *uart0; + DeviceState *uart1; + DeviceState *uart2; + +}; + +#endif diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c new file mode 100644 index 00000000000..8c282f3916f --- /dev/null +++ b/hw/misc/max78000_gcr.c @@ -0,0 +1,339 @@ +/* + * MAX78000 Global Control Registers + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "system/runstate.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_gcr.h" + + +static void max78000_gcr_reset_hold(Object *obj, ResetType type) +{ + DeviceState *dev =3D DEVICE(obj); + Max78000GcrState *s =3D MAX78000_GCR(dev); + s->sysctrl =3D 0x21002; + s->rst0 =3D 0; + /* All clocks are always ready */ + s->clkctrl =3D 0x3e140008; + s->pm =3D 0x3f000; + s->pclkdiv =3D 0; + s->pclkdis0 =3D 0xffffffff; + s->memctrl =3D 0x5; + s->memz =3D 0; + s->sysst =3D 0; + s->rst1 =3D 0; + s->pckdis1 =3D 0xffffffff; + s->eventen =3D 0; + s->revision =3D 0xa1; + s->sysie =3D 0; + s->eccerr =3D 0; + s->ecced =3D 0; + s->eccie =3D 0; + s->eccaddr =3D 0; +} + +static uint64_t max78000_gcr_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000GcrState *s =3D opaque; + + switch (addr) { + case SYSCTRL: + return s->sysctrl; + + case RST0: + return s->rst0; + + case CLKCTRL: + return s->clkctrl; + + case PM: + return s->pm; + + case PCLKDIV: + return s->pclkdiv; + + case PCLKDIS0: + return s->pclkdis0; + + case MEMCTRL: + return s->memctrl; + + case MEMZ: + return s->memz; + + case SYSST: + return s->sysst; + + case RST1: + return s->rst1; + + case PCKDIS1: + return s->pckdis1; + + case EVENTEN: + return s->eventen; + + case REVISION: + return s->revision; + + case SYSIE: + return s->sysie; + + case ECCERR: + return s->eccerr; + + case ECCED: + return s->ecced; + + case ECCIE: + return s->eccie; + + case ECCADDR: + return s->eccaddr; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + return 0; + + } +} + +static void max78000_gcr_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000GcrState *s =3D opaque; + uint32_t val =3D val64; + uint8_t zero[0xc000] =3D {0}; + switch (addr) { + case SYSCTRL: + /* Checksum calculations always pass immediately */ + s->sysctrl =3D (val & 0x30000) | 0x1002; + break; + + case RST0: + if (val & SYSTEM_RESET) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } + if (val & PERIPHERAL_RESET) { + /* + * Peripheral reset resets all peripherals. The CPU + * retains its state. The GPIO, watchdog timers, AoD, + * RAM retention, and general control registers (GCR), + * including the clock configuration, are unaffected. + */ + val =3D UART2_RESET | UART1_RESET | UART0_RESET | + ADC_RESET | CNN_RESET | TRNG_RESET | + RTC_RESET | I2C0_RESET | SPI1_RESET | + TMR3_RESET | TMR2_RESET | TMR1_RESET | + TMR0_RESET | WDT0_RESET | DMA_RESET; + } + if (val & SOFT_RESET) { + /* Soft reset also resets GPIO */ + val =3D UART2_RESET | UART1_RESET | UART0_RESET | + ADC_RESET | CNN_RESET | TRNG_RESET | + RTC_RESET | I2C0_RESET | SPI1_RESET | + TMR3_RESET | TMR2_RESET | TMR1_RESET | + TMR0_RESET | GPIO1_RESET | GPIO0_RESET | + DMA_RESET; + } + if (val & UART2_RESET) { + device_cold_reset(s->uart2); + } + if (val & UART1_RESET) { + device_cold_reset(s->uart1); + } + if (val & UART0_RESET) { + device_cold_reset(s->uart0); + } + /* TODO: As other devices are implemented, add them here */ + break; + + case CLKCTRL: + s->clkctrl =3D val | SYSCLK_RDY; + break; + + case PM: + s->pm =3D val; + break; + + case PCLKDIV: + s->pclkdiv =3D val; + break; + + case PCLKDIS0: + s->pclkdis0 =3D val; + break; + + case MEMCTRL: + s->memctrl =3D val; + break; + + case MEMZ: + if (val & ram0) { + address_space_write(&s->sram_as, SYSRAM0_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x8000); + } + if (val & ram1) { + address_space_write(&s->sram_as, SYSRAM1_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x8000); + } + if (val & ram2) { + address_space_write(&s->sram_as, SYSRAM2_START, + MEMTXATTRS_UNSPECIFIED, zero, 0xC000); + } + if (val & ram3) { + address_space_write(&s->sram_as, SYSRAM3_START, + MEMTXATTRS_UNSPECIFIED, zero, 0x4000); + } + break; + + case SYSST: + s->sysst =3D val; + break; + + case RST1: + /* TODO: As other devices are implemented, add them here */ + s->rst1 =3D val; + break; + + case PCKDIS1: + s->pckdis1 =3D val; + break; + + case EVENTEN: + s->eventen =3D val; + break; + + case REVISION: + s->revision =3D val; + break; + + case SYSIE: + s->sysie =3D val; + break; + + case ECCERR: + s->eccerr =3D val; + break; + + case ECCED: + s->ecced =3D val; + break; + + case ECCIE: + s->eccie =3D val; + break; + + case ECCADDR: + s->eccaddr =3D val; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\= n", + __func__, addr); + break; + + } +} + +static const Property max78000_gcr_properties[] =3D { + DEFINE_PROP_LINK("sram", Max78000GcrState, sram, + TYPE_MEMORY_REGION, MemoryRegion*), + DEFINE_PROP_LINK("uart0", Max78000GcrState, uart0, + TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("uart1", Max78000GcrState, uart1, + TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2, + TYPE_MAX78000_UART, DeviceState*), +}; + +static const MemoryRegionOps max78000_gcr_ops =3D { + .read =3D max78000_gcr_read, + .write =3D max78000_gcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription vmstate_max78000_gcr =3D { + .name =3D TYPE_MAX78000_GCR, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(sysctrl, Max78000GcrState), + VMSTATE_UINT32(rst0, Max78000GcrState), + VMSTATE_UINT32(clkctrl, Max78000GcrState), + VMSTATE_UINT32(pm, Max78000GcrState), + VMSTATE_UINT32(pclkdiv, Max78000GcrState), + VMSTATE_UINT32(pclkdis0, Max78000GcrState), + VMSTATE_UINT32(memctrl, Max78000GcrState), + VMSTATE_UINT32(memz, Max78000GcrState), + VMSTATE_UINT32(sysst, Max78000GcrState), + VMSTATE_UINT32(rst1, Max78000GcrState), + VMSTATE_UINT32(pckdis1, Max78000GcrState), + VMSTATE_UINT32(eventen, Max78000GcrState), + VMSTATE_UINT32(revision, Max78000GcrState), + VMSTATE_UINT32(sysie, Max78000GcrState), + VMSTATE_UINT32(eccerr, Max78000GcrState), + VMSTATE_UINT32(ecced, Max78000GcrState), + VMSTATE_UINT32(eccie, Max78000GcrState), + VMSTATE_UINT32(eccaddr, Max78000GcrState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_gcr_init(Object *obj) +{ + Max78000GcrState *s =3D MAX78000_GCR(obj); + + memory_region_init_io(&s->mmio, obj, &max78000_gcr_ops, s, + TYPE_MAX78000_GCR, 0x400); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_gcr_realize(DeviceState *dev, Error **errp) +{ + Max78000GcrState *s =3D MAX78000_GCR(dev); + + address_space_init(&s->sram_as, s->sram, "sram"); +} + +static void max78000_gcr_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + device_class_set_props(dc, max78000_gcr_properties); + + dc->realize =3D max78000_gcr_realize; + dc->vmsd =3D &vmstate_max78000_gcr; + rc->phases.hold =3D max78000_gcr_reset_hold; +} + +static const TypeInfo max78000_gcr_info =3D { + .name =3D TYPE_MAX78000_GCR, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000GcrState), + .instance_init =3D max78000_gcr_init, + .class_init =3D max78000_gcr_class_init, +}; + +static void max78000_gcr_register_types(void) +{ + type_register_static(&max78000_gcr_info); +} + +type_init(max78000_gcr_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7e3610dca8f..a96349ee118 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -368,6 +368,7 @@ config MAX78000_SOC select ARM_V7M select MAX78000_ICC select MAX78000_UART + select MAX78000_GCR =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 781bcf74ccc..fde2266b8fc 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_GCR + bool + config MAX78000_ICC bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index a21a994ff83..283d06dad4d 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240926; cv=none; d=zohomail.com; s=zohoarc; b=c74jQtYLD2YB/QenOoOmdvqLZIOTbBWtWfNeSxRHqzc1IcLJZvplYsdJfzw6TzmIfqfDeBv+U+5BijnHrZoqr7hblwk6kdNx2XjQPPuPK6ccsAu4s+nABYFiG9jiFYahNfnQ7o7kA7L4Fgp/d6vJQcT4lJCouF0JEIRKblt+K58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240926; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IbWkS2Lz1RSDDCgrF//hw5Y0E8siEDxPmbN3bJe1c5E=; b=gq6Za3mZp+v/NMO6D6tqJZljkPaC+lVv/Jx79ulU8UyOUNXPi+v+f+9rWwiVyU9aAGTrJtPs9vFLu5m8tg7U5gKqK5xVsqF8sy6B8UBMqtBsFlP7zeoti3KC3Wx6g4tEH6PO2D8c8QKOJM4XA2MNjkj7NXlWRbJmaRQgHItk72E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175224092636227.147238523655915; Fri, 11 Jul 2025 06:35:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuI-0004nX-3a; Fri, 11 Jul 2025 09:35:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtl-0004Oz-Oz for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:47 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtg-0002yp-Hq for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:45 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-455b00283a5so3368835e9.0 for ; Fri, 11 Jul 2025 06:34:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240879; x=1752845679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IbWkS2Lz1RSDDCgrF//hw5Y0E8siEDxPmbN3bJe1c5E=; b=SsVIDv3Ayhuajf0B7/8SGqYhIwbJyPJWLRwZLWQaioOlwr0HzYjvcfAnXXHUuGB08b 7ZcYVtvHRMjm5z5CuF9aEFN47mDnmz+hwzI1lrN9z403et1os4MkRLug/c4QaUfFjTA4 S4/NrP3pBwbh5xuWqmOWY4uPALj7T+K690kIJ+LI8tspu5NZHNEP6EWdTo7iEJkWiEQh FIziX8fEfnhcLml+eCEjKayq4kAbMlEZVAXdIrJOmk/c2uafIc2DlCDPvVkWoXhnQaQu C+k+ayMW9OKQJJatauhhokt3ddXqt/DVFuiXJWxB+mZGv6Waxemr0uRJIHXv/Inrez7y SBQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240879; x=1752845679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IbWkS2Lz1RSDDCgrF//hw5Y0E8siEDxPmbN3bJe1c5E=; b=ciKEistixG8ct66ugW3xg4SJPxiZtejDGsZsGuaBPYHImTuZTFlXLV4VX+UlZ1nb6W 7zZJoiJ047vR+6gtEImHNtd15KAXIU2Ss1vkR1sYrJ4S+rPk3KjDr7B8BQgLafcM86Rd KdpkAmFu+YG3ukBxYyR61J0E3uU6l+AyFL/JNX17E7DxpKUZcpG+UlDB2lgFip33TYuL TdNZI0J/6enkYJYxtdvxJMr4goWqONkOm4HWlnQ3cbSv3pL1xu6N9qmz8HTF5xX2SR93 G6a1FtirCIyabWDWPAZKEjcaZuUeeX+81sVU3Pzx0wZKINa0UK2/NGvnZzNAAcMn5KXY HCIg== X-Gm-Message-State: AOJu0YxGi4oSirpn5f5DktB8NQs+XJJ3ZWeW7ZHZeKouvO+a8zLXfp/X ul4VsfIs+kIzEvdRtuk0/sl+SmPvsoxcvrenT6AWm7GxUcbN+/iKKscMBb0hc4UE7QziqoV5Zss utWvp X-Gm-Gg: ASbGncu0i0hFjc0eta8NlDJ9GO/o4tMvnmV8EW+R4DDrKD9bj1jQ0jZVR3raTdY0Fea I/AIRGe7r+2oWmprwKrcyDxAwly7X0dSbNq5t+PDRD1UzKtx9pFwjmxPjdSU7ZY6AvcFPpxmS2t DyKPPMwaGiO0PAjRbTy2DNsmvUwqEZxGz5Pdn9+kHQ6dd+vbO/jBThc07CZedE2vLwInZvTOzk0 W6DbYfaWKkWwuFRnkpL4RJenpU6yev63cs+ZbyBe1fdofHt2zwVuZ4sjLNmjkBMl3diOYA8+2f2 jiY8Rmms7lUXMNu1AqUoulC4VfIb/ULz6B23yvFrT/VkdH8+7w0ABYS1AUHjqEjXgEcDBsB8z2h ELAKQ3rZOmHc9/qxFfAliOndrlunP X-Google-Smtp-Source: AGHT+IHqBOdlFqG4x8i1tcRtlMZBbp7X07oaWyTABDd7wdZktH0Q02TwNIE9ot4cFpmqcXMYEDAUlw== X-Received: by 2002:a05:600c:3b05:b0:43c:f513:958a with SMTP id 5b1f17b1804b1-454ec16cc0fmr33497755e9.13.1752240878871; Fri, 11 Jul 2025 06:34:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/36] MAX78000: Add GCR to SOC Date: Fri, 11 Jul 2025 14:34:00 +0100 Message-ID: <20250711133429.1423030-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240927300116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit adds the Global Control Register to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-8-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 2 ++ hw/arm/max78000_soc.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 57894f00359..919aca0855f 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" #include "qom/object.h" @@ -35,6 +36,7 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; =20 + Max78000GcrState gcr; Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; =20 diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 2f93ab882d4..45c60883121 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -30,6 +30,8 @@ static void max78000_soc_initfn(Object *obj) =20 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); =20 + object_initialize_child(obj, "gcr", &s->gcr, TYPE_MAX78000_GCR); + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { g_autofree char *name =3D g_strdup_printf("icc%d", i); object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); @@ -48,7 +50,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) { MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *dev, *armv7m; + DeviceState *dev, *gcrdev, *armv7m; SysBusDevice *busdev; Error *err =3D NULL; int i; @@ -69,6 +71,11 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) =20 memory_region_init_ram(&s->sram, NULL, "MAX78000.sram", SRAM_SIZE, &err); + + gcrdev =3D DEVICE(&s->gcr); + object_property_set_link(OBJECT(gcrdev), "sram", OBJECT(&s->sram), + &err); + if (err !=3D NULL) { error_propagate(errp, err); return; @@ -101,19 +108,26 @@ static void max78000_soc_realize(DeviceState *dev_soc= , Error **errp) } =20 for (i =3D 0; i < MAX78000_NUM_UART; i++) { + g_autofree char *link =3D g_strdup_printf("uart%d", i); dev =3D DEVICE(&(s->uart[i])); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { return; } =20 + object_property_set_link(OBJECT(gcrdev), link, OBJECT(dev), + &err); + busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, max78000_uart_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, max78000_uart_irq[i= ])); } =20 - create_unimplemented_device("globalControl", 0x40000000, 0x400); + dev =3D DEVICE(&s->gcr); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); + create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); create_unimplemented_device("watchdogTimer0", 0x40003000, 0x400); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241250; cv=none; d=zohomail.com; s=zohoarc; b=VNT7+C+hC0GIt/zOZhTv3pmv8smuT6sQR5+27RaAz1jjk+FIsd9AcKFEkEv9+j70V2DHzTbk0zT82Kn2qwA+e9BlgUPgUryJ61Ds5Bbva2e5eL+uLD2jtL4dUAPbOBmwWQFYYx3CPL9keyslj3De3jY58pM1FfpkkJuFVuzua7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241250; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uZm8K2Z4owBWHBWBi2KxHz/YZ075aCoUBIbwy/8Ca/4=; b=aaALN9kMQG2jeh6AGCiOeu8ZriZf/WB82hauOtcVOS7snSdicHG5UyKv/7J/l6PEUsBDtbXHCOe9SJK5zzksy8mzRegAn+dqk9szkzOcvmRLZtWwNOIT2TBbS6/Ih2v9dU89zk2gvBqNyuXgi5heuvn8WkCFlzFjrHDM1bJzO60= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175224125020481.09475172822727; Fri, 11 Jul 2025 06:40:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuX-0005Kc-RL; Fri, 11 Jul 2025 09:35:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtk-0004OY-5N for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:46 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDth-0002zg-W8 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:43 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3a5257748e1so1612294f8f.2 for ; Fri, 11 Jul 2025 06:34:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240880; x=1752845680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uZm8K2Z4owBWHBWBi2KxHz/YZ075aCoUBIbwy/8Ca/4=; b=Aj4aVOWgVkg6p9LA90bQyzzjyPHe+rNPK9y1K2BmEZbjeK8WRc3OHlMxqmmlZ8n3Dd TuXNx7qhdep2/+Aw/mj8IwXZrk+zUcSPFWZBiAUTEZgdQvFXtEoA5Hwt636Vr+WJtrvf CqQ3xb2Gwwo72OSj/sV3RXcI4iDm7kCJOkzPNbfiQ1xoQETWx/oDPLykg8/RnkdfG8vy JIynA2wPop/M+TRjNBi82O33Iq1tPZqcnYrYwyx8naqE2dWF7SSjwBKnZxOtcOF0PPNY Z+aifpVBe4fCv1pNtoXJaRLazNLZ85QLmkzmactnD8Qna2pgR3qgIC1jicrVj9Y6bMun 63lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240880; x=1752845680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uZm8K2Z4owBWHBWBi2KxHz/YZ075aCoUBIbwy/8Ca/4=; b=dReppXxMKQjWOrBniA4fiUnS5gS7DM/vl1Utwqs3f1ZXSDC+iCtMRdR2pkasDSRuRU 7+Qj8GoRTwr2Im+23g3Fm3llUPq9N2jo2ANnJZ9IULjkAZlY0hpbrgW1JDEHA8vkeDkV 3Hsn8o9YiYHfU3/DlCcXwIIV9FRkyo7XX8/3t1Ru0gIpScf4FOefsTUOVGo/PVnhZKOW JcNaJrVz2XTgEHRj+Xpv8cT08RAdwnUWAHNYyYXTEJf0QxDZYOGpNVAh6YNtlsjIAOpo CdVlTa35r8mCDIgisL9O7OEPNXNR9l7QBXWIWIvNNZR19NCdXN9RJQBtKBQhh7aHLHnw tE4w== X-Gm-Message-State: AOJu0YxY/99SQqtVc+IKKwZzPuYVnKa+sz/lfarUtZ2Jj4jz6hQ0gGdL 5QPvFNenFF1XXvpI0RY7R5UgeQ6mePewuNgdHbFfOLtrvf6BeBhyXRs+t19pc2hcLb8eOMVvpjC gt8Dv X-Gm-Gg: ASbGncvxzR4PW9Cf08cmmgk0hIuJUwF+f0E/PIvbo2CrmSIzpqF1IR70wvYEpbBoQIq TnRMuhLDzRx9Puw6QOEcCCDuySLqu8JciOyV2YsojLgBd3SOlQdRBsWdsUEapN8o6/icKNAeQwE 4GVk5XMxaYAaFQkzbkwIs2jeEoorkaBDaDRzzRKLNfmNo7mtES2K7nSO3WG9HuftRxGrum2I823 jqJYi7/AcDwhIb+ns/hh5a934Q+WrRinF/vNrO1R3zBxN43VlfOfA+mllyj6vh+V7KX7uikdXe2 ygDea0WW8oUt95wpnCMYJ+vJ5Grk/wazXetSm0ZqRHQcNrj0d7dPh7DNNblNMb3M0tOzjvAPPbx OwoR3XzkpIUVf2V44Ws6OMQwvY85N X-Google-Smtp-Source: AGHT+IFRFZCG14TkcZg5inTmtrH7JYPqcw9MeejGtBlISiQ+DwZ1Jw9cMh+meKHlC5geggIS8Eo6Qw== X-Received: by 2002:a05:6000:2910:b0:3a6:d26a:f0f5 with SMTP id ffacd0b85a97d-3b5f2dc374emr2265403f8f.21.1752240879978; Fri, 11 Jul 2025 06:34:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/36] MAX78000: TRNG Implementation Date: Fri, 11 Jul 2025 14:34:01 +0100 Message-ID: <20250711133429.1423030-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241251618116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit implements the True Random Number Generator for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-9-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/misc/max78000_gcr.h | 1 + include/hw/misc/max78000_trng.h | 35 ++++++++ hw/misc/max78000_gcr.c | 6 ++ hw/misc/max78000_trng.c | 139 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + 7 files changed, 186 insertions(+) create mode 100644 include/hw/misc/max78000_trng.h create mode 100644 hw/misc/max78000_trng.c diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h index f04c8a3ee7b..23ddf0885b9 100644 --- a/include/hw/misc/max78000_gcr.h +++ b/include/hw/misc/max78000_gcr.h @@ -123,6 +123,7 @@ struct Max78000GcrState { DeviceState *uart0; DeviceState *uart1; DeviceState *uart2; + DeviceState *trng; =20 }; =20 diff --git a/include/hw/misc/max78000_trng.h b/include/hw/misc/max78000_trn= g.h new file mode 100644 index 00000000000..c5a8129b6a0 --- /dev/null +++ b/include/hw/misc/max78000_trng.h @@ -0,0 +1,35 @@ +/* + * MAX78000 True Random Number Generator + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_TRNG_H +#define HW_MAX78000_TRNG_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_MAX78000_TRNG "max78000-trng" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000TrngState, MAX78000_TRNG) + +#define CTRL 0 +#define STATUS 4 +#define DATA 8 + +#define RND_IE (1 << 1) + +struct Max78000TrngState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t data; + + qemu_irq irq; +}; + +#endif diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c index 8c282f3916f..5916ee615a9 100644 --- a/hw/misc/max78000_gcr.c +++ b/hw/misc/max78000_gcr.c @@ -14,6 +14,7 @@ #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_trng.h" #include "hw/misc/max78000_gcr.h" =20 =20 @@ -157,6 +158,9 @@ static void max78000_gcr_write(void *opaque, hwaddr add= r, if (val & UART0_RESET) { device_cold_reset(s->uart0); } + if (val & TRNG_RESET) { + device_cold_reset(s->trng); + } /* TODO: As other devices are implemented, add them here */ break; =20 @@ -257,6 +261,8 @@ static const Property max78000_gcr_properties[] =3D { TYPE_MAX78000_UART, DeviceState*), DEFINE_PROP_LINK("uart2", Max78000GcrState, uart2, TYPE_MAX78000_UART, DeviceState*), + DEFINE_PROP_LINK("trng", Max78000GcrState, trng, + TYPE_MAX78000_TRNG, DeviceState*), }; =20 static const MemoryRegionOps max78000_gcr_ops =3D { diff --git a/hw/misc/max78000_trng.c b/hw/misc/max78000_trng.c new file mode 100644 index 00000000000..ecdaef53b6c --- /dev/null +++ b/hw/misc/max78000_trng.c @@ -0,0 +1,139 @@ +/* + * MAX78000 True Random Number Generator + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_trng.h" +#include "qemu/guest-random.h" + +static uint64_t max78000_trng_read(void *opaque, hwaddr addr, + unsigned int size) +{ + uint32_t data; + + Max78000TrngState *s =3D opaque; + switch (addr) { + case CTRL: + return s->ctrl; + + case STATUS: + return 1; + + case DATA: + /* + * When interrupts are enabled, reading random data should cause a + * new interrupt to be generated; since there's always a random nu= mber + * available, we could qemu_set_irq(s->irq, s->ctrl & RND_IE). Bec= ause + * of how trng_write is set up, this is always a noop, so don't + */ + qemu_guest_getrandom_nofail(&data, sizeof(data)); + return data; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + } + return 0; +} + +static void max78000_trng_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000TrngState *s =3D opaque; + uint32_t val =3D val64; + switch (addr) { + case CTRL: + /* TODO: implement AES keygen */ + s->ctrl =3D val; + + /* + * This device models random number generation as taking 0 time. + * A new random number is always available, so the condition for t= he + * RND interrupt is always fulfilled; we can just set irq to 1. + */ + if (val & RND_IE) { + qemu_set_irq(s->irq, 1); + } else{ + qemu_set_irq(s->irq, 0); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + } +} + +static void max78000_trng_reset_hold(Object *obj, ResetType type) +{ + Max78000TrngState *s =3D MAX78000_TRNG(obj); + s->ctrl =3D 0; + s->status =3D 0; + s->data =3D 0; +} + +static const MemoryRegionOps max78000_trng_ops =3D { + .read =3D max78000_trng_read, + .write =3D max78000_trng_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription max78000_trng_vmstate =3D { + .name =3D TYPE_MAX78000_TRNG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000TrngState), + VMSTATE_UINT32(status, Max78000TrngState), + VMSTATE_UINT32(data, Max78000TrngState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_trng_init(Object *obj) +{ + Max78000TrngState *s =3D MAX78000_TRNG(obj); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_trng_ops, s, + TYPE_MAX78000_TRNG, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_trng_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + rc->phases.hold =3D max78000_trng_reset_hold; + dc->vmsd =3D &max78000_trng_vmstate; + +} + +static const TypeInfo max78000_trng_info =3D { + .name =3D TYPE_MAX78000_TRNG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000TrngState), + .instance_init =3D max78000_trng_init, + .class_init =3D max78000_trng_class_init, +}; + +static void max78000_trng_register_types(void) +{ + type_register_static(&max78000_trng_info); +} + +type_init(max78000_trng_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a96349ee118..c7aae4c9e76 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -369,6 +369,7 @@ config MAX78000_SOC select MAX78000_ICC select MAX78000_UART select MAX78000_GCR + select MAX78000_TRNG =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fde2266b8fc..dd6a6e54dad 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -53,6 +53,9 @@ config MAX78000_GCR config MAX78000_ICC bool =20 +config MAX78000_TRNG + bool + config MOS6522 bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 283d06dad4d..c7c57d924bf 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -72,6 +72,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( )) system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) +system_ss.add(when: 'CONFIG_MAX78000_TRNG', if_true: files('max78000_trng.= c')) system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm_clk.c', 'npcm_gcr.c', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241272; cv=none; d=zohomail.com; s=zohoarc; b=dqef5uTvAWrgovvdUZPSf1w82dSKr5235hnm+gva5QM+gE/NgTjlX8ZMpinRx0ChVFmH9onXeYCsXkou6iZmsxFj/BmxDilcOu1k9AIrRKogOnNpqiD7q10u8CUJoCzPvKuZYE1HokYDDDfgnuT90mxDxX7uhjivqj2tC4i+nG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241272; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xLvUOEistdyulnFrRYxEkwmXouibdyACcWmS4j+YWEc=; b=YZk7eqbyxYIRDzaN3Kvfq87t1bfs4v/Y98gv8Err3hTvX690g+KjH/ONdgdHF1afNgI05zIKJ8DjRLxV7MOZ/2NiqXK6NIyGIbaPdIF2RrVvrskqsxHL2L0uD6+UiCZzfgKav3Tuq3vCcwENC22g89Bzo0cJx9yFsGajOVBlvxU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241272416654.9306729852199; Fri, 11 Jul 2025 06:41:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuf-0005Z8-Dn; Fri, 11 Jul 2025 09:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtk-0004Og-D8 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:47 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDti-0002zz-K7 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:44 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-450cb2ddd46so12433155e9.2 for ; Fri, 11 Jul 2025 06:34:42 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240881; x=1752845681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xLvUOEistdyulnFrRYxEkwmXouibdyACcWmS4j+YWEc=; b=ja3UQ+2DN2Y2Hpp93fUNdVoUizYLASkB6v9zpMB8szzGBgzkjVL3MOLnz9gKxV++8u jkBIbvoBupVEmrVWQfTkLPFCz80L9r/wFqccpSIsMCgl6bdgE3HzkmAPp4nZbJQZ2t7z DHvpWDCL81I8OSCXYesosEIwnLwdkG6DGOl3D1dFXdhxAFvs663k3cEdjnKjqqoE8LpS ixSg1vNK/oQWfN7+g9wUOIAVYoFtG4wFujVUZQoRTMBl2qDIZdEB2QgZb5gOByUQK0Ti GWGdmXR/K943efuNIZSQ5+Co3/+t452cbUZV12N76ZlYLmTE8ENGstBvOg7qq5RngzJS JDAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240881; x=1752845681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xLvUOEistdyulnFrRYxEkwmXouibdyACcWmS4j+YWEc=; b=LNTPJgsztYozzwDKZUhAqS9JWiI9SemDD2LqSYP7hh5E0ssVCpyV0eVP1Srv1kjMeX BAwKXJjN2Ei7Gb3bs1DlP85Ilo/HbJltdL9MivtGbxyNp0Op35mYD68Zt96kqMvXBYqP 3lOAISpU+2vZBlTjgVRki9jT0SIWcTpmBITlR7HYWyX0w0aRKAUmwfyVcBlRQm0iJn+f h9AwVbSGnVx4PdsaEz5jHY162aJmT5xY8GS5Bi6Yjyd/4Vb5ItQO+ATwbqvDbKD8pBEf Y7UklIIX1L6BaUEGSKncE71RL19LEQJiLEhYhW421jMUosKH5DfGY6bz2VoXNuQc8Zsy usfg== X-Gm-Message-State: AOJu0Yw9Ciq6AY90D67+epRNajnsg3BWdXWafdKy4Vg7RTDmZTlfMSEI 5QU2IOkgQ8zNdnsuvvm2j476zQx0H3eI29Vweti87T9ETFCLwyWdZNLawNIs2oUJs8U3f1Ih8vF pmz5i X-Gm-Gg: ASbGncs6L+Srph6MNRsrKoonhxOSLwsIZAqjiH1//vDbJLL7l5l/Ph6H1ONUYQqX6IM 47ZC9HBMzh6t045TDvQxvcXpX61BhpNE4DvcyYLsHJDoryjPK1MLXWceDB88mIY60+uHyP8Vudt HXKv+XdPK1V15WlmWOK0Zx5Lt0ZMCB9rXqO824DENWrXqBDbwTDGH1UKyQI8sI57+s9P676CgU1 G42v6ZswOi12dxpK59eVUblNcOpGfVV3b9WkYY0Da/RDsD84Zhu20t+GR9ksFi4h5FUPzg+872C 1UNYkMaJRc2p7nn4cLh/YZMF1tlyFWbX/Mci+HeMsWOpRp4v3HBqdhl2vVuYVNIqrqkggMRgvj6 OwLk/TbDxP/16S2nFyz9RhlpE9KnD X-Google-Smtp-Source: AGHT+IESU2ZBjATExqSFUm/Ml1xt8dlMCVCp8VZM03IvxhPolsaTEv5+F1YHqYrX+qflbJ9v5R4YLg== X-Received: by 2002:a05:6000:2dc2:b0:3a4:f50b:ca2 with SMTP id ffacd0b85a97d-3b5f187591bmr3088907f8f.8.1752240880958; Fri, 11 Jul 2025 06:34:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/36] MAX78000: Add TRNG to SOC Date: Fri, 11 Jul 2025 14:34:02 +0100 Message-ID: <20250711133429.1423030-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241273757116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit adds TRNG to max78000_soc Signed-off-by: Jackson Donaldson Message-id: 20250704223239.248781-10-jcksn@duck.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 2 ++ hw/arm/max78000_soc.c | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 919aca0855f..528598cfcbe 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -14,6 +14,7 @@ #include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" +#include "hw/misc/max78000_trng.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -39,6 +40,7 @@ struct MAX78000State { Max78000GcrState gcr; Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; + Max78000TrngState trng; =20 Clock *sysclk; }; diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 45c60883121..3f2069fb039 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -43,6 +43,8 @@ static void max78000_soc_initfn(Object *obj) TYPE_MAX78000_UART); } =20 + object_initialize_child(obj, "trng", &s->trng, TYPE_MAX78000_TRNG); + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -124,6 +126,13 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) max78000_uart_irq[i= ])); } =20 + dev =3D DEVICE(&s->trng); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x4004d000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 4)= ); + + object_property_set_link(OBJECT(gcrdev), "trng", OBJECT(dev), &err); + dev =3D DEVICE(&s->gcr); sysbus_realize(SYS_BUS_DEVICE(dev), errp); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); @@ -166,7 +175,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("semaphore", 0x4003e000, 0x1000= ); =20 create_unimplemented_device("spi1", 0x40046000, 0x2000= ); - create_unimplemented_device("trng", 0x4004d000, 0x1000= ); create_unimplemented_device("i2s", 0x40060000, 0x1000= ); create_unimplemented_device("lowPowerControl", 0x40080000, 0x400); create_unimplemented_device("gpio2", 0x40080400, 0x200); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240922; cv=none; d=zohomail.com; s=zohoarc; b=I/ePdYPUylpapc/1viA3sR++N+mLZOXCrkjMHRSrPDwjMTDVwXQVQpFmMz1O3rFyWwwhggX9UgBDyEGe5C7pvkKxSdrNUas70tog1sL8NXPifPWetfP1HMLFxD5Kj8O4fZe2T05hDpmTeJZmQFa4s0wW71HrSsLgKDTI8Ue3Ef0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240922; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VtWNl16YmmRFqGhXR8hej2yTFeJyM8lzLKVOg5We2zM=; b=HT4LqnuuQy1Tqb4/loVvQtGYwxU/yYkIXwKKE393B36Rwj0bpCqYbT4GUZIlXzKTv9wsC8XZYd6VZLI1z7A/BGFR/SpXAJ4T80S3fGYUfoltHu9GEolwLcu6BnozaA9/dQPcyIF1N4sbvljCzCg3DYNVNddlSRY1PvMHN77wbHU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17522409226981005.7976316951417; Fri, 11 Jul 2025 06:35:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDtz-0004Th-7Z; Fri, 11 Jul 2025 09:35:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtm-0004P5-Ni for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:47 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtj-00030f-V8 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:46 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-451d6ade159so16191075e9.1 for ; Fri, 11 Jul 2025 06:34:43 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240882; x=1752845682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VtWNl16YmmRFqGhXR8hej2yTFeJyM8lzLKVOg5We2zM=; b=UwinwaStAHS5f8RXpRXpVnH4mNDxKXh+KZfpz1Nt4fDmFk3iDA/0GATNjmfY3YCUcR a2n2xpMkjqqfSZhtSa1n8ETuwRprxHdz0k+ngRO/pro3fPijY2rkV7huv5K2a71me4JK 7BuUrzr1u4w8acMW3ptPUpofZLnPov4J1o/c5nEiIDuiMYQad4AEL2nZ2vnXZnfXY2UV +jsyCzE8FX3hll5CrHg9qCKhAp7eKtqclPgHthtX5lgIaVWkUzC8ELA8cxdfqTiA92SP 5qxUHFfsq5b+WWUPTFWCw/7rGCnsDoSBiayfvBAxvakv72JG/QwiG+CMLBC5qg1n1lsa usEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240882; x=1752845682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VtWNl16YmmRFqGhXR8hej2yTFeJyM8lzLKVOg5We2zM=; b=AfIGx5sz6cFN13Ge0ncmgrz3IF3UDrhSL25rGfUtXgfkbE/ziMBzarxxFAJ18BxN6w 1r/8565uQQnN/NAAeHCzNFwh/VrT35ch+vWdrjnNMIbFR02S4plg6yrSw9S5lNai3P1W lJ2uryUxh0E3ocp4HOS+r22HhZOz2K0D/0AsR325PPGa1v0c/kXDppAdryIsDQP8cw7f pSWz28nDOQnbMDzX3uGc5vJUNa7dgQQrwe6TSPFg1guyF46dgrV5RI9NKvbJEVpJcBGL Makc9uoVWBWdFxnNcQPpaeLtZ4OTLPKRlnr1bDctTHlVvLS1ZUmwO+b2dYNvINx0kGeI TfyA== X-Gm-Message-State: AOJu0YwnwoJM5PIb0LxFGf2tIE+BpWut+uHjeImW9Hvk66em4hETklQ0 LH0dCsBd98sPm0oA3q8R+2ZbA+UQWd9gWncDwgKz5mXSe10jFf0PIr4T06PZzTXxpXBUn1aSTPQ o+Lc+ X-Gm-Gg: ASbGncuYNjc6oFl4fHCwTKg6NRavhnt39ohYacKRW9XX7DtScQnATGHJygJ6ZinupnJ Bi/x6GLyHSW4H4LOHaL/CnEiU4+7o3D7tcFMNsk9NPFc/Oo4+f4DAwTo520pR5qz7Y0JJj8pKdY bK4aNijZDDDDHgAISgmVhoW+3rO497qiEfk+OFpC34h+bp7k/ZChZiHvV3WYpylfdCmAKLTuyyH Pu8ES9tOER2r34Abc/tZL7u/lVdSu6MWg8XY/VnfuuV0xxQFH17IlubfwNUkhHy2+fXPH5qx/ke fe4N/u9XudcBlEjEYgnagzgf+BzA4ADu9w1Ti5MAdpYtWdrADKNQ7tz7trF6l3mwCO5/DW6DQmS Z/fGThbSE7KEIRTyQX0Aqe+/JW34q X-Google-Smtp-Source: AGHT+IHQR9yvftpOusBc/Tyrw6y1gDCNlatYlmJZ/nfS7y4QRkWMmWy5E3F0P5+uu1qw64xM9qmqvA== X-Received: by 2002:a05:600c:c4b8:b0:43d:82c:2b11 with SMTP id 5b1f17b1804b1-454f4253429mr24271775e9.23.1752240882278; Fri, 11 Jul 2025 06:34:42 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/36] MAX78000: AES implementation Date: Fri, 11 Jul 2025 14:34:03 +0100 Message-ID: <20250711133429.1423030-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240923413116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit implements AES for the MAX78000 Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-11-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/misc/max78000_aes.h | 68 ++++++++++ include/hw/misc/max78000_gcr.h | 1 + hw/misc/max78000_aes.c | 223 +++++++++++++++++++++++++++++++++ hw/misc/max78000_gcr.c | 6 + hw/arm/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + 7 files changed, 303 insertions(+) create mode 100644 include/hw/misc/max78000_aes.h create mode 100644 hw/misc/max78000_aes.c diff --git a/include/hw/misc/max78000_aes.h b/include/hw/misc/max78000_aes.h new file mode 100644 index 00000000000..407c45ef61e --- /dev/null +++ b/include/hw/misc/max78000_aes.h @@ -0,0 +1,68 @@ +/* + * MAX78000 AES + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HW_MAX78000_AES_H +#define HW_MAX78000_AES_H + +#include "hw/sysbus.h" +#include "crypto/aes.h" +#include "qom/object.h" + +#define TYPE_MAX78000_AES "max78000-aes" +OBJECT_DECLARE_SIMPLE_TYPE(Max78000AesState, MAX78000_AES) + +#define CTRL 0 +#define STATUS 4 +#define INTFL 8 +#define INTEN 0xc +#define FIFO 0x10 + +#define KEY_BASE 0x400 +#define KEY_END 0x420 + +/* CTRL */ +#define TYPE (1 << 9 | 1 << 8) +#define KEY_SIZE (1 << 7 | 1 << 6) +#define OUTPUT_FLUSH (1 << 5) +#define INPUT_FLUSH (1 << 4) +#define START (1 << 3) + +#define AES_EN (1 << 0) + +/* STATUS */ +#define OUTPUT_FULL (1 << 4) +#define OUTPUT_EMPTY (1 << 3) +#define INPUT_FULL (1 << 2) +#define INPUT_EMPTY (1 << 1) +#define BUSY (1 << 0) + +/* INTFL*/ +#define DONE (1 << 0) + +struct Max78000AesState { + SysBusDevice parent_obj; + + MemoryRegion mmio; + + uint32_t ctrl; + uint32_t status; + uint32_t intfl; + uint32_t inten; + uint32_t data_index; + uint8_t data[16]; + + uint8_t key[32]; + AES_KEY internal_key; + + uint32_t result_index; + uint8_t result[16]; + + + qemu_irq irq; +}; + +#endif diff --git a/include/hw/misc/max78000_gcr.h b/include/hw/misc/max78000_gcr.h index 23ddf0885b9..d5858a40f3b 100644 --- a/include/hw/misc/max78000_gcr.h +++ b/include/hw/misc/max78000_gcr.h @@ -124,6 +124,7 @@ struct Max78000GcrState { DeviceState *uart1; DeviceState *uart2; DeviceState *trng; + DeviceState *aes; =20 }; =20 diff --git a/hw/misc/max78000_aes.c b/hw/misc/max78000_aes.c new file mode 100644 index 00000000000..0bfb2f02b5b --- /dev/null +++ b/hw/misc/max78000_aes.c @@ -0,0 +1,223 @@ +/* + * MAX78000 AES + * + * Copyright (c) 2025 Jackson Donaldson + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "hw/misc/max78000_aes.h" +#include "crypto/aes.h" + +static void max78000_aes_set_status(Max78000AesState *s) +{ + s->status =3D 0; + if (s->result_index >=3D 16) { + s->status |=3D OUTPUT_FULL; + } + if (s->result_index =3D=3D 0) { + s->status |=3D OUTPUT_EMPTY; + } + if (s->data_index >=3D 16) { + s->status |=3D INPUT_FULL; + } + if (s->data_index =3D=3D 0) { + s->status |=3D INPUT_EMPTY; + } +} + +static uint64_t max78000_aes_read(void *opaque, hwaddr addr, + unsigned int size) +{ + Max78000AesState *s =3D opaque; + switch (addr) { + case CTRL: + return s->ctrl; + + case STATUS: + return s->status; + + case INTFL: + return s->intfl; + + case INTEN: + return s->inten; + + case FIFO: + if (s->result_index >=3D 4) { + s->intfl &=3D ~DONE; + s->result_index -=3D 4; + max78000_aes_set_status(s); + return ldl_be_p(&s->result[s->result_index]); + } else{ + return 0; + } + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + + } + return 0; +} + +static void max78000_aes_do_crypto(Max78000AesState *s) +{ + int keylen =3D 256; + uint8_t *keydata =3D s->key; + if ((s->ctrl & KEY_SIZE) =3D=3D 0) { + keylen =3D 128; + keydata +=3D 16; + } else if ((s->ctrl & KEY_SIZE) =3D=3D 1 << 6) { + keylen =3D 192; + keydata +=3D 8; + } + + AES_KEY key; + if ((s->ctrl & TYPE) =3D=3D 0) { + AES_set_encrypt_key(keydata, keylen, &key); + AES_set_decrypt_key(keydata, keylen, &s->internal_key); + AES_encrypt(s->data, s->result, &key); + s->result_index =3D 16; + } else if ((s->ctrl & TYPE) =3D=3D 1 << 8) { + AES_set_decrypt_key(keydata, keylen, &key); + AES_set_decrypt_key(keydata, keylen, &s->internal_key); + AES_decrypt(s->data, s->result, &key); + s->result_index =3D 16; + } else{ + AES_decrypt(s->data, s->result, &s->internal_key); + s->result_index =3D 16; + } + s->intfl |=3D DONE; +} + +static void max78000_aes_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + Max78000AesState *s =3D opaque; + uint32_t val =3D val64; + switch (addr) { + case CTRL: + if (val & OUTPUT_FLUSH) { + s->result_index =3D 0; + val &=3D ~OUTPUT_FLUSH; + } + if (val & INPUT_FLUSH) { + s->data_index =3D 0; + val &=3D ~INPUT_FLUSH; + } + if (val & START) { + max78000_aes_do_crypto(s); + } + + /* Hardware appears to stay enabled even if 0 written */ + s->ctrl =3D val | (s->ctrl & AES_EN); + break; + + case FIFO: + assert(s->data_index <=3D 12); + stl_be_p(&s->data[12 - s->data_index], val); + s->data_index +=3D 4; + if (s->data_index >=3D 16) { + s->data_index =3D 0; + max78000_aes_do_crypto(s); + } + break; + + case KEY_BASE ... KEY_END - 4: + stl_be_p(&s->key[(KEY_END - KEY_BASE - 4) - (addr - KEY_BASE)], va= l); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" + HWADDR_PRIx "\n", __func__, addr); + break; + + } + max78000_aes_set_status(s); +} + +static void max78000_aes_reset_hold(Object *obj, ResetType type) +{ + Max78000AesState *s =3D MAX78000_AES(obj); + s->ctrl =3D 0; + s->status =3D 0; + s->intfl =3D 0; + s->inten =3D 0; + + s->data_index =3D 0; + s->result_index =3D 0; + + memset(s->data, 0, sizeof(s->data)); + memset(s->key, 0, sizeof(s->key)); + memset(s->result, 0, sizeof(s->result)); + memset(&s->internal_key, 0, sizeof(s->internal_key)); +} + +static const MemoryRegionOps max78000_aes_ops =3D { + .read =3D max78000_aes_read, + .write =3D max78000_aes_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription vmstate_max78000_aes =3D { + .name =3D TYPE_MAX78000_AES, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(ctrl, Max78000AesState), + VMSTATE_UINT32(status, Max78000AesState), + VMSTATE_UINT32(intfl, Max78000AesState), + VMSTATE_UINT32(inten, Max78000AesState), + VMSTATE_UINT8_ARRAY(data, Max78000AesState, 16), + VMSTATE_UINT8_ARRAY(key, Max78000AesState, 32), + VMSTATE_UINT8_ARRAY(result, Max78000AesState, 16), + VMSTATE_UINT32_ARRAY(internal_key.rd_key, Max78000AesState, 60), + VMSTATE_INT32(internal_key.rounds, Max78000AesState), + VMSTATE_END_OF_LIST() + } +}; + +static void max78000_aes_init(Object *obj) +{ + Max78000AesState *s =3D MAX78000_AES(obj); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &max78000_aes_ops, s, + TYPE_MAX78000_AES, 0xc00); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + +} + +static void max78000_aes_class_init(ObjectClass *klass, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + rc->phases.hold =3D max78000_aes_reset_hold; + dc->vmsd =3D &vmstate_max78000_aes; + +} + +static const TypeInfo max78000_aes_info =3D { + .name =3D TYPE_MAX78000_AES, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Max78000AesState), + .instance_init =3D max78000_aes_init, + .class_init =3D max78000_aes_class_init, +}; + +static void max78000_aes_register_types(void) +{ + type_register_static(&max78000_aes_info); +} + +type_init(max78000_aes_register_types) diff --git a/hw/misc/max78000_gcr.c b/hw/misc/max78000_gcr.c index 5916ee615a9..fbbc92cca32 100644 --- a/hw/misc/max78000_gcr.c +++ b/hw/misc/max78000_gcr.c @@ -15,6 +15,7 @@ #include "hw/qdev-properties.h" #include "hw/char/max78000_uart.h" #include "hw/misc/max78000_trng.h" +#include "hw/misc/max78000_aes.h" #include "hw/misc/max78000_gcr.h" =20 =20 @@ -161,6 +162,9 @@ static void max78000_gcr_write(void *opaque, hwaddr add= r, if (val & TRNG_RESET) { device_cold_reset(s->trng); } + if (val & AES_RESET) { + device_cold_reset(s->aes); + } /* TODO: As other devices are implemented, add them here */ break; =20 @@ -263,6 +267,8 @@ static const Property max78000_gcr_properties[] =3D { TYPE_MAX78000_UART, DeviceState*), DEFINE_PROP_LINK("trng", Max78000GcrState, trng, TYPE_MAX78000_TRNG, DeviceState*), + DEFINE_PROP_LINK("aes", Max78000GcrState, aes, + TYPE_MAX78000_AES, DeviceState*), }; =20 static const MemoryRegionOps max78000_gcr_ops =3D { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c7aae4c9e76..1634e26fcc9 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -370,6 +370,7 @@ config MAX78000_SOC select MAX78000_UART select MAX78000_GCR select MAX78000_TRNG + select MAX78000_AES =20 config RASPI bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index dd6a6e54dad..c27285b47ab 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -47,6 +47,9 @@ config A9SCU config ARM11SCU bool =20 +config MAX78000_AES + bool + config MAX78000_GCR bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index c7c57d924bf..b1d8d8e5d2a 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( 'imx_ccm.c', 'imx_rngc.c', )) +system_ss.add(when: 'CONFIG_MAX78000_AES', if_true: files('max78000_aes.c'= )) system_ss.add(when: 'CONFIG_MAX78000_GCR', if_true: files('max78000_gcr.c'= )) system_ss.add(when: 'CONFIG_MAX78000_ICC', if_true: files('max78000_icc.c'= )) system_ss.add(when: 'CONFIG_MAX78000_TRNG', if_true: files('max78000_trng.= c')) --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241236; cv=none; d=zohomail.com; s=zohoarc; b=L+SF6OM1BArBHdk7rjo9HNeR+kN6ya3ns2SwNLXOBiBY9Mr0WkWlGvbRBGNEbJzl+y69mUAXPQO7fE4gKGJnyQY9hfdt2r7FRDxhqbThj0KJEj/ve+8Ex85r2LbkxM7bl5xwSMEwKCbhHp99omN3uFGxgNDBzY2XW/UHKB48Eys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241236; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=zCEHngMuEKAJlSIQienwre2JI7I+N6ggKt6meJEzMfI=; b=WFsdbXfbaBdgZpyy338yltiG9+X1F4IgI+ck4UhqnTgzVKOgBVciNPZmX87ausgpZWY5PA93HoM2B6hjUzRqdI9OtW21+m0MFlkMUpfH/bZe2WBUIOVAZX3dOhrnWIOJ7OcwkAP5RZ0RONvCnMhoIA1yuv0SA4nzVBHrFtvI+gM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241236865121.91377280205461; Fri, 11 Jul 2025 06:40:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDub-0005RK-2t; Fri, 11 Jul 2025 09:35:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtm-0004P6-PD for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:47 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtk-000312-N8 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:46 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-453643020bdso16147595e9.1 for ; Fri, 11 Jul 2025 06:34:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240883; x=1752845683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zCEHngMuEKAJlSIQienwre2JI7I+N6ggKt6meJEzMfI=; b=EnT1zqo+5WWz9UmA2/Ns/dhG0yWBcxC+t0f3NiAugqFRwQi/6TUDvKBCBsl8kinWID VE6EgIS3nvqpKKm9FjY0FOnbLm+HyOcGWzXzrT6ELFM0NP7UvF+BR4RLS8lt5EGulYS4 akVLQtiWSZXnnnFBEseq5c5TyK2BNdlllQrd4WnTipzHLTcC8NG1XfXEse9Q5WHopnUS gFAUZKf7arXVffXMr75OlnCOV8UUtj47KyNkOJWw/AunkRvLPZDET/7zlxmyvAWejAru uPbZLlvi3+VmjdoGHT8GEDOajTe8lL/VF3fHm//7tIgzHOtnYExoBP/vwiPfY0nBbTad uCtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240883; x=1752845683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zCEHngMuEKAJlSIQienwre2JI7I+N6ggKt6meJEzMfI=; b=SvIgmNA3SlNWs2Yn764c7gF11GzrWBAsk5kquEkkWWzcRMOLMF8da+Z+rsyXV3zLUe P3Octqu0J9jPulW4c+J9YjIvspRLahcJlCq+GKYZNa8Jief2ut/YAZILqIKbmb0jojKB WSnXXJEkjBvGWshwX2mnEmt61VlgOFc1W0b9u3mp/a8Txl7MtngeU9cxbfIFmeOZscon 3m+7s9t9d4G7GsDTKA2OjPP9KJ8AqWfmcHe5zcsCTD1QYE7Bzt//MikyH6SRPlaiXfUW jaN7WW4PRVUgiqMHpcjFqKAc6epyxCZJPKdEUY6aUCt0oiEe+DI4FoTTK4B7XmLU8FbU RWeA== X-Gm-Message-State: AOJu0YxAvPRvJi/HfWxZPinqGlqEZMf8oK+q/4FpUnTrbx3VoKWRyPpE eAODiFzd6Xhb6C0UVjOgyVkplcMv3CVNYmd4ow4ySVZeD//ID/pYP522AkbJRYBsTnm3tvshZOi 2rMpZ X-Gm-Gg: ASbGnctdCMvAAks77mcZg96oDBm5n/fC11b7CJM7oknGPlnAlgWLrD7MhAiqrHWmqxT EAAOf7QDnc6NPJx7VFMWuw5V7/d6PIWECzZW9YlTeRRox01VKXQsbxK+JgldroXNy8fpCFjejh2 1RgatKCgGb1ry4sFrFHb62E4xnLq8q7d3+oF5pgCzk0nkoEB2FjoSLHw5sFJgrP5pwrqwo4Hfh+ C2LhkDFNLT738217LDeCiNt7u5CMA2wv4dFFooe+5E6uKq29k0wsfASF2DMgLv0fyF6Pxzy9Pt9 g/gujsYCbKG2ukPYRkiDLPsjO6PLSjKDyL8gLs6wcbsOa7DqJYASPlreWfaGE6+dpr3NXuT+IZZ luKjHWviFeNjRHDgwtmnQ2WtBgiDY X-Google-Smtp-Source: AGHT+IFw9iz8Ys08C1N3M3LAAbJ7jMt/1HR0hixOL0zF87fHcXhqrVQtz9roarpJ5GgIDNZBbZbSkQ== X-Received: by 2002:a05:600c:628e:b0:43c:fceb:91a with SMTP id 5b1f17b1804b1-454f42814bamr29962765e9.11.1752240883231; Fri, 11 Jul 2025 06:34:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] MAX78000: Add AES to SOC Date: Fri, 11 Jul 2025 14:34:04 +0100 Message-ID: <20250711133429.1423030-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241239284116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This commit adds AES to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell Message-id: 20250704223239.248781-12-jcksn@duck.com Signed-off-by: Peter Maydell --- include/hw/arm/max78000_soc.h | 2 ++ hw/arm/max78000_soc.c | 12 +++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 528598cfcbe..a203079ee9a 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_aes.h" #include "hw/misc/max78000_gcr.h" #include "hw/misc/max78000_icc.h" #include "hw/char/max78000_uart.h" @@ -41,6 +42,7 @@ struct MAX78000State { Max78000IccState icc[MAX78000_NUM_ICC]; Max78000UartState uart[MAX78000_NUM_UART]; Max78000TrngState trng; + Max78000AesState aes; =20 Clock *sysclk; }; diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 3f2069fb039..7f1856f5ba1 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -45,6 +45,8 @@ static void max78000_soc_initfn(Object *obj) =20 object_initialize_child(obj, "trng", &s->trng, TYPE_MAX78000_TRNG); =20 + object_initialize_child(obj, "aes", &s->aes, TYPE_MAX78000_AES); + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -133,6 +135,13 @@ static void max78000_soc_realize(DeviceState *dev_soc,= Error **errp) =20 object_property_set_link(OBJECT(gcrdev), "trng", OBJECT(dev), &err); =20 + dev =3D DEVICE(&s->aes); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40007400); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(armv7m, 5)= ); + + object_property_set_link(OBJECT(gcrdev), "aes", OBJECT(dev), &err); + dev =3D DEVICE(&s->gcr); sysbus_realize(SYS_BUS_DEVICE(dev), errp); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x40000000); @@ -148,9 +157,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("powerSequencer", 0x40006800, 0x400); create_unimplemented_device("miscControl", 0x40006c00, 0x400); =20 - create_unimplemented_device("aes", 0x40007400, 0x400); - create_unimplemented_device("aesKey", 0x40007800, 0x400); - create_unimplemented_device("gpio0", 0x40008000, 0x1000= ); create_unimplemented_device("gpio1", 0x40009000, 0x1000= ); =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240922; cv=none; d=zohomail.com; s=zohoarc; b=VnHu8fpdKdUt3Rqa3QsFGIQw0fmHiYPmDRa9TuLeaPia1I/gumLbozZ0TNyudQrVb35iUtKAIDd9usBC+3dof93awz0KQ2I7FItXyV/UcUSZCCPhrw/m1+uVVwFZi5FGBqHsxerqL+Vtt+NIID9yg+4kmJNA/GXSB8xFmKyt8a0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240922; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jgAVdewJ8pDHlKu4rlqFJIDOTB9PnXtF4nPjiIJFR90=; b=BcrPGsdLmquPN+3Nro919wUsMPpT7Zl542L+QMPk0lU3AkVf18chwDBtldRt2jcQVNV84BxP/RoLkqD0lagIBTb8+dbP7S9GL+rCTKr1ZaxAEHbJ5lXnmoL+aJe50qobzBEglNfvXcg8e5Pn3EPJXieBU48rCRY1ZElPhdvxUzk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240922599276.11392140212877; Fri, 11 Jul 2025 06:35:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuF-0004Xt-0R; Fri, 11 Jul 2025 09:35:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtn-0004P8-Dz for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:48 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtl-00031g-ML for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:47 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-451d7b50815so15572175e9.2 for ; Fri, 11 Jul 2025 06:34:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240884; x=1752845684; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jgAVdewJ8pDHlKu4rlqFJIDOTB9PnXtF4nPjiIJFR90=; b=fdCUyFaQCaBMwdepBChafWPJ61Hw3h4eJF6TyR63paV0PJK5DHlRYQmgnaJbC+sWpl A23Alunt8tqdfuQMnlyczEQkLwb/NRYf4rCnoSoFNYQipPfrMnEyWbVV36bOjY48bFcV ycaBYzb8v7QN5xrADNkk+cBMiz1aBRPm0gwnESKM2C70ojetp374KKX7iweA5NMKJstm TjAelLr7yHTnUhKkd1uLAlxagDwsd7TkkkccsJaU+x7GBkxkrBbqVwRLHPr7CILyq/qH YQnF65RCiI4HbxnMs0FdhtqBZorftd/I0GDUBVkQEh3RwpjYveFuiMof+mPwCmPAqsMu C9Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240884; x=1752845684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jgAVdewJ8pDHlKu4rlqFJIDOTB9PnXtF4nPjiIJFR90=; b=R+QFYMPECJE+SNnewxbm7zUnJ+BBf5DZn4GjuRrFrAk6z+MFdVwnEVDtSMuFhaVoIl ZxeyOuvxZgC1+uq9/A8rEx+hCTnrnOtw5Xf/vyLZazFCvgygYvmXCfdK5FQuNprXITMz 0liUqEKQL3qEF64a0JA7X71AnVDm4fTMjqIHf/ztVEWzs9I5HhBOeol5Rts96lu/AcrU /ULhT5VRbZ4jedsNhHojaYTBkX68UbzVl5TPvkswlUVsVLF2x3d+MIQtd5xzJGTujegV +ghYlaLtgLKcDpfAk+6eR0HZOTwf3VwFk3AF01WOeflWcHNbUHuLpi4mmpd/quc8qNAj 8HRQ== X-Gm-Message-State: AOJu0Yz+Nz1/B+ysn4JCezRi3wtRT90Dn5Bn/R4PCgF603UhF3YXPkzV K4uUAmGZfCvNkg+RL59oLwUuIqts9NCsz0T5idXTd0JWQW/FGCodL1hBS9wWMRBaL7VQzdLnHof /DAmg X-Gm-Gg: ASbGncsV8GB51uUWdzQV39e1jXwpcFy4+7WzzYF/QRqvmS2Sc1c4uteOQMgh0giW9Z3 B41dBai417VNpsEKmEpNg4KzdvoZ7tu8/FKQ6P0+g7tMrm+3cQcfyh65e4Fe3yPT6E+u2ckwve3 VBzKcFNtepszWzf/au6IY+m6ICWch8dcmv2aROlfKcfCPMjygiyhJl52n3E9rj1wp0R+r4gxkc0 X85Ewt1bmnnjWo4GuWnyECv5JYs9MyQllouZ5jNP19bJMxrpFRZU1/ZTbg8sK/pm4CQZUjt8ebz lyauBpIuGAGrA4jJcmhFnFRigpunQGIDoicNNJMCaPBXVcxpXWeRFug0R6h9eoEDi9xr8EXQngB mfEvdqkN4wAQtmNJKypARh2oj6bVn X-Google-Smtp-Source: AGHT+IFWstTJlC0XjzSPW9njkSxKiUqpISxufyhLCs1/s1sQ87P91tylBaVXeowsiN1FgL9pX3shUw== X-Received: by 2002:a05:600c:c09c:b0:450:d012:df85 with SMTP id 5b1f17b1804b1-45526f25a77mr22769485e9.18.1752240884174; Fri, 11 Jul 2025 06:34:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/36] hw/cxl-host: Add an index field to CXLFixedMemoryWindow Date: Fri, 11 Jul 2025 14:34:05 +0100 Message-ID: <20250711133429.1423030-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240923182116600 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron To enable these to be found in a fixed order, that order needs to be known. This will later be used to sort a list of these structures so that address map and ACPI table entries are predictable. Tested-by: Li Zhijian Reviewed-by: Li Zhijian Reviewed-by: Fan Ni Reviewed-by: Eric Auger Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Message-id: 20250703104110.992379-2-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell --- include/hw/cxl/cxl.h | 1 + hw/cxl/cxl-host.c | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 75e47b68644..b2bcce7ed60 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -27,6 +27,7 @@ typedef struct PXBCXLDev PXBCXLDev; =20 typedef struct CXLFixedWindow { + int index; uint64_t size; char **targets; PXBCXLDev *target_hbs[16]; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index e0101631744..b7aa429ddf4 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -24,13 +24,15 @@ =20 static void cxl_fixed_memory_window_config(CXLState *cxl_state, CXLFixedMemoryWindowOptions *ob= ject, - Error **errp) + int index, Error **errp) { ERRP_GUARD(); g_autofree CXLFixedWindow *fw =3D g_malloc0(sizeof(*fw)); strList *target; int i; =20 + fw->index =3D index; + for (target =3D object->targets; target; target =3D target->next) { fw->num_targets++; } @@ -325,14 +327,15 @@ static void machine_set_cfmw(Object *obj, Visitor *v,= const char *name, CXLState *state =3D opaque; CXLFixedMemoryWindowOptionsList *cfmw_list =3D NULL; CXLFixedMemoryWindowOptionsList *it; + int index; =20 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp); if (!cfmw_list) { return; } =20 - for (it =3D cfmw_list; it; it =3D it->next) { - cxl_fixed_memory_window_config(state, it->value, errp); + for (it =3D cfmw_list, index =3D 0; it; it =3D it->next, index++) { + cxl_fixed_memory_window_config(state, it->value, index, errp); } state->cfmw_list =3D cfmw_list; } --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240928; cv=none; d=zohomail.com; s=zohoarc; b=eRo8MhFlgMVonJh0W8dyqzekW4EeuNABdn4R0ySI1DIqM11jUHx/e/15uzPQJV/kyIyDfdOBfFsNXVkSDI3qicOHOofBW5U/YIyIM54U3/BN+okdfNrYoH2fL7HhOAusyjALosYeQWyMhu9hVlitN6xXvyrDIJo0PKpFDm3OWkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240928; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8z9AtDLYqnn49RbQF2PUqhNNRXhINMXFbAw84qOvI+Y=; b=ikkZt3H6xke/lULECyevpVXOV+G98sizcMYKAgep/qKRPih7tBCJlFGrbwCtAsoVcHyZEXKBr7vDkQtvbzq9Kltt4yC5Lv/9p/6HdMwsurGJ3TWKyDOtX7YvWdJcLNEnGVutxtvcb3Iywkit30yS3xEQRalVa9dIjjua3xZK4Cg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240928327399.6075417573494; Fri, 11 Jul 2025 06:35:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuH-0004lo-Ku; Fri, 11 Jul 2025 09:35:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtp-0004Px-N4 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:51 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtn-00032D-2P for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:49 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4550709f2c1so4524325e9.3 for ; Fri, 11 Jul 2025 06:34:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240885; x=1752845685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8z9AtDLYqnn49RbQF2PUqhNNRXhINMXFbAw84qOvI+Y=; b=fwjlVYjRxc8VlTpE5DBJkWu5MGLyiXxUelHvdEo4h1T9VqyCkhTS+axCNEusXb+4zO 8lH/P9PDvLlvY/n5Tm1TOGElcOfK8h1X++6E+wlUuMTu/3g8VgI3lqsler4S8OiZXMRK gs/hPUfcc16yo+BQJh9P4bgRX3RdoEMIfGmpLoQlF/YTkgZgp6zSNbtimdV0iC3bzyYW 5tXLnHbj7eZHmGVz/R43h3SlfvVTb0HbC/rDSpiPEzjFjPFqtZ9XHoDP1ebTu+/3Vxdj zNBg//WzZYcEJiiH9IhJjb/+1e/cl/ktB8CfJ8YjpgHIk8en1bi3rRGH2vM3th7lqkDr rwXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240885; x=1752845685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8z9AtDLYqnn49RbQF2PUqhNNRXhINMXFbAw84qOvI+Y=; b=ozGfjhQtAlw1rYB4yuOgLvKHdb/lxrOwyh3ynW5e/ee8UeO38ArSecWn3Q5RjYZQLC ImTsjaFgGRFJ5zJk209F38Y1QgxoXziyOCngC/umWq/spnztbSmJ3EqgFFIf1ySETBEe 20p7eL28bMog65Jnzl+hIdLSxannI9F46cgtQ41W67d08SAU+LYpNYI0DYt+mBWRceH8 8eegggXRixG2jl1Gc1tpRX6VKpETlZop4KpqNgmLQdhnCqZF5FEXDJAmT/Tf2sq9bS3g eMILTFjByPpANLqjh8U65YzlBppNYzPanHZf8ixmwgJ5YW1PUTvKCP32jCNq3+vnGUAw QcfQ== X-Gm-Message-State: AOJu0Yzb9BVlgKiGP3dd9xwYWyDInaRvCapfMXapIb/cUkZtSa0YHGRZ wcdLyrfUfSMCcyWkLehSVvHDlcfQoCncT73yBmnXolhwBIwswAvkH9/iwS+lwA+cjLwSidbEVRD kXm91 X-Gm-Gg: ASbGncuoFAmEo+fmMR/5Yxtqk1Q2MqyOFTrc/UZnUBlvYdTlGkWBAsq7iYVV+uGrM3D 3RLGL2tuKRfDchRCiOhxgwjfhVA21yRHBUvf0mMr8sKYrFO+gVql3mCxu29q3LP8ulf7gbqgAhl Lt/RJlqdsVk9Il+06+LsxPURLIU/s812xybS3qgmuKoVD/W1Qz6+GgNaMlsBgNRNtAcEbYznp0z SgYxSpOQeJAtUDeYYp3MeHyK5JccPf84+L7UYq2470+vCFuQ1sQM2ATo7d2dDt5zwHPzPnQTScS rbyoYtRW0OMyS0MAMQII4PTHMeC+FdBam/nALQ2aczL1TaV+71/JUfyvd9eGst/xVPXzA1JCbi5 eoH5YOPTJpSaxgrablrdKL5NhgNKsfoe/q69uxHU= X-Google-Smtp-Source: AGHT+IFi3VaeWODir7Dt9BsMWjv/Jvo4C/4gHUQSxvk6g6GpMPoNCZYTcynbj/CzMbtloskCqtzS+g== X-Received: by 2002:a05:600c:8b26:b0:440:6a37:be0d with SMTP id 5b1f17b1804b1-454ec26d101mr32138095e9.15.1752240885163; Fri, 11 Jul 2025 06:34:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/36] hw/cxl: Make the CXL fixed memory windows devices. Date: Fri, 11 Jul 2025 14:34:06 +0100 Message-ID: <20250711133429.1423030-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240929513116600 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Previously these somewhat device like structures were tracked using a list in the CXLState in each machine. This is proving restrictive in a few cases where we need to iterate through these without being aware of the machine type. Just make them sysbus devices. Restrict them to not user created as they need to be visible to early stages of machine init given effects on the memory map. This change both simplifies state tracking and enables features needed for performance optimization and hotness tracking by making it possible to retrieve the fixed memory window on actions elsewhere in the topology. In some cases the ordering of the Fixed Memory Windows matters. For those utility functions provide a GSList sorted by the window index. This ensures that we get consistency across: - ordering in the command line - ordering of the host PA ranges - ordering of ACPI CEDT structures describing the CFMWS. Other aspects don't have this constraint. For those direct iteration of the underlying hash structures is fine. In the setup path for the memory map in pc_memory_init() split the operations into two calls. The first, cxl_fmws_set_mmemap(), loops over fixed memory windows in order and assigns their addresses. The second, cxl_fmws_update_mmio() actually sets up the mmio for each window. This is obviously less efficient than a single loop but this split design is needed to put the logic in two different places in the arm64 support and it is not a hot enough path to justify an x86 only implementation. Reviewed-by: Li Zhijian Tested-by: Li Zhijian Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Message-id: 20250703104110.992379-3-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell --- include/hw/cxl/cxl.h | 4 +- include/hw/cxl/cxl_host.h | 5 +- hw/acpi/cxl.c | 76 +++++++++-------- hw/cxl/cxl-host-stubs.c | 7 +- hw/cxl/cxl-host.c | 167 +++++++++++++++++++++++++++++++------- hw/i386/pc.c | 50 +++++------- 6 files changed, 214 insertions(+), 95 deletions(-) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index b2bcce7ed60..de66ab8c354 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -27,6 +27,7 @@ typedef struct PXBCXLDev PXBCXLDev; =20 typedef struct CXLFixedWindow { + SysBusDevice parent_obj; int index; uint64_t size; char **targets; @@ -38,12 +39,13 @@ typedef struct CXLFixedWindow { MemoryRegion mr; hwaddr base; } CXLFixedWindow; +#define TYPE_CXL_FMW "cxl-fmw" +OBJECT_DECLARE_SIMPLE_TYPE(CXLFixedWindow, CXL_FMW) =20 typedef struct CXLState { bool is_enabled; MemoryRegion host_mr; unsigned int next_mr_idx; - GList *fixed_windows; CXLFixedMemoryWindowOptionsList *cfmw_list; } CXLState; =20 diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index c9bc9c7c500..cd3c368c86a 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -14,8 +14,11 @@ #define CXL_HOST_H =20 void cxl_machine_init(Object *obj, CXLState *state); -void cxl_fmws_link_targets(CXLState *stat, Error **errp); +void cxl_fmws_link_targets(Error **errp); void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp); +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr); +void cxl_fmws_update_mmio(void); +GSList *cxl_fmws_get_all_sorted(void); =20 extern const MemoryRegionOps cfmws_ops; =20 diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index 9cd7905ea25..75d5b30bb8b 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -22,6 +22,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/mem/memory-device.h" #include "hw/acpi/acpi.h" #include "hw/acpi/aml-build.h" @@ -135,55 +136,52 @@ static void cedt_build_chbs(GArray *table_data, PXBCX= LDev *cxl) * Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory * interleaving. */ -static void cedt_build_cfmws(GArray *table_data, CXLState *cxls) +static void cedt_build_cfmws(CXLFixedWindow *fw, Aml *cedt) { - GList *it; + GArray *table_data =3D cedt->buf; + int i; =20 - for (it =3D cxls->fixed_windows; it; it =3D it->next) { - CXLFixedWindow *fw =3D it->data; - int i; + /* Type */ + build_append_int_noprefix(table_data, 1, 1); =20 - /* Type */ - build_append_int_noprefix(table_data, 1, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 1); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 1); + /* Record Length */ + build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); =20 - /* Record Length */ - build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 4); + /* Base HPA */ + build_append_int_noprefix(table_data, fw->mr.addr, 8); =20 - /* Base HPA */ - build_append_int_noprefix(table_data, fw->mr.addr, 8); + /* Window Size */ + build_append_int_noprefix(table_data, fw->size, 8); =20 - /* Window Size */ - build_append_int_noprefix(table_data, fw->size, 8); + /* Host Bridge Interleave Ways */ + build_append_int_noprefix(table_data, fw->enc_int_ways, 1); =20 - /* Host Bridge Interleave Ways */ - build_append_int_noprefix(table_data, fw->enc_int_ways, 1); + /* Host Bridge Interleave Arithmetic */ + build_append_int_noprefix(table_data, 0, 1); =20 - /* Host Bridge Interleave Arithmetic */ - build_append_int_noprefix(table_data, 0, 1); + /* Reserved */ + build_append_int_noprefix(table_data, 0, 2); =20 - /* Reserved */ - build_append_int_noprefix(table_data, 0, 2); + /* Host Bridge Interleave Granularity */ + build_append_int_noprefix(table_data, fw->enc_int_gran, 4); =20 - /* Host Bridge Interleave Granularity */ - build_append_int_noprefix(table_data, fw->enc_int_gran, 4); + /* Window Restrictions */ + build_append_int_noprefix(table_data, 0x0f, 2); =20 - /* Window Restrictions */ - build_append_int_noprefix(table_data, 0x0f, 2); /* No restrictions= */ + /* QTG ID */ + build_append_int_noprefix(table_data, 0, 2); =20 - /* QTG ID */ - build_append_int_noprefix(table_data, 0, 2); - - /* Host Bridge List (list of UIDs - currently bus_nr) */ - for (i =3D 0; i < fw->num_targets; i++) { - g_assert(fw->target_hbs[i]); - build_append_int_noprefix(table_data, PXB_DEV(fw->target_hbs[i= ])->bus_nr, 4); - } + /* Host Bridge List (list of UIDs - currently bus_nr) */ + for (i =3D 0; i < fw->num_targets; i++) { + g_assert(fw->target_hbs[i]); + build_append_int_noprefix(table_data, + PXB_DEV(fw->target_hbs[i])->bus_nr, 4); } } =20 @@ -202,6 +200,7 @@ void cxl_build_cedt(GArray *table_offsets, GArray *tabl= e_data, BIOSLinker *linker, const char *oem_id, const char *oem_table_id, CXLState *cxl_state) { + GSList *cfmws_list, *iter; Aml *cedt; AcpiTable table =3D { .sig =3D "CEDT", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id }; @@ -213,7 +212,12 @@ void cxl_build_cedt(GArray *table_offsets, GArray *tab= le_data, /* reserve space for CEDT header */ =20 object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, = cedt); - cedt_build_cfmws(cedt->buf, cxl_state); + + cfmws_list =3D cxl_fmws_get_all_sorted(); + for (iter =3D cfmws_list; iter; iter =3D iter->next) { + cedt_build_cfmws(CXL_FMW(iter->data), cedt); + } + g_slist_free(cfmws_list); =20 /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len); diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c index cae4afcdde2..c015baac813 100644 --- a/hw/cxl/cxl-host-stubs.c +++ b/hw/cxl/cxl-host-stubs.c @@ -8,8 +8,13 @@ #include "hw/cxl/cxl.h" #include "hw/cxl/cxl_host.h" =20 -void cxl_fmws_link_targets(CXLState *stat, Error **errp) {}; +void cxl_fmws_link_targets(Error **errp) {}; void cxl_machine_init(Object *obj, CXLState *state) {}; void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)= {}; +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr) +{ + return base; +}; +void cxl_fmws_update_mmio(void) {}; =20 const MemoryRegionOps cfmws_ops; diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index b7aa429ddf4..5c2ce25a19c 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -22,12 +22,12 @@ #include "hw/pci/pcie_port.h" #include "hw/pci-bridge/pci_expander_bridge.h" =20 -static void cxl_fixed_memory_window_config(CXLState *cxl_state, - CXLFixedMemoryWindowOptions *ob= ject, +static void cxl_fixed_memory_window_config(CXLFixedMemoryWindowOptions *ob= ject, int index, Error **errp) { ERRP_GUARD(); - g_autofree CXLFixedWindow *fw =3D g_malloc0(sizeof(*fw)); + DeviceState *dev =3D qdev_new(TYPE_CXL_FMW); + CXLFixedWindow *fw =3D CXL_FMW(dev); strList *target; int i; =20 @@ -67,35 +67,39 @@ static void cxl_fixed_memory_window_config(CXLState *cx= l_state, fw->targets[i] =3D g_strdup(target->value); } =20 - cxl_state->fixed_windows =3D g_list_append(cxl_state->fixed_windows, - g_steal_pointer(&fw)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp); } =20 -void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp) +static int cxl_fmws_link(Object *obj, void *opaque) { - if (cxl_state && cxl_state->fixed_windows) { - GList *it; + struct CXLFixedWindow *fw; + int i; =20 - for (it =3D cxl_state->fixed_windows; it; it =3D it->next) { - CXLFixedWindow *fw =3D it->data; - int i; - - for (i =3D 0; i < fw->num_targets; i++) { - Object *o; - bool ambig; - - o =3D object_resolve_path_type(fw->targets[i], - TYPE_PXB_CXL_DEV, - &ambig); - if (!o) { - error_setg(errp, "Could not resolve CXLFM target %s", - fw->targets[i]); - return; - } - fw->target_hbs[i] =3D PXB_CXL_DEV(o); - } - } + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; } + fw =3D CXL_FMW(obj); + + for (i =3D 0; i < fw->num_targets; i++) { + Object *o; + bool ambig; + + o =3D object_resolve_path_type(fw->targets[i], TYPE_PXB_CXL_DEV, + &ambig); + if (!o) { + error_setg(&error_fatal, "Could not resolve CXLFM target %s", + fw->targets[i]); + return 1; + } + fw->target_hbs[i] =3D PXB_CXL_DEV(o); + } + return 0; +} + +void cxl_fmws_link_targets(Error **errp) +{ + /* Order doesn't matter for this, so no need to build list */ + object_child_foreach_recursive(object_get_root(), cxl_fmws_link, NULL); } =20 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, @@ -335,7 +339,7 @@ static void machine_set_cfmw(Object *obj, Visitor *v, c= onst char *name, } =20 for (it =3D cfmw_list, index =3D 0; it; it =3D it->next, index++) { - cxl_fixed_memory_window_config(state, it->value, index, errp); + cxl_fixed_memory_window_config(it->value, index, errp); } state->cfmw_list =3D cfmw_list; } @@ -373,3 +377,110 @@ void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState = *state, Error **errp) } } } + +static int cxl_fmws_find(Object *obj, void *opaque) +{ + GSList **list =3D opaque; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + *list =3D g_slist_prepend(*list, obj); + + return 0; +} + +static GSList *cxl_fmws_get_all(void) +{ + GSList *list =3D NULL; + + object_child_foreach_recursive(object_get_root(), cxl_fmws_find, &list= ); + + return list; +} + +static gint cfmws_cmp(gconstpointer a, gconstpointer b, gpointer d) +{ + const struct CXLFixedWindow *ap =3D a; + const struct CXLFixedWindow *bp =3D b; + + return ap->index > bp->index; +} + +GSList *cxl_fmws_get_all_sorted(void) +{ + return g_slist_sort_with_data(cxl_fmws_get_all(), cfmws_cmp, NULL); +} + +static int cxl_fmws_mmio_map(Object *obj, void *opaque) +{ + struct CXLFixedWindow *fw; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + fw =3D CXL_FMW(obj); + sysbus_mmio_map(SYS_BUS_DEVICE(fw), 0, fw->base); + + return 0; +} + +void cxl_fmws_update_mmio(void) +{ + /* Ordering is not required for this */ + object_child_foreach_recursive(object_get_root(), cxl_fmws_mmio_map, N= ULL); +} + +hwaddr cxl_fmws_set_memmap(hwaddr base, hwaddr max_addr) +{ + GSList *cfmws_list, *iter; + CXLFixedWindow *fw; + + cfmws_list =3D cxl_fmws_get_all_sorted(); + for (iter =3D cfmws_list; iter; iter =3D iter->next) { + fw =3D CXL_FMW(iter->data); + if (base + fw->size <=3D max_addr) { + fw->base =3D base; + base +=3D fw->size; + } + } + g_slist_free(cfmws_list); + + return base; +} + +static void cxl_fmw_realize(DeviceState *dev, Error **errp) +{ + CXLFixedWindow *fw =3D CXL_FMW(dev); + + memory_region_init_io(&fw->mr, OBJECT(dev), &cfmws_ops, fw, + "cxl-fixed-memory-region", fw->size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &fw->mr); +} + +/* + * Note: Fixed memory windows represent fixed address decoders on the host= and + * as such have no dynamic state to reset or migrate + */ +static void cxl_fmw_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "CXL Fixed Memory Window"; + dc->realize =3D cxl_fmw_realize; + /* Reason - created by machines as tightly coupled to machine memory m= ap */ + dc->user_creatable =3D false; +} + +static const TypeInfo cxl_fmw_info =3D { + .name =3D TYPE_CXL_FMW, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CXLFixedWindow), + .class_init =3D cxl_fmw_class_init, +}; + +static void cxl_host_register_types(void) +{ + type_register_static(&cxl_fmw_info); +} +type_init(cxl_host_register_types) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index b2116335752..860346d6b7f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -609,7 +609,7 @@ void pc_machine_done(Notifier *notifier, void *data) &error_fatal); =20 if (pcms->cxl_devices_state.is_enabled) { - cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); + cxl_fmws_link_targets(&error_fatal); } =20 /* set the number of CPUs */ @@ -718,20 +718,28 @@ static uint64_t pc_get_cxl_range_start(PCMachineState= *pcms) return cxl_base; } =20 +static int cxl_get_fmw_end(Object *obj, void *opaque) +{ + struct CXLFixedWindow *fw; + uint64_t *start =3D opaque; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + fw =3D CXL_FMW(obj); + + *start +=3D fw->size; + + return 0; +} + static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) { uint64_t start =3D pc_get_cxl_range_start(pcms) + MiB; =20 - if (pcms->cxl_devices_state.fixed_windows) { - GList *it; - - start =3D ROUND_UP(start, 256 * MiB); - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D it->= next) { - CXLFixedWindow *fw =3D it->data; - start +=3D fw->size; - } - } - + /* Ordering doesn't matter so no need to build a sorted list */ + object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end, + &start); return start; } =20 @@ -933,23 +941,9 @@ void pc_memory_init(PCMachineState *pcms, cxl_base =3D pc_get_cxl_range_start(pcms); memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); memory_region_add_subregion(system_memory, cxl_base, mr); - cxl_resv_end =3D cxl_base + cxl_size; - if (pcms->cxl_devices_state.fixed_windows) { - hwaddr cxl_fmw_base; - GList *it; - - cxl_fmw_base =3D ROUND_UP(cxl_base + cxl_size, 256 * MiB); - for (it =3D pcms->cxl_devices_state.fixed_windows; it; it =3D = it->next) { - CXLFixedWindow *fw =3D it->data; - - fw->base =3D cxl_fmw_base; - memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops= , fw, - "cxl-fixed-memory-region", fw->size); - memory_region_add_subregion(system_memory, fw->base, &fw->= mr); - cxl_fmw_base +=3D fw->size; - cxl_resv_end =3D cxl_fmw_base; - } - } + cxl_base =3D ROUND_UP(cxl_base + cxl_size, 256 * MiB); + cxl_resv_end =3D cxl_fmws_set_memmap(cxl_base, maxphysaddr); + cxl_fmws_update_mmio(); } =20 /* Initialize PC system firmware */ --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241467; cv=none; d=zohomail.com; s=zohoarc; b=Qsau7LenhEUyD2ry1IbmbTb9RZj1WegGcWkcqOQDgktH/8+G8ryRGZ8uZWJF+GeXtVMJIyh5XSonoMn7kzdpI48/ZJ3rtRzncOfFstcz8UvSZrlkiuBf/P/X9FtWmyaAH4JUiool9+04UGGtf1PGMPaZ5V//zvlji4PykjFklFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241467; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=554uR+tWHHbPvIB9l177CJtnBAnLDMfIkrvonXqbU0Y=; b=SKBfXwxW6lC1thK4DP7ZuDX/HMWjs+TYXYnlZvMMWUkGrp2WPglq6ckJ/esqXH8IS4FagypxUrCrWWVMY7jOK5Bq1FFgjVLgcR9WxDRfZNqBvinyxMEjq5+mKnMJf5K15behbpmmwjkyfKghEAJ46tMnsj6RjkZY7V8UCTU/eMA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241467222439.68026489565136; Fri, 11 Jul 2025 06:44:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuj-0005nX-Fe; Fri, 11 Jul 2025 09:35:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtr-0004QA-39 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:51 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDto-00032u-Bz for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:50 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-454aaade1fbso21792095e9.3 for ; Fri, 11 Jul 2025 06:34:47 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240887; x=1752845687; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=554uR+tWHHbPvIB9l177CJtnBAnLDMfIkrvonXqbU0Y=; b=GsfUTWUbXV64bu6TVB7/LMTokB79DhnUrYH32Htk9KTXCMtJy5sXv0lp/k0AmgmLHn dDcbzp6vTlEEUZtq0F+GnDduc/+ziuWHJFNzePSaZkIe1cWiGsm94Ie/AMG4runr6BUH zSeP8tMrtNavuh6QYtxA6r/UHdKTBooDPGhBW8rx2+kH8pfpCTUd68mUcih8MPnFI8MF 8NwbX6RwEcEyWen4HoJ0R+VTHmTjfyzVXdhFP2sE85B2V8c8RUHepKPWhnrX0NPqlrSZ XF+DPEY2bX+TqFOIpcZp+ByWFHzVLlJTopiI7cA7Fz9q2GDerlB0aUFvskf6scc6Xr/e yhxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240887; x=1752845687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=554uR+tWHHbPvIB9l177CJtnBAnLDMfIkrvonXqbU0Y=; b=w1/1FhSQoBK7Ce+8gSDl7NR13NV8yS3ixn4R/dPHPyZvwbjTFZ5O1OgK/eUSiYX8rK nnNn/SjfOqF37tOA7MolmtTU7DGHWSgv5ulEEm4n9zlB6iQK9SCw8tVJMdzdFoBx+vmO OVO+HvYxnk1kwk5BMtZ30clUY59lcCXLKeuohEqLlGPzdPqoxqe5G0JFX7m8hOgRQwOn HgxwGWrsq6Ag01WCVdZ2pt9HNrx41k6xP5879DjFNkyNfS/7KlTW0IMxMAsauf7BmJN8 wQ+iXxAMUu65ICU9AEMnTqhfOeok2wDl2DrXNYBnlB/sdeA6tFBwGy+unUQDVT0CFpj4 VxTw== X-Gm-Message-State: AOJu0YxxIxzdoYR740qspuXj0WizIqajtj2zf9AcAaWurU5P4i12rX7p 5zcnd1XCUWBh2FnVIRM72OVgZJb8nVOLG2/yEj1NSpZ0kSe9SddszxdCMgRPrAUrJpbpFgB1pKI Spx3R X-Gm-Gg: ASbGnct+gLljrNlDWUJFyXIlvDiSLhLixs0ArlpNNRifx1oj3deUD6FhQE4FbBN1gnP PSISMzWHpVlK/xzq3+uomhmjtzdYFhFjLRIi5drMdsFnfmsqv4E7NvhuC4NIavRVbS/JK7hVI17 wyDVdfMlsUz1t6oVxdGCUWY5VTf1cYiBRaF3/SYVdaeMlI9g3iDPZVTLavNb9U5Q4DeAVIZsYc+ YUXUnmZ84Buyv9QDi2Vgx53+m/yQu4fVXjbqWXNkxOOIXwlblU+8e+jDyE9GMQuibHK5x35lKpt URKIivqu2ciUgBPggL8y+njzK+JMYBG69Sg5GOYqKCRh48D3CEpoYTo4x2f41L9kCHKkKgsZ3qf g+zWEwFMsW7/Q/YyTxoH8ps2QUHGi X-Google-Smtp-Source: AGHT+IHV/SoVnbOTV0TjQ9aK3UDZ4znKLKtl1G00ZdM2vWVxii1XL01+dpEr6lXdVd3Nu3jrLDgl6A== X-Received: by 2002:a05:600c:3155:b0:441:ac58:eb31 with SMTP id 5b1f17b1804b1-454f4257e83mr23164205e9.20.1752240886518; Fri, 11 Jul 2025 06:34:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Date: Fri, 11 Jul 2025 14:34:07 +0100 Message-ID: <20250711133429.1423030-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241468647116600 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. This is a hole in the current map so adding them here has no impact on placement of other memory regions (tested with enough CPUs for GIC_REDIST2 to be in use.) The high memory map is GiB aligned so the hole is there whatever the size of memory or device_memory below this point. The CFMWs are placed above the extended memmap. Note the existing variable highest_gpa is the highest GPA that has been allocated at a particular point in setting up the memory map. Whilst this caused some confusion in review there are existing comments explaining this so nothing is added. The cxl_devices_state.host_mr provides a small space in which to place the individual host bridge register regions for whatever host bridges are allocated via -device pxb-cxl on the command line. The existing dynamic sysbus infrastructure is not reused because pxb-cxl is a PCI device not a sysbus one but these registers are directly in the main memory map, not the PCI address space. Only create the CEDT table if cxl=3Don set for the machine. Default to off. Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Tested-by: Li Zhijian Message-id: 20250703104110.992379-4-Jonathan.Cameron@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 9 +++++++++ include/hw/arm/virt.h | 4 ++++ hw/arm/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 77 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 6a719b95863..10cbffc8a70 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -31,6 +31,7 @@ Supported devices The virt board supports: =20 - PCI/PCIe devices +- CXL Fixed memory windows, root bridges and devices. - Flash memory - Either one or two PL011 UARTs for the NonSecure World - An RTC @@ -189,6 +190,14 @@ ras acpi Set ``on``/``off``/``auto`` to enable/disable ACPI. =20 +cxl + Set ``on``/``off`` to enable/disable CXL. More details in + :doc:`../devices/cxl`. The default is off. + +cxl-fmw + Array of CXL fixed memory windows describing fixed address routing to + target CXL host bridges. See :doc:`../devices/cxl`. + dtb-randomness Set ``on``/``off`` to pass random seeds via the guest DTB rng-seed and kaslr-seed nodes (in both "/chosen" and diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d21..4375819ea06 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -36,6 +36,7 @@ #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/block/flash.h" +#include "hw/cxl/cxl.h" #include "system/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" @@ -85,6 +86,7 @@ enum { /* indices of IO regions located after the RAM */ enum { VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, + VIRT_CXL_HOST, VIRT_HIGH_PCIE_ECAM, VIRT_HIGH_PCIE_MMIO, }; @@ -140,6 +142,7 @@ struct VirtMachineState { bool secure; bool highmem; bool highmem_compact; + bool highmem_cxl; bool highmem_ecam; bool highmem_mmio; bool highmem_redists; @@ -174,6 +177,7 @@ struct VirtMachineState { char *oem_id; char *oem_table_id; bool ns_el2_virt_timer_irq; + CXLState cxl_devices_state; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index cd90c47976c..c3b9b3f6ea4 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -39,10 +39,12 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" +#include "hw/acpi/cxl.h" #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/tpm.h" #include "hw/acpi/hmat.h" +#include "hw/cxl/cxl.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -119,10 +121,29 @@ static void acpi_dsdt_add_flash(Aml *scope, const Mem= MapEntry *flash_memmap) aml_append(scope, dev); } =20 +static void build_acpi0017(Aml *table) +{ + Aml *dev, *scope, *method; + + scope =3D aml_scope("_SB"); + dev =3D aml_device("CXLM"); + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017"))); + + method =3D aml_method("_STA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(0x0B))); + aml_append(dev, method); + build_cxl_dsm_method(dev); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irq, VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); + bool cxl_present =3D false; + PCIBus *bus =3D vms->bus; struct GPEXConfig cfg =3D { .mmio32 =3D memmap[VIRT_PCIE_MMIO], .pio =3D memmap[VIRT_PCIE_PIO], @@ -136,6 +157,14 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, } =20 acpi_dsdt_add_gpex(scope, &cfg); + QLIST_FOREACH(bus, &vms->bus->child, sibling) { + if (pci_bus_is_cxl(bus)) { + cxl_present =3D true; + } + } + if (cxl_present) { + build_acpi0017(scope); + } } =20 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -1027,6 +1056,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuil= dTables *tables) } } =20 + if (vms->cxl_devices_state.is_enabled) { + cxl_build_cedt(table_offsets, tables_blob, tables->linker, + vms->oem_id, vms->oem_table_id, &vms->cxl_devices_s= tate); + } + if (ms->nvdimms_state->is_enabled) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, ms->nvdimms_state, ms->ram_slots, vms->oem_id, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3bcdf92e2ff..394e8b53018 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -57,6 +57,7 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/pci-host/gpex.h" +#include "hw/pci-bridge/pci_expander_bridge.h" #include "hw/virtio/virtio-pci.h" #include "hw/core/sysbus-fdt.h" #include "hw/platform-bus.h" @@ -86,6 +87,8 @@ #include "hw/virtio/virtio-md-pci.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" =20 static GlobalProperty arm_virt_compat[] =3D { @@ -220,9 +223,11 @@ static const MemMapEntry base_memmap[] =3D { static MemMapEntry extended_memmap[] =3D { /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ [VIRT_HIGH_GIC_REDIST2] =3D { 0x0, 64 * MiB }, + [VIRT_CXL_HOST] =3D { 0x0, 64 * KiB * 16 }, /* 16 UID */ [VIRT_HIGH_PCIE_ECAM] =3D { 0x0, 256 * MiB }, /* Second PCIe window */ [VIRT_HIGH_PCIE_MMIO] =3D { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE }, + /* Any CXL Fixed memory windows come here */ }; =20 static const int a15irqmap[] =3D { @@ -1623,6 +1628,17 @@ static void create_pcie(VirtMachineState *vms) } } =20 +static void create_cxl_host_reg_region(VirtMachineState *vms) +{ + MemoryRegion *sysmem =3D get_system_memory(); + MemoryRegion *mr =3D &vms->cxl_devices_state.host_mr; + + memory_region_init(mr, OBJECT(vms), "cxl_host_reg", + vms->memmap[VIRT_CXL_HOST].size); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, m= r); + vms->highmem_cxl =3D true; +} + static void create_platform_bus(VirtMachineState *vms) { DeviceState *dev; @@ -1739,6 +1755,12 @@ void virt_machine_done(Notifier *notifier, void *dat= a) struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 + cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state, + &error_fatal); + + if (vms->cxl_devices_state.is_enabled) { + cxl_fmws_link_targets(&error_fatal); + } /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where @@ -1785,6 +1807,7 @@ static inline bool *virt_get_high_memmap_enabled(Virt= MachineState *vms, { bool *enabled_array[] =3D { &vms->highmem_redists, + &vms->highmem_cxl, &vms->highmem_ecam, &vms->highmem_mmio, }; @@ -1892,6 +1915,9 @@ static void virt_set_memmap(VirtMachineState *vms, in= t pa_bits) if (device_memory_size > 0) { machine_memory_devices_init(ms, device_memory_base, device_memory_= size); } + vms->highest_gpa =3D cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1, + 256 * MiB), + BIT_ULL(pa_bits)) - 1; } =20 static VirtGICType finalize_gic_version_do(const char *accel_name, @@ -2343,6 +2369,8 @@ static void machvirt_init(MachineState *machine) memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, machine->ram); =20 + cxl_fmws_update_mmio(); + virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem); =20 create_gic(vms, sysmem); @@ -2398,6 +2426,7 @@ static void machvirt_init(MachineState *machine) create_rtc(vms); =20 create_pcie(vms); + create_cxl_host_reg_region(vms); =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); @@ -3364,6 +3393,7 @@ static void virt_instance_init(Object *obj) =20 vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); + cxl_machine_init(obj, &vms->cxl_devices_state); } =20 static const TypeInfo virt_machine_info =3D { --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241253; cv=none; d=zohomail.com; s=zohoarc; b=VCBFCf0v6ukeHbmr93JyPDBKpdSCLS3rt2ZN6jZYv1WVUkvveb22ov+HumnHYMQrt/qZ/Rd0ToLkv+E+xvat+y6FSsI/xOngxAMQpBhrCB5kNY5sIH1UTtjSzjKhwgp2uBCPK0w3cy999agr6gH1OtTRrMHDpq7zr3drnBL6A78= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241253; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=x2nVtAA8fp2H3YDMXCDIIgapnlhWHhnckzqsHWXu494=; b=l6WzfrZY7TAKgDcapAPaAOxytKOZ9wgX248zOMw2T2PQrIUQ/mRLbqooIXyLQOkK2rdl2C1mFFPk2OErE3bSBLvcKaxaFRMfM+HmjsJlcKeNpvZ1T8w0MnWiPc+iUy3jf+UDHQ0okuoqHiPs9CBN1JC6+fdXfBeJDrGZnaN184I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241253559518.7644991514994; Fri, 11 Jul 2025 06:40:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDue-0005XY-OU; Fri, 11 Jul 2025 09:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtq-0004Q9-WD for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:51 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtp-00033P-7j for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:50 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-455b002833bso2469315e9.0 for ; Fri, 11 Jul 2025 06:34:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240887; x=1752845687; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=x2nVtAA8fp2H3YDMXCDIIgapnlhWHhnckzqsHWXu494=; b=pWLbwfRQ/y01dFJe79oyuMaoLAfy5X6aWeE7fxVOScbrTEDSgzCOSYlaSd1hmmQ/N3 1/PnDCj+So71U6Y999vFPafiUtTdVuCGCIkG3mJ76aG/24oik+nxYGGieTzYSg9ZbqfK KF4cD1Dz4VpFXoclFTmp06GtYQl5ohrzuUwg4VzO6/+GqpJW/KxucaxFRFSSfLVCTkL2 9zwJpBXcLk60B9bM0iLNQtaDU44w6kV/KlUBHZwb+WW8bKSwtigblStvjlSz/VOATanO CSsuGrXxLkIu+UEiBaNxrKTE3UMbytLrf92mMvzpL40YSD9AD15k8+rae8Dv1yNDyoJw 7Gjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240887; x=1752845687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x2nVtAA8fp2H3YDMXCDIIgapnlhWHhnckzqsHWXu494=; b=W10M1vu8gnHIG+zsM72XyQgE55OBnREBqp7uLASEsIaYxKy+n+Qy/91j7+3q08QzU4 d/U6rb/c/HxCucxv5iLiXQMumDLHojTPjNlFeUQScqKodfXxyPHLo9G9XI4DKZVVlNR4 Hhl8uMyDFrJ+aRVCqzognKfGZ1XNjIeno1tPNhq3JCc9+Ejo+zH6uv8reKIPcHM7l5x7 +Cvsm7LB2SUle+SFlFl9LXC2x88TMbY+Fcue1u4VDaz7NSP4VoS1pmIEtMU/Eh93xHqA EvsknTwjQpMZ8VlWkKhU/ay39reC+GfNyvd0+7rXBNaY9wt8PaU7ORJpIc+Bfozj8XLV 5IbA== X-Gm-Message-State: AOJu0YxU/pOe/3mS0/V2lHHvPVjGG+WTJd3lxl8VDkSTA8/VpPW5CW1+ PFz561yJBoyJUgFig4lBoxMwKDpvWyb1/C//bkAkjkHIRqH09OlPZp/4isQgUE8ieAE/srcI3+V oPPFR X-Gm-Gg: ASbGncsQIBjs8JG88d+awFsCo7btN0bohkEy+y0VB3F+2zkWvR/aUx4L7OsJyJ7x4Dg 2SIfOU/b1CnGjKM/1nbTbOFxmxlf4/Ul71GZcdIfvxQaZvLirMVnJNm+VZrt+Nf84P372Yc0p6N nPC5XLNOeHubXhBxsp1B7Tj8lE5+EhCh/9dk/SPSg6QwWVC9qm35J0lrFZQm4Id0H4vZgoY7G1W Fl5vvdmunDfScpSjP/rngwboDrgjjSV/K0t8NUL+XC96gdw4w5ZBOKfRxjGa7/+TVw+gnCIfSiF K30dWJCQWr1O7VM+zOgK0gChfqp7YI2w/W+DFNGmwLclnkDkaX7bZct7YfkJtCU/HdiwzWovWhm Gfgr+LHdjIroJVBIlZU6j/n6JIU/IRrZ/8C+nG4Y= X-Google-Smtp-Source: AGHT+IGuX1eqhcqjGz7erYss60WbhYzGWHm1RjdLt+okYvnQaX4ePvQ8lngC296bBmwAZAAhrUMcHA== X-Received: by 2002:a05:600c:1c95:b0:451:833f:483c with SMTP id 5b1f17b1804b1-454ec133982mr33708365e9.7.1752240887513; Fri, 11 Jul 2025 06:34:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/36] docs/cxl: Add an arm/virt example. Date: Fri, 11 Jul 2025 14:34:08 +0100 Message-ID: <20250711133429.1423030-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241255672116600 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Only add one very simple example as all the i386/pc examples will work for arm/virt with a change to appropriate executable and appropriate standard launch line for arm/virt. Note that max cpu is used to ensure we have plenty of physical address space. Suggested-by: Peter Maydell Reviewed-by: Eric Auger Signed-off-by: Jonathan Cameron Tested-by: Itaru Kitayama Tested-by: Li Zhijian Message-id: 20250703104110.992379-5-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell --- docs/system/devices/cxl.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index e307caf3f88..ca15a0da1c1 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -384,6 +384,17 @@ An example of 4 devices below a switch suitable for 1,= 2 or 4 way interleave:: -device cxl-type3,bus=3Dswport3,persistent-memdev=3Dcxl-mem3,lsa=3Dcxl-l= sa3,id=3Dcxl-pmem3,sn=3D0x4 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +A simple arm/virt example featuring a single direct connected CXL Type 3 +Volatile Memory device:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8g,s= lots=3D4 -cpu max -smp 4 \ + ... + -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,id=3Dcxl-vme= m0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + Deprecations ------------ =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240991; cv=none; d=zohomail.com; s=zohoarc; b=akAyijFSRoH4kB2eVU8cmD4hRTFl6J5qo2b0VQ8ize3pVSJ0qlxYkBktA/hRMQjp8PcZMJasjo+EPQOKyipZ+PqsbhY9Os0pjxL+ikzDyJz+E1/wO9fcBKPtsbvSHwU+adyx1Bmx+NxYfP8Jwc7nNrdKI+6g/UBNCu28GTVwaIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240991; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Z/tqj/ko8WEeVpxtCck+nDGeWxY6ZT+VKsk2/PDMd8Q=; b=Mf2hkoxtSBNZLAiDXx9XbZ6vrXYl1Od1QYkngh4KW94qhaXwtnUTgpsXZi9xpgUClrSuZ0eQnUv5fhV8PCgRGdw969Wu1I2ViEWc5PRS4c0wPnzEakdWtWouYj6qzg4uv1V1nWKoxKSNTJeJj35Wauso8Hx7FD/VO8aNaOzErYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240991682135.02526070751196; Fri, 11 Jul 2025 06:36:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDu1-0004W9-AL; Fri, 11 Jul 2025 09:35:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDts-0004Qw-Ix for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:55 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtq-000348-56 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:52 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-45555e3317aso4183795e9.3 for ; Fri, 11 Jul 2025 06:34:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240888; x=1752845688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Z/tqj/ko8WEeVpxtCck+nDGeWxY6ZT+VKsk2/PDMd8Q=; b=gMJl0g4Qa7wFlp20dwQzq6+oE37XbmPyuhMQJWBQ4T7T4o1KPg/guh8my4iSAEj4x3 3c1U9Tw2n/p2FBGu/VYsw3gHuGhR5WfNdyF8ougwriyOpLOKeRZwbJhIrm9BuR/qgh3L oADPqnH92aeL3v+hcmcFa219bmGbggu/7FiFtPUGbbVjl2H2W+qP5GvM9vb3fPbHh5xR ud+gosHISKxq5i/26TmlI1HSr8Veu+ojlBEL30FZgyVGwAgyyKW6aHNEJSlMQ0hHc0Ri tPWfIXR6qSYPzdTScrN0amYG6amppWcwcDM4JynhAqAh0hVT0ryO8XrxhNBIynEEwmVH pkPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240888; x=1752845688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z/tqj/ko8WEeVpxtCck+nDGeWxY6ZT+VKsk2/PDMd8Q=; b=ZK2qNzGcaFNNr28cdT+xiOOwdis1qoizje2Wb36i0E/tyqYSU0ASRTgIaQhzbrWj7+ 2kPgjdcFmpHNdnkrV461+I2mFIZz9/+axeykBhSdu/7wA4vyvhzXOoLktOwrASNryJwq /HdouDQbPBwu5MZ8HkUSmWz47gRsvHKHEKkKjDWZN3u0D+AlvbXXe33tAng+tKztIeWt 2bR7vgeF3xO75fiYT4vrBoHHdlA+/j033BN7MqCP2JpMCZ1UhjUwylUbeUS1Nk4wcmUj YQz9MdJzo71+WJN+n2Tvi8eP4WZSNp1QtWXGXKMIzTfv1IVOMINpr662tiUjMAUT2C1Q xHEg== X-Gm-Message-State: AOJu0Ywp4X+OVyz2qeyk+TTJaud04ssJNkvIGPxB2rLmf3jr6qMvzyrs 3OiP9Xjq8Hz4gGuMZ534YWuIrQFA7om3i5tdVS/XmpzU01HsvwZf7nKrk3q16qI7kNFx5T3lnj4 huwuW X-Gm-Gg: ASbGncsiGQZQsCU4Fnd6v+5HGjVin2R0pJEmK5q6qSvLVHrnDGP6gzn1ikSmxwv493r 2i+sk/IJeITEOltqHHKoiuFDdNFnKP7qc7SNrOBjb6QrIIBZvVHtB9yKP+7yNuOztJX3AEPye3B fWs0JYqiLGCvF5BAUcxMCuEhzggr53dwPJYDjbJBWLEhfl5KCqyRVDfLVXq71MN5U2AhaIKbm2m MI1aHD3DYe7ljASjOpI4W8qYo9B7g1ruF5KeKt/TUseObg6deWEq7N3G52DjKpvlKpaS98Xp+Oy av+4kQwzz2KjBEYkYlCgZH5DIRAMEwQbYqk5fjZPtyZkC2Ea52RF4JOfqubXMwIU3BKFHayyRoe NATjyZbQGTnmWBVijpOYkASss7iGW X-Google-Smtp-Source: AGHT+IH1VaYSUQnz3XrsTenMXkbJsXMHztbZz2iPD5JrG4OHiJBcycGhoVBo5LoYYWNg0aIop/4Wow== X-Received: by 2002:a05:600c:c11c:b0:453:66f:b96e with SMTP id 5b1f17b1804b1-454ec146a71mr22329455e9.11.1752240888576; Fri, 11 Jul 2025 06:34:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/36] qtest/cxl: Add aarch64 virt test for CXL Date: Fri, 11 Jul 2025 14:34:09 +0100 Message-ID: <20250711133429.1423030-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240993839116600 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Add a single complex case for aarch64 virt machine. Given existing much more comprehensive tests for x86 cover the common functionality, a single test should be enough to verify that the aarch64 part continues to work. Tested-by: Itaru Kitayama Reviewed-by: Eric Auger Signed-off-by: Jonathan Cameron Tested-by: Li Zhijian Message-id: 20250703104110.992379-6-Jonathan.Cameron@huawei.com Signed-off-by: Peter Maydell --- tests/qtest/cxl-test.c | 58 ++++++++++++++++++++++++++++++++--------- tests/qtest/meson.build | 1 + 2 files changed, 46 insertions(+), 13 deletions(-) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index a6003318439..8fb7e58d4f1 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -19,6 +19,12 @@ "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53 " \ "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl.1,cxl-fmw.0.= size=3D4G " =20 +#define QEMU_VIRT_2PXB_CMD \ + "-machine virt,cxl=3Don -cpu max " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 " \ + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53 " \ + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl.1,cxl-fmw.0.= size=3D4G " + #define QEMU_RP \ "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " =20 @@ -197,25 +203,51 @@ static void cxl_2pxb_4rp_4t3d(void) qtest_end(); rmdir(tmpfs); } + +static void cxl_virt_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); + rmdir(tmpfs); +} #endif /* CONFIG_POSIX */ =20 int main(int argc, char **argv) { - g_test_init(&argc, &argv, NULL); + const char *arch =3D qtest_get_arch(); =20 - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); - qtest_add_func("/pci/cxl/rp", cxl_root_port); - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + g_test_init(&argc, &argv, NULL); + if (strcmp(arch, "i386") =3D=3D 0 || strcmp(arch, "x86_64") =3D=3D 0) { + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window= ); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_= lsa); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", + cxl_2pxb_4rp_4t3d); #endif + } else if (strcmp(arch, "aarch64") =3D=3D 0) { +#ifdef CONFIG_POSIX + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", + cxl_virt_2pxb_4rp_4t3d); +#endif + } + return g_test_run(); } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 91b4a71a186..5ad969f6165 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -262,6 +262,7 @@ qtests_aarch64 =3D \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : [])= + \ (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ + qtests_cxl + = \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241003; cv=none; d=zohomail.com; s=zohoarc; b=MRV7H32qlK4xvZ3zZ6D2yVrPg4aC0Llel39nPH3s7fnXl6kGkkfOZKbvU+vygjPFkCDRzjeaJGoGJ0d/6l/1QkAlvDG40WH3SD6NYyC5NbzSBGgLF7Nt6loPMyoQ5BYpcex9D23eqanWoQUTdl5hUv/ZbitmNEE9Dhv0gq6FqCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241003; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Erap8AHQdZkhg+yiGAeAXU/b7lA6PMXWKp0iI3z4iK8=; b=XonkGim7+YA1Q00TmTmDHkTVRs7x7ZuJNNCY4KBb6g6mVF87Tqj0kiy1jE2TnMv7s9E6OPTNektLfrny5OMk0huojIUiuw6o3mmSQ78k2QskE+c4miH1jT97DjfKD/sfx/9WkMz82MO+N1mHLQ1s4csd5dsdtcdTDBNaDjkFA0U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241003089735.3896490464787; Fri, 11 Jul 2025 06:36:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuc-0005Tw-PG; Fri, 11 Jul 2025 09:35:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtu-0004RA-94 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:55 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtr-00034l-Ie for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:53 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-455e6fb8057so6305515e9.3 for ; Fri, 11 Jul 2025 06:34:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240890; x=1752845690; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Erap8AHQdZkhg+yiGAeAXU/b7lA6PMXWKp0iI3z4iK8=; b=YtQF5Hn6794FEejrChFZUoKo75JlMawMLrFFOXFCdsGxFsD1gtJu2DYwH3JOAvNWlO he3NukpNVEvPtRhlELRxXPV6rz6UOSVT/Ps6gUA9EIpjTo9lbcvCia3ffPp2oVYNQymP bKLZQVYSa9q+knOgqOz+LQilhDFK2RXlcQCvOVH4SJrX8UM9CEignT4T77tvuMh7vF/N PZXfcV9Hk1anRbCcfp9AEN+NH8waLOB2PAughQKFaLoRuL4B7UQTKEF9cJUcf5vjrNTl dL6ryeQWyj6N6CBz36jJ10HFIQgBjRQS6+Y/DL1QNdce1eqLcJzKOOyUmf7zAWPvsc4B b/vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240890; x=1752845690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Erap8AHQdZkhg+yiGAeAXU/b7lA6PMXWKp0iI3z4iK8=; b=MIyugQ6t45cJ98dyPRO7Hvq61uMBA4kfXrO/C7/yDU9CHV2beMadZpk1bd0S+9Yflr u1L3MY83gsXyuf0YVW1JnZMEUH9JdSGas1Y2XsBukzyUH8baiqTfQovubjOG7V4zjEk0 kLg4/Kb07NA81lR1zebUKfOi+pSBavrwI9Dk5I4/vvoArwwjXauSHqu9CnxhmmQMsXRQ NnI2511/zHwwOAM/HrHJfof6u7H3V7E23l2R4q7faov8lvp91W5odj/tDRkwW/ZToqIP aQ1/GdkB/PpRCrUfAnjFGZbVWlGWRwAJcZ1TPnQ/xx2LXIT1s3ekbjPg/Wambju02Pdx ZU8w== X-Gm-Message-State: AOJu0Ywr2lLW2hEW9YkmxpSCpLMGjTWBQlwXsMPN7ivhb/jlha/n0iyv XyDDmCAxVv6993c1gYp5qbvBYx3ntF6x/qGD1wPjP26IUwQMYg8GuUsF64OZ+o+SaY+w/1DhhCD P5E53 X-Gm-Gg: ASbGnctEOJpQAXvpIuy89+oWho6RTNwQsj4FZvm4WaL3NDxvD+1D0bJibPt1ZyfKCS0 fePuEuiHuHIe7rvilXXrm35ThtYq4pVPA95QNKBSp9m9GB7Psp/tHlNjuEZA67bs+Y0VonbRrIB UOF2lZLvhGMx9R1ko0ENnOawQ9fQ7/v8HUshtKCcffNRTE6Hat4nZo9x93mvNlSvzABIixx8JOj axc2jRla1JHDc+YY1U52P7eDboCcPswVFB4bn2o9O8icNVsEA53ytLME2jWcPwxUYFzvbFZb8J+ mAPqblC/QWPQwzoP9858XZfafE56POzC6cXQOqFIzz/uMjbQfU9CNLQYSCQVj4qliQcO+G5Y48S EjzajmpSwcXYUippN/L53obzrOmvi X-Google-Smtp-Source: AGHT+IEVtcy4y8HvT3Gl+rG1qbKApJL+4GJj1w/R5n/Zdy1RVU33De3349hw+Oah4lJ9+GRGGApVBw== X-Received: by 2002:a05:600c:1d1c:b0:454:aac0:ce1a with SMTP id 5b1f17b1804b1-454ec128bafmr33199565e9.14.1752240889569; Fri, 11 Jul 2025 06:34:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/36] arm/cpu: store id_afr0 into the idregs array Date: Fri, 11 Jul 2025 14:34:10 +0100 Message-ID: <20250711133429.1423030-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241003982116600 From: Cornelia Huck Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Message-id: 20250704141927.38963-2-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 - target/arm/cpu-sysregs.h.inc | 1 + hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 2 +- target/arm/tcg/cpu-v7m.c | 12 ++++++------ target/arm/tcg/cpu32.c | 22 +++++++++++----------- target/arm/tcg/cpu64.c | 16 ++++++++-------- 8 files changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8cf0ab417b..835700cfab8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1082,7 +1082,6 @@ struct ArchCPU { uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; - uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint64_t clidr; diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index cb99286f704..b96a3588043 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) +DEF(ID_AFR0_EL1, 3, 0, 0, 1, 3) DEF(ID_MMFR0_EL1, 3, 0, 0, 1, 4) DEF(ID_MMFR1_EL1, 3, 0, 0, 1, 5) DEF(ID_MMFR2_EL1, 3, 0, 0, 1, 6) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 6d85720f1b4..d93e593fcba 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1279,7 +1279,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } - return cpu->id_afr0; + return GET_IDREG(isar, ID_AFR0); case 0xd50: /* MMFR0. */ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bd33d6cc6ea..d648ea066c6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -663,7 +663,7 @@ static void aarch64_a57_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10101105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); @@ -725,7 +725,7 @@ static void aarch64_a53_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10101105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); diff --git a/target/arm/helper.c b/target/arm/helper.c index b3f0d6f17a8..ae6231803e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7809,7 +7809,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_afr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AFR0)}, { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index eddd7117d5b..a65b83fe990 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00000030); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x00000000); @@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00000030); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x00000000); @@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00000030); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x00000000); @@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000200); SET_IDREG(isar, ID_DFR0, 0x00100000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00100030); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x01000000); @@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000030); SET_IDREG(isar, ID_PFR1, 0x00000210); SET_IDREG(isar, ID_DFR0, 0x00200000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00101F40); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x01000000); @@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x20000030); SET_IDREG(isar, ID_PFR1, 0x00000230); SET_IDREG(isar, ID_DFR0, 0x10200000); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00111040); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x01000000); diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 942b636aa5b..03cbe42f22f 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -225,7 +225,7 @@ static void arm1136_r2_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); - cpu->id_afr0 =3D 0x3; + SET_IDREG(isar, ID_AFR0, 0x3); SET_IDREG(isar, ID_MMFR0, 0x01130003); SET_IDREG(isar, ID_MMFR1, 0x10030302); SET_IDREG(isar, ID_MMFR2, 0x01222110); @@ -257,7 +257,7 @@ static void arm1136_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0x2); - cpu->id_afr0 =3D 0x3; + SET_IDREG(isar, ID_AFR0, 0x3); SET_IDREG(isar, ID_MMFR0, 0x01130003); SET_IDREG(isar, ID_MMFR1, 0x10030302); SET_IDREG(isar, ID_MMFR2, 0x01222110); @@ -290,7 +290,7 @@ static void arm1176_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x33); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x01130003); SET_IDREG(isar, ID_MMFR1, 0x10030302); SET_IDREG(isar, ID_MMFR2, 0x01222100); @@ -320,7 +320,7 @@ static void arm11mpcore_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x111); SET_IDREG(isar, ID_PFR1, 0x1); SET_IDREG(isar, ID_DFR0, 0); - cpu->id_afr0 =3D 0x2; + SET_IDREG(isar, ID_AFR0, 0x2); SET_IDREG(isar, ID_MMFR0, 0x01100103); SET_IDREG(isar, ID_MMFR1, 0x10020302); SET_IDREG(isar, ID_MMFR2, 0x01222000); @@ -360,7 +360,7 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x400); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x31100003); SET_IDREG(isar, ID_MMFR1, 0x20000000); SET_IDREG(isar, ID_MMFR2, 0x01202000); @@ -436,7 +436,7 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x1031); SET_IDREG(isar, ID_PFR1, 0x11); SET_IDREG(isar, ID_DFR0, 0x000); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x00100103); SET_IDREG(isar, ID_MMFR1, 0x20000000); SET_IDREG(isar, ID_MMFR2, 0x01230000); @@ -502,7 +502,7 @@ static void cortex_a7_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10101105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01240000); @@ -554,7 +554,7 @@ static void cortex_a15_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00001131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x02010555); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10201105); SET_IDREG(isar, ID_MMFR1, 0x20000000); SET_IDREG(isar, ID_MMFR2, 0x01240000); @@ -598,7 +598,7 @@ static void cortex_r5_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x0131); SET_IDREG(isar, ID_PFR1, 0x001); SET_IDREG(isar, ID_DFR0, 0x010400); - cpu->id_afr0 =3D 0x0; + SET_IDREG(isar, ID_AFR0, 0x0); SET_IDREG(isar, ID_MMFR0, 0x0210030); SET_IDREG(isar, ID_MMFR1, 0x00000000); SET_IDREG(isar, ID_MMFR2, 0x01200000); @@ -745,7 +745,7 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x10111001); SET_IDREG(isar, ID_DFR0, 0x03010006); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x00211040); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01200000); @@ -977,7 +977,7 @@ static void arm_max_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10101105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d0df50a2f34..e3183c53bb1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -52,7 +52,7 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x10201105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); @@ -227,7 +227,7 @@ static void aarch64_a55_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x0000000010112222ull); SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); @@ -298,7 +298,7 @@ static void aarch64_a72_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x00000131); SET_IDREG(isar, ID_PFR1, 0x00011011); SET_IDREG(isar, ID_DFR0, 0x03010066); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_MMFR0, 0x10201105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); @@ -360,7 +360,7 @@ static void aarch64_a76_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); @@ -608,7 +608,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_DFR0, 0x04010088); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); @@ -687,7 +687,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull), SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); - cpu->id_afr0 =3D 0x00000000; + SET_IDREG(isar, ID_AFR0, 0x00000000); SET_IDREG(isar, ID_DFR0, 0x15011099); SET_IDREG(isar, ID_ISAR0, 0x02101110); SET_IDREG(isar, ID_ISAR1, 0x13112111); @@ -905,7 +905,7 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x10201105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); @@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_PFR0, 0x21110131); SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ SET_IDREG(isar, ID_DFR0, 0x16011099); - cpu->id_afr0 =3D 0; + SET_IDREG(isar, ID_AFR0, 0); SET_IDREG(isar, ID_MMFR0, 0x10201105); SET_IDREG(isar, ID_MMFR1, 0x40000000); SET_IDREG(isar, ID_MMFR2, 0x01260000); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241234; cv=none; d=zohomail.com; s=zohoarc; b=kGyL+GVxD0h5Cx/x8kcMyu2LYpUHbVRcIN+I6RkAg0TDbLg6ce2BDjO7YIIBWVRK/8i1BWAg4PknkCbxtbcp5zwZC5y+g4dSjU2hftlGd7lpCcyMMdmMMdOfFcvNqXfRcsf7FOX7miJOdcH/Lt0va4T3qCMw+RuzZ6E32dfOL5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241234; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pbjg9RvDfbdG6d500Oq0/a5SPdDZ16+NUzBBz9QOEEg=; b=l5gAyGtcxzqD1iUpJD3dJws6wh7l2MhMKvlEC+FbReGS0GHlI1rwFyAPn+mddeq6pvexYrB1pyZw491fsxWqoYge2kH2OEPujALaLUkMt7AKf1XtQgUAw4cbkUChsnhM8GKmtABXjqVbBoF2prjTkVyra2u/hbo8/XMq+om1DWs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241234693320.0335982346679; Fri, 11 Jul 2025 06:40:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuX-0005JV-J5; Fri, 11 Jul 2025 09:35:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtu-0004RB-Ft for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:55 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDts-00035N-7V for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:54 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-453647147c6so19098085e9.2 for ; Fri, 11 Jul 2025 06:34:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240891; x=1752845691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pbjg9RvDfbdG6d500Oq0/a5SPdDZ16+NUzBBz9QOEEg=; b=X/7C/NmglnHTpnRS3y8SEBmJ5NTGnB36kRa7o40NFO7TFXeR3qj3UuHhQ1LqU55tcs Q612o+rbIIPBgkx/BU4ZU7yOntMKvWRPDhfKcMt3nYNVGzPbNN+8MT+WHkWBFgUMKTsE uwx3eBvZnGyaFcyEZUOTlLB87UYscASgsqrG3bKDR6bxxJLYtoIIQ8Tntgk8LFqefJBO 4U/1kMpHN6aW9iXl/unLZDCAXzJKGpO1UZgxZYTUUDIWkaWeAUZsN3VnDib4OJNOKVgP VKR12oHA7YJKvpN9hEtJGl/OTKdmRW2LzoW/SlWDkZPaWo3/zysL9+Al7UrIQDT7gWpc YGkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240891; x=1752845691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pbjg9RvDfbdG6d500Oq0/a5SPdDZ16+NUzBBz9QOEEg=; b=VMwbUdYtthmsRGXNnz8q8e3rXqbdlndky3xyCV7323lYOngIqN/Gm2yPGwaZ70CgJJ 8TbJ4AIRUbwvwSN2azsVwBn0Z/9IggQtpSNHkGHLm/rh8T30R4LB3VIXHe9e4zo/DOBU hqYFHopkdysl338sgGWBa1xJUyHoAXNq9PaeB1NjtKgNQygE+FcYpI0xG5aUZY4mSbgJ KCm3FC0NHig6Li4OhEC4WAMs72olem3STrYbo1rvSmRxOK3R81FevijJbIohLqbJ4gRn tT9x4DsRhNlESdTTx7V2v4U5APZMooN2tG05mdPztpHVdfqF74SoDXF2htapWIHAEcn1 iMqQ== X-Gm-Message-State: AOJu0Yw0xokg6QfEB8BxinAfXoCTwvfVpc5V3lhFa0mT/kRoDEl6wklO ec0gAcP3Kfy+HwoAQL9y/fkNKDaQTZDn99t90zxqEC8JIRwtxFs69Kw7hXTjWniWgEyvJGuRk2S R2BZ0 X-Gm-Gg: ASbGncv0mfPTrYKci0q6eqDI2X8/79W7hVVq9UiMFS4nur9c6NHhOziYh0HndYjPuLs gGJWV7U/Q0UDxcyN45aqe/vYNBFfwLyA7n11gQ4dM1wI1Ggc+y/NFEcjeDHNITtUD9Zk6lQUiAS 0R0wHKHVRoXeE9PHHREk2zadyjZsD29HV+njaCVtQXzqnpfPRaahpJ7euejWZLqgtHouko1uGn2 XE1P/RENDDWh2ajtNXgyDJKFxgqSUa4TwLaG8tMyEfdrIo29R1I1NE3eKTCSBTx+zt2xxBLAgmu xOcQpQzFqVSwZfSVp9xv9ulGoECint9mFl/3nLF1G1dkFTvh9vBhpYM//PW+zVTSvifybKx84P9 kCPdcQrt1ipZbBSlNDrNGXZEwxduJ X-Google-Smtp-Source: AGHT+IHv3x8qLBs9lv511hYGEUMvfHkuVCjiV3SxFDca1cQAxy0u8wFIX9Vf0BO9bLN3QrULRQbu2A== X-Received: by 2002:a05:600c:1c95:b0:451:833f:483c with SMTP id 5b1f17b1804b1-454ec133982mr33710275e9.7.1752240890546; Fri, 11 Jul 2025 06:34:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/36] arm/cpu: store id_aa64afr{0,1} into the idregs array Date: Fri, 11 Jul 2025 14:34:11 +0100 Message-ID: <20250711133429.1423030-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241235159116600 From: Cornelia Huck Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Message-id: 20250704141927.38963-3-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/cpu-sysregs.h.inc | 2 ++ target/arm/helper.c | 4 ++-- target/arm/tcg/cpu64.c | 16 ++++++++-------- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 835700cfab8..008e5305782 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1082,8 +1082,6 @@ struct ArchCPU { uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; - uint64_t id_aa64afr0; - uint64_t id_aa64afr1; uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index b96a3588043..44c877245ee 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -4,6 +4,8 @@ DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) +DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) +DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index ae6231803e1..93da8f170ea 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7987,12 +7987,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64afr0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64AFR0) }, { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64afr1 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64AFR1) }, { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index e3183c53bb1..3a65d3903bf 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -428,8 +428,8 @@ static void aarch64_a64fx_initfn(Object *obj) SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), - cpu->id_aa64afr0 =3D 0x0000000000000000; - cpu->id_aa64afr1 =3D 0x0000000000000000; + SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000); + SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); SET_IDREG(isar, ID_AA64MMFR1, 0x0000000011212100); SET_IDREG(isar, ID_AA64MMFR2, 0x0000000000001011); @@ -676,8 +676,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0xb444c004; /* With DIC and IDC set */ cpu->dcz_blocksize =3D 4; - cpu->id_aa64afr0 =3D 0x00000000; - cpu->id_aa64afr1 =3D 0x00000000; + SET_IDREG(isar, ID_AA64AFR0, 0x00000000); + SET_IDREG(isar, ID_AA64AFR1, 0x00000000); SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), SET_IDREG(isar, ID_AA64DFR1, 0x00000000), SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ @@ -927,8 +927,8 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ SET_IDREG(isar, ID_AA64DFR0, 0x000011f010305619ull); SET_IDREG(isar, ID_AA64DFR1, 0); - cpu->id_aa64afr0 =3D 0; - cpu->id_aa64afr1 =3D 0; + SET_IDREG(isar, ID_AA64AFR0, 0); + SET_IDREG(isar, ID_AA64AFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */ SET_IDREG(isar, ID_AA64ISAR1, 0x0010111101211052ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); @@ -1029,8 +1029,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */ SET_IDREG(isar, ID_AA64DFR0, 0x000011f210305619ull); SET_IDREG(isar, ID_AA64DFR1, 0); - cpu->id_aa64afr0 =3D 0; - cpu->id_aa64afr1 =3D 0; + SET_IDREG(isar, ID_AA64AFR0, 0); + SET_IDREG(isar, ID_AA64AFR1, 0); SET_IDREG(isar, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto a= nd FEAT_RNG */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011111101211052ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241345; cv=none; d=zohomail.com; s=zohoarc; b=EyCSL0DBdDSjmUPYJHnGnrj84Y8f88hAmCJONXgo55UdOmjzmv3E5gVltAoE6bUuOLY1A+myXVbzS+muU/vkYYL3La6g8zZapS+skaauRgG/tA7+ttLBmhpo73icLVgvF/eGBtpf+Tnf+V+mfjTxGFCbIcxU0Qoi6y4j1ZCgrvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241345; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=fnzvogd1uSvEdf0/LpDdDirPBucDnCNCJdSSizExPTI=; b=ibWxdEIq/Rz4z8zQIt2VCbRoYcUBrYCHKfN4fkZjV6z3vkdbPFItUHHVQl+w3vdFLvTs3lD/48N+MkSAwO5Yg+qmnlbuzsDufOWBWY3402Sjng2J1peOZB15uj79vPPbNro5cui3HP7JWuv/9x9VmASCdrMKkIey1NLYp6DJw7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241345064925.2151968333793; Fri, 11 Jul 2025 06:42:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuZ-0005N0-1U; Fri, 11 Jul 2025 09:35:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtv-0004RI-9E for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:55 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtt-00035t-G0 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:55 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-455b00283a5so3370235e9.0 for ; Fri, 11 Jul 2025 06:34:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240891; x=1752845691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fnzvogd1uSvEdf0/LpDdDirPBucDnCNCJdSSizExPTI=; b=Is9Tp8DejD5H30qLQgftsm0Z/DzMoUQntnz6S0gIJcVTn3HXHf5po8YKfvubdo3t8n QhdiXrnyZU0vtxsKnKCZ2DzrIeNmfpiK609ah0KygBWHTykbtolt1Hb/xMNwP5QIjGxy oUzx4cRU5vy6Jqs7y3PF9hRbyBmusnrVRsfWmySFcvCXJxJuPUM6u4p515dfdv6qI4AF oUfwTwIa/kXIi+QzvWOrh9NU+bZTcb/5D0+oQePd1p1Bt4tO0AtRZ+qNSv2PeLOXJq7u pvFOU6OTeblHKbieM8a+bm3SLOA1LZ2tuQqaLy4cB2TyBNCxkxBrwcKSm0VRgxtlkEfq lJhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240891; x=1752845691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fnzvogd1uSvEdf0/LpDdDirPBucDnCNCJdSSizExPTI=; b=nvhhTh8RdfseMs+7u3bLblKusaYKkG2ev58u8D3R7CwDvUfEQ6UE7juwuzAwMIFYZf u3NwSMC11CVbXugLxL//OnAPeevydn80lXNSZlHWkfbBsdWaZardarScJbN11zqZtHhg WMX+YFccAomQiOkZZqI62ZvhrynK2dy+2BUz7TGiwpj98ez8nDMTg5R4vRDS4uBBkcky CK1a4WsHPAUIox3Xvd1IsoyfnhSzd7TXN/aBwQaZYSw7rVcEnTdTYhzd44g90b74lh6E IyKYMsI0tmMRha8FJzRaDPnr7Kc1g0LL85d+crghQiZX6Ff9E+yj/j85wes8PmeQ6OK7 szMw== X-Gm-Message-State: AOJu0YzGQ8YqIpI/ynAk2jgfuoRCa0Yo8ZBj6xvXq6As7rU/oszVBTqp JyM6fxHnCgj2rsa1B6pPibi8f59mxEmpyGClzn+2rC2YPJPugYtMWYCn5f9E82gaPqe9lDZaRB1 rrw8q X-Gm-Gg: ASbGnct3f/mRFUul6Wbvjw91mSjHGqbAyxxksPjf1eTIaRldI17fXxU6yxNvVcorSkh A7whBOZZADktPl8LEXb7A6dUtTqFWRTyv+9pFCXjGfb10vDJVcaXMymvPMIjLela5J/IMrCrLis cRiVzAZ1YOuf0l+JRr/vqZKEB2iT/E6X7LK/GNv/OkJGpUyIUoPrptUYbJ9yBiMGbUUDmWMoTI/ ts0wUSIbDUtdFX1mCyUzW48Rz1mN3GNWUX4ZCs+QldyzlCaiYusg/2qlp1n/yYzkG2OorqJXViD x5fV8nS/g0g6eeMSi/XjPeBHbNk0DzOOT+PhLTJGwk9jCPHeSIYMk8GTrFXlxY+q0iqkxxOnzVw rgnUhT1WKQqfQKaijOdtlR4TxrjVQ X-Google-Smtp-Source: AGHT+IGzcXA3lMsM+9ouXeJu3D1hElHuhjfDIdEei8Vuh0fHpID423iCzgnUXJHlSJXIgSz9ukNgxw== X-Received: by 2002:a05:600c:37c9:b0:43d:b3:fb1 with SMTP id 5b1f17b1804b1-455e7b63b8emr22499435e9.27.1752240891532; Fri, 11 Jul 2025 06:34:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/36] arm/cpu: fix trailing ',' for SET_IDREG Date: Fri, 11 Jul 2025 14:34:12 +0100 Message-ID: <20250711133429.1423030-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241346808116600 From: Cornelia Huck While a trailing comma is not broken for SET_IDREG invocations, it does look odd; use a semicolon instead. Fixes: f1fd81291c91 ("arm/cpu: Store aa64mmfr0-3 into the idregs array") Fixes: def3f1c1026a ("arm/cpu: Store aa64dfr0/1 into the idregs array") Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Message-id: 20250704141927.38963-4-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/tcg/cpu64.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 3a65d3903bf..bcc8e2dfafa 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj) cpu->clidr =3D 0x82000023; cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; - SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull), + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); SET_IDREG(isar, ID_AA64ISAR0, 0x0000100010211120ull); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000100001ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101122ull); @@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->reset_sctlr =3D 0x30000180; SET_IDREG(isar, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions= */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000000); - SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408), - SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000), + SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408); + SET_IDREG(isar, ID_AA64DFR1, 0x0000000000000000); SET_IDREG(isar, ID_AA64AFR0, 0x0000000000000000); SET_IDREG(isar, ID_AA64AFR1, 0x0000000000000000); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000001122); @@ -678,13 +678,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize =3D 4; SET_IDREG(isar, ID_AA64AFR0, 0x00000000); SET_IDREG(isar, ID_AA64AFR1, 0x00000000); - SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull), - SET_IDREG(isar, ID_AA64DFR1, 0x00000000), + SET_IDREG(isar, ID_AA64DFR0, 0x000001f210305519ull); + SET_IDREG(isar, ID_AA64DFR1, 0x00000000); SET_IDREG(isar, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG= */ SET_IDREG(isar, ID_AA64ISAR1, 0x0011000001211032ull); SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); - SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull), - SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull), + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0220011102101011ull); SET_IDREG(isar, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in = later */ SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000020ull); SET_IDREG(isar, ID_AFR0, 0x00000000); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240955; cv=none; d=zohomail.com; s=zohoarc; b=K4VrP6miKYo1+uZvIONTdaxSP/OTEcZYvh7fhTs2OOdXVdwQEr253YUoPU5sNuCan2OuB0/h9VBpcgucSW5+8Dwzj1lGYiXcgc4dXQPE75a3QXZBhTn+Dh1RT4wZO7SM4F94wE8IJU+lzogJvcUxT8nN9rUzttSzs4KeDubgHz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240955; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=bZjsPWCU7T+wQ5ALI5V5Ak+8ebHq2WSUGtHgALDJm24=; b=Mcmb7ovwdfXz0vOtAYMUxlUNAwTdU/fE1o/WzNe2f/emhJQSHxhQxcOQDs81hc92HEgvRBK3O45RVN3Ex4FDgGEdiMU8sQrRgGc4pzKaob3VeGl+0wu9apHmI7LmzbmLiPpOmvU8+/i1N4U1N5OVu/r495FixqgyO7voWk9WDbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240955906497.9416350196368; Fri, 11 Jul 2025 06:35:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuh-0005iJ-LV; Fri, 11 Jul 2025 09:35:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtw-0004TN-Ma for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:56 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtu-00036W-8x for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:56 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4555f89b236so6492975e9.1 for ; Fri, 11 Jul 2025 06:34:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240893; x=1752845693; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bZjsPWCU7T+wQ5ALI5V5Ak+8ebHq2WSUGtHgALDJm24=; b=NAcUkbwpuzporpFilVbqG7cXsU3lfSRrCdyOgOZgjL0gIzatIbDhHsu742NvoJ6Cg5 jLNOd0h6TW0bZkm4FL3/Cy8MgvzHtYgiNe7PXcoACWpowsTBp3H/VJtLLr5rfMKjgIsx ffE5aEiPTtfqlR2uSmRz/stZFZTUvEU/E4DZk9iAinaxjVWCNHUj/0T3qouyMWXJzrnK wwHn7cDmKXLBc1RCJb/usNIvOkv3PaBZjVxLp1qL/waSmUHiQoe+Z15kFJdxKFLbjwcj dOpK+ikLPDS4PG1MeJmubAvME/pZnTVokwkrIClpPfw1VLbowJ5A0MdamaK+7ailOO59 XN4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240893; x=1752845693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bZjsPWCU7T+wQ5ALI5V5Ak+8ebHq2WSUGtHgALDJm24=; b=EPgqyFfVY8JpZXxT1PBd61PCoDebmbdvNkAo6E2td4301Y/QGCaFPvB0TLweg+HXfB D4tIKtMJ0fnKcnycIR7WFr2vCg/SmIENpyXDANvcgtgm8xHPQepi8XmIGD+Ijfbl/51b LL4r9jbEWgB+c4K0uOLfJurD/fpegioNLWCfVagM3KxTxdoZRqBZBPppk2BKJLjo2FfT k5fQwq3p/HIpTEe6NCBRe7eaO72H6mXG1U9N45Fx8L9/TS84dIpdXj9a2TXg4gGcVqAK 7MIqPan2vYXQ0BGpgcEzOs50l63kMK/zxkh1BMr/tl0LHXWRxi1l5uROFComGsADBB16 14lw== X-Gm-Message-State: AOJu0Yww7GyHo+3uxZLGCdrj5eSXZBlTgBqvBLWHDl+IrrC+5a2bWXpt MvFHequld830yPqQsdto7HDzEcLnp8kcPS0WyO78f4pt0pqL91FM9FtlsD48sZpkfHhYbWhwNTC DkbdL X-Gm-Gg: ASbGncsLJ8H+0eo77ipLYW7um+FtMVa1A8/n3TX9kQKDedZpodpidvBo+L8q4P7X8pp kAiGlIdyt3FKBKVZ0dAOZmm1MdW4CA+aK6kCXwPBfLZlj0b5lcJ6rTUA6jpgGaP9l6HlrKI0Bcm 99P+0nqNlAiFVF6eGx1dCoPB7zPKUnpPnjL4M/oPidjSaDiUNQJLtNB2rKmd5aK7cl58Ah/Uxz8 33C3Yfe1SpO63OkFFtNSnGmYn3ijA0077QrFCvKz/rsfpFqAIBWaYXzPnUmhhn+9wVpgtmoI0Ic jEFAgct7KnD7gM05G7GTIr7eLT/W4BfH7fF+NXBDJl4dJ4VTl93zO1Cmt4W7lB1S8B2u9SkATV6 rHWV068+W6+n3WbVkXh3zGxtO8Jhy X-Google-Smtp-Source: AGHT+IG35R2imiTJYLfwfTBRsBH5TpQCj/IhYT0yVLDnkoEFzy6ZX7f84TOASs/hCh0OeUng/zuzZw== X-Received: by 2002:a05:600c:4ed0:b0:453:5c30:a2c2 with SMTP id 5b1f17b1804b1-454ec15ee1emr31768485e9.8.1752240892562; Fri, 11 Jul 2025 06:34:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/36] arm/cpu: store clidr into the idregs array Date: Fri, 11 Jul 2025 14:34:13 +0100 Message-ID: <20250711133429.1423030-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240957402116600 From: Cornelia Huck Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Message-id: 20250704141927.38963-5-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 +-- target/arm/cpu-sysregs.h.inc | 1 + hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu64.c | 4 ++-- target/arm/helper.c | 2 +- target/arm/tcg/cpu-v7m.c | 4 ++-- target/arm/tcg/cpu32.c | 12 ++++++------ target/arm/tcg/cpu64.c | 22 +++++++++++----------- 8 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 008e5305782..dc9b6dce4c9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1082,7 +1082,6 @@ struct ArchCPU { uint32_t reset_sctlr; uint64_t pmceid0; uint64_t pmceid1; - uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. @@ -2945,7 +2944,7 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) /* If all the CLIDR.Ctypem bits are 0 there are no caches, and * CSSELR is RAZ/WI. */ - return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) !=3D 0; + return (GET_IDREG(&cpu->isar, CLIDR) & R_V7M_CLIDR_CTYPE_ALL_MASK) != =3D 0; } =20 static inline bool arm_sctlr_b(CPUARMState *env) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 44c877245ee..f48a9daa7c1 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -35,5 +35,6 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(CTR_EL0, 3, 3, 0, 0, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index d93e593fcba..7c78961040e 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1331,7 +1331,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return GET_IDREG(&cpu->isar, ID_ISAR5); case 0xd78: /* CLIDR */ - return cpu->clidr; + return GET_IDREG(&cpu->isar, CLIDR); case 0xd7c: /* CTR */ return cpu->ctr; case 0xd80: /* CSSIDR */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d648ea066c6..26cf7e6dfa2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -683,7 +683,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; cpu->isar.reset_pmcr_el0 =3D 0x41013000; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); /* 48KB L1 icache */ @@ -745,7 +745,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.dbgdevid =3D 0x00110f13; cpu->isar.dbgdevid1 =3D 0x1; cpu->isar.reset_pmcr_el0 =3D 0x41033000; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); /* 32KB L1 icache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 93da8f170ea..3ea9958ea7a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7889,7 +7889,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_tid4, .fgt =3D FGT_CLIDR_EL1, - .resetvalue =3D cpu->clidr + .resetvalue =3D GET_IDREG(isar, CLIDR) }; define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index a65b83fe990..dc249ce1f14 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -195,7 +195,7 @@ static void cortex_m33_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x01310132); SET_IDREG(isar, ID_ISAR5, 0x00000000); SET_IDREG(isar, ID_ISAR6, 0x00000000); - cpu->clidr =3D 0x00000000; + SET_IDREG(isar, CLIDR, 0x00000000); cpu->ctr =3D 0x8000c000; } =20 @@ -233,7 +233,7 @@ static void cortex_m55_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x01310132); SET_IDREG(isar, ID_ISAR5, 0x00000000); SET_IDREG(isar, ID_ISAR6, 0x00000000); - cpu->clidr =3D 0x00000000; /* caches not implemented */ + SET_IDREG(isar, CLIDR, 0x00000000); /* caches not implemented */ cpu->ctr =3D 0x8303c003; } =20 diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 03cbe42f22f..a2a23eae0d7 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -371,7 +371,7 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_ISAR3, 0x11112131); SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; - cpu->clidr =3D (1 << 27) | (2 << 24) | 3; + SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3); cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ @@ -447,7 +447,7 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_ISAR3, 0x11112131); SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; - cpu->clidr =3D (1 << 27) | (1 << 24) | 3; + SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3); cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ cpu->isar.reset_pmcr_el0 =3D 0x41093000; @@ -519,7 +519,7 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.dbgdidr =3D 0x3515f005; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ @@ -567,7 +567,7 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.dbgdidr =3D 0x3515f021; cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ @@ -758,7 +758,7 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00010142); SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; - cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; + SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3); cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ =20 @@ -990,7 +990,7 @@ static void arm_max_initfn(Object *obj) SET_IDREG(isar, ID_ISAR5, 0x00011121); SET_IDREG(isar, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index bcc8e2dfafa..35cddbafa4c 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -71,7 +71,7 @@ static void aarch64_a35_initfn(Object *obj) SET_IDREG(isar, ID_AA64ISAR1, 0); SET_IDREG(isar, ID_AA64MMFR0, 0x00101122); SET_IDREG(isar, ID_AA64MMFR1, 0); - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); cpu->dcz_blocksize =3D 4; =20 /* From B2.4 AArch64 Virtual Memory control registers */ @@ -216,7 +216,7 @@ static void aarch64_a55_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; + SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->dcz_blocksize =3D 4; /* 64 bytes */ SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); @@ -317,7 +317,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x2; cpu->isar.reset_pmcr_el0 =3D 0x41023000; - cpu->clidr =3D 0x0a200023; + SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); /* 48KB L1 dcache */ @@ -349,7 +349,7 @@ static void aarch64_a76_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; + SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x8444C004; cpu->dcz_blocksize =3D 4; SET_IDREG(isar, ID_AA64DFR0, 0x0000000010305408ull); @@ -436,7 +436,7 @@ static void aarch64_a64fx_initfn(Object *obj) SET_IDREG(isar, ID_AA64ISAR0, 0x0000000010211120); SET_IDREG(isar, ID_AA64ISAR1, 0x0000000000010001); SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); - cpu->clidr =3D 0x0000000080000023; + SET_IDREG(isar, CLIDR, 0x0000000080000023); /* 64KB L1 dcache */ cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); /* 64KB L1 icache */ @@ -597,7 +597,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by B2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; + SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0x8444c004; cpu->dcz_blocksize =3D 4; SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); @@ -673,7 +673,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMU); =20 /* Ordered by 3.2.4 AArch64 registers by functional group */ - cpu->clidr =3D 0x82000023; + SET_IDREG(isar, CLIDR, 0x82000023); cpu->ctr =3D 0xb444c004; /* With DIC and IDC set */ cpu->dcz_blocksize =3D 4; SET_IDREG(isar, ID_AA64AFR0, 0x00000000); @@ -934,7 +934,7 @@ static void aarch64_a710_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101122ull); SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); SET_IDREG(isar, ID_AA64MMFR2, 0x1221011110101011ull); - cpu->clidr =3D 0x0000001482000023ull; + SET_IDREG(isar, CLIDR, 0x0000001482000023ull); cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x000000049444c004ull; cpu->dcz_blocksize =3D 4; @@ -1036,7 +1036,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR0, 0x0000022200101125ull); SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); SET_IDREG(isar, ID_AA64MMFR2, 0x1221011112101011ull); - cpu->clidr =3D 0x0000001482000023ull; + SET_IDREG(isar, CLIDR, 0x0000001482000023ull); cpu->gm_blocksize =3D 4; cpu->ctr =3D 0x00000004b444c004ull; cpu->dcz_blocksize =3D 4; @@ -1125,10 +1125,10 @@ void aarch64_max_tcg_initfn(Object *obj) * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,= LoUIS} * are zero. */ - u =3D cpu->clidr; + u =3D GET_IDREG(isar, CLIDR); u =3D FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); u =3D FIELD_DP32(u, CLIDR_EL1, LOUU, 0); - cpu->clidr =3D u; + SET_IDREG(isar, CLIDR, u); =20 /* * Set CTR_EL0.DIC and IDC to tell the guest it doesnt' need to --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241231; cv=none; d=zohomail.com; s=zohoarc; b=FvKvWGSjOZg93GrBChTGodd3XRbYmvWD/0DnRVUsgps2QxPl7QHkavoqEvbnuwKlyzA4LMjqwZwlEEgB+ngJTcCgPfgX6FTyczfcPnElPufP7Yg6FWcQm152BJGN0mgbueUWvalR2F7Bxu3DismIr87RNVWbNlpQhOm1lzUHunk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241231; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4D1P721eTGF05yoXPAl8RR3ddO38S69UMpsn5Oq3Ffc=; b=LdXngPVch0oA6LJH49J9xFCG+fIclzew8Wo9oh1SqvqQmFznEYuGyrFX5iqJg2k2H7n4PrkxPxzTdUbuZjrvfL3984O2rWyrOP67696dDm6rPvN3q/oEzI66rOeKhovp/3kUixhq6df3gPGJ47pC8+I5Z26JCWj14u5VUDdD+U4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241231186246.94319604726297; Fri, 11 Jul 2025 06:40:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDup-00061d-8X; Fri, 11 Jul 2025 09:35:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDtw-0004TT-PM for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:56 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtv-00036v-0h for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:56 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-455e6fb8057so6306635e9.3 for ; Fri, 11 Jul 2025 06:34:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240893; x=1752845693; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4D1P721eTGF05yoXPAl8RR3ddO38S69UMpsn5Oq3Ffc=; b=TAACE78ByWO7m02I6UVpGHdeEcvFbCJLtjYOjw0yuHOq7vCAasGFUzCCmdGvFGr34L 7SA5/DeV2ThRyCQHjWy1cK8Bmdu0DV1of/OfkX2wMovYFqCiovl4NUohlMwJcrf7HpC6 anR69RA57IG3RBzwb/ot3Oo5d/VIpG7kvjAwksQBoi5PM+N8h1bw90bcMmGswyFoGzKP hyQ1PoHD5gTQA5vRJeI1M5HiBXZnyovgqo0Bm+9bEdMEZf6qilfiGWtFo6ZEovDkC9O4 zbXKwfUT9+23v4QNlRPiqW0jSJnZxJAZIwYAhdpfBnWFSpOEkAzuCw7J1Zq6Zf9YWRvc FJXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240893; x=1752845693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4D1P721eTGF05yoXPAl8RR3ddO38S69UMpsn5Oq3Ffc=; b=QtkRvXsFzsdtUJwjAt4/wNfOGjdIZZqqUDvKHlkmyEdLO18SFjDXENhI6rxu6qvJIR Bqj/KngGawz4Rek6k5J0rBwHfamrmhxHlVwVs6zDj/rqJeqCulpb7/Kjxdsc6U7cK9Js ap+SGhGZTDvKdyjXdKC5ommlhEGCHv893/u1wzaSQutYlVtZej3A+zxGa+1umw7tw3fC UZH939RQupQkDfdT+lD52eEQP3T1HKVETwzjmWUPQxeEv9A42WwQf8IcIliod3IU1Kuv rpoggo42tk9DKnNnZSCy707FUn8Gje1D16Rh98NMMg8E6G5q9nRghIY2BjgSBZX4LgFY jLmA== X-Gm-Message-State: AOJu0YwqIKp5MUnsdIIET0T2nqMfShIzicQh5KueAVr2qFgXdBgFFzK9 siUE9FGcpAKOqtbJOZ+/8GtWUlgdTXFoKMuV5lTXjzIARNktnScj59zBYE2WOFKPLulkH8MbPVx KfyfV X-Gm-Gg: ASbGncuEqoMyzs60uQUh0d12jx/RL/rMsDzmy/ckTyhM1tMBwyfjhVsiSqr14TO0mUO HsEwj0gqrpurlkuoxby7YIUTA3AV0L5NQkFQPxIh5tTL3PnNK7xxjEwo8cedS02QBgZygdeJZzH cqFsE3oFYyD8K6XmpsoAOoy59dQvD18MnDpSbNdWoE+6NbMZswqZZOMY8aqZqgi5YPSQsypekPm AGCEx23ovkaO4pt7IIf7qA73dm6TD9zEW8ciiDz2mxcB8N1jnHXk4oqvdQxI5Y0ItVi4HfYgXkT I4NdoU9O90T+pcNKreFLWrfGKtu+arCxwwCaRvF/q0HHq8lcdrJFp2ALSSmRkGFRNypqqzudV9H KmOTRarNigRB1HZ1dq1Vl7teKLVFO X-Google-Smtp-Source: AGHT+IFoGT7AtPo6/0JtV5y3fUeCo/3/9cENyDQkJE4KusBCMXFJhtyA3D6mBCqpHHsLHpTppfOv3w== X-Received: by 2002:a05:600c:3e0b:b0:450:d04e:22d6 with SMTP id 5b1f17b1804b1-454e7b603b9mr28157485e9.7.1752240893458; Fri, 11 Jul 2025 06:34:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/36] arm/kvm: shorten one overly long line Date: Fri, 11 Jul 2025 14:34:14 +0100 Message-ID: <20250711133429.1423030-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241233176116600 From: Cornelia Huck Fixes: 804cfc7eedb7 ("arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arr= ays") Signed-off-by: Cornelia Huck Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Eric Auger Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250704141927.38963-6-cohuck@redhat.com Signed-off-by: Peter Maydell --- target/arm/kvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 426f8b159e8..8ab0d692d36 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -230,7 +230,8 @@ static uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sys= reg) } =20 /* read a sysreg value and store it in the idregs */ -static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, ARMIDRegiste= rIdx index) +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, + ARMIDRegisterIdx index) { uint64_t *reg; int ret; --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241342; cv=none; d=zohomail.com; s=zohoarc; b=eJBmUaFH4k0BYNodkr31roiqX9a11WB8dc/LVHMbaA+daMX0DMKxg8ybyXV8HcJsb060QWo/MTW/pUyJBkhBQSZ04g0mzc/4EPWTzk03+B8OZBe5ZGO/dmo9ATAJoVQZKMnuHRE33pOVLqy4zqUHTCN7Rcw5QSFWH38Z64qrHgw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241342; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3RKupyWJCQDDIhOP+u0cTCBpDLfFp7iJSn/Hu9Aqtmc=; b=go/cVoCEChlvlq+JxDdc8h0akZhUEg6EGhNNa9Q4bjILh+Y7m6MITw8jfvo2eMoT87+FV4Y2clTOp9F1hV6gneeR+UesYQDVswb+cCEbYTU39qWsY7RaOILVQoqf/5n4mV7/CmuReEAjA7I2Jp0pVZB7PJobFa+R/i2n9w8vwKI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241342588523.8753036467585; Fri, 11 Jul 2025 06:42:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDv7-0007En-EQ; Fri, 11 Jul 2025 09:36:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDty-0004Ui-3C for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:59 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtw-00037U-8M for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:34:57 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-454df871875so6293355e9.0 for ; Fri, 11 Jul 2025 06:34:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240894; x=1752845694; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3RKupyWJCQDDIhOP+u0cTCBpDLfFp7iJSn/Hu9Aqtmc=; b=oPy6mtOTPKk+gc8s2ThS2fJyFF1q5QR700o+nrc/0yiV0hfGX98Z1x37dDOw2VhQDx RRew3mRjR35gGfgbvSGaeuwhQ79NidrcSPwsuXlBpTk8NgTRAyn6Np719Xi894BFroLY hEzBoKEB4wiViEItcqFyT8kqdXcOYcWDWWuondOcvcCD7q4fYhUW0rdrl5VCnMD0V/TB /1GRjyVh3EFJYtM2u3R8MP+iTeN1pRYv/7izIRgtdAnYqSqu69A3LXfB1kT3lIjpT3PH HLba82rSrBbtpIpPMVs9fYF0gqRRQO1LAV6FXW7LVSJh3AVIl6pZjvFmM5JEsAFm4noZ aPUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240894; x=1752845694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3RKupyWJCQDDIhOP+u0cTCBpDLfFp7iJSn/Hu9Aqtmc=; b=Kguri3ZOpYlRyzOopzQrSwWASEAvmJsZbClJ9EpjQ6iowgAaiLO01+eCrMy9fCWOob 0xkY0mlqWEhjkBjdEI03Mmg/ytp3smrbj+PAoB+s1YnGrBzkj8sFm1GwxSoqtlIaCXFG 8c01FvxuyaECx8f3nd2UVqlia8zX9Pr2ddTu4dGfOscYkyZOTLNJQq6GuKvC1ai0M92e CUL+8ZU5GaX7IYDU6ReVPBUk8ATW58m0Y1UHJlGsL6YPohAK2pNGPqK92otYHwYXgrtw WJeqyUeP0yfdP6v1bJjYbq68FXfDlLvPdUGpSnamkSrpORw8FE9CM99WZc7hu8VXLqSa xXCw== X-Gm-Message-State: AOJu0YxKSZjsr4RDL5G5jR/dkTS1ZJtVy0mDK3WsHS14UxzWhcVHvwc0 mNoD5m/AOqYfyu348/BjRiaS+1Y2vRy9WeM+1pj+rpMV+3CQ7x6j7UCS31gcNrpNVUycovuRrva DR9tL X-Gm-Gg: ASbGncvFeMDJizwabr1GOd9Y/yZyIkiTc/6BsAfHkAsnQO7P3pylnY86kq752htvvAU pJGoDQnmbEaRjc63Bf16Ohgdu1cLa5OQCdAeSP+BVQnBNgIWeOvnBgT/xQ26BJFzfSjzfni73Jo Ftrcf6rsVtHVHdziGq1Ng2N5qhDW2FJt98oDfBLMUxyXairVntVuyzRejcDSBtUVWPOkXrwERQK 3mEzu7TrnhkJVuNcpNpn8i2uJ2HFcQUqZ86XpUozflTt1CxQtdbqaPB1+5+bfrNvk74PqveTbZk eir0ztc16PcrqGG/yn9NfdIWFhQ5jkvLFc+X4cvVcY4HKnCG1Zjw8Ym27zxduvmM4gPD938No2R AGaorvOtLXaUL1droiuMpCokxeKxt3+oGCng8cwA= X-Google-Smtp-Source: AGHT+IHrZBBK9jSnP0CSqbt2lXJjpcFhAxVYfC6d4YNAC/Fo8ODbs6TsXAao6jIJjRdY6YHZM6YOAw== X-Received: by 2002:a05:600c:1d8b:b0:455:ed48:144f with SMTP id 5b1f17b1804b1-455ed4815f8mr20753175e9.14.1752240894434; Fri, 11 Jul 2025 06:34:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/36] target/arm: Drop stub for define_tlb_insn_regs Date: Fri, 11 Jul 2025 14:34:15 +0100 Message-ID: <20250711133429.1423030-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241344886116600 From: Richard Henderson Allow the call to be compiled out by protecting it with tcg_enabled. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250707151547.196393-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 +++- target/arm/tcg-stubs.c | 5 ----- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ea9958ea7a..c1b684e3d1c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7771,7 +7771,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 #ifndef CONFIG_USER_ONLY - define_tlb_insn_regs(cpu); + if (tcg_enabled()) { + define_tlb_insn_regs(cpu); + } #endif =20 if (arm_feature(env, ARM_FEATURE_V6)) { diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index 5e5166c0490..aac99b2672a 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -22,11 +22,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, g_assert_not_reached(); } =20 -/* TLBI insns are only used by TCG, so we don't need to do anything for KV= M */ -void define_tlb_insn_regs(ARMCPU *cpu) -{ -} - /* With KVM, we never use float_status, so these can be no-ops */ void arm_set_default_fp_behaviours(float_status *s) { --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241035; cv=none; d=zohomail.com; s=zohoarc; b=BAvw/UrUBj/Kq0LCEC1eAQvMFcyEsfsyIhFtWQD9kNyWWYLFRo/QP9OwRAa9q34U8F36ZfQHguibjIZt25tVBD6lsmY9s/FGJUGbdPnYee0FOJ5AYtaZM2XT8RK3vUe3zIp/vRAznpdDX+kCYeMXrwGCPngZU/+iNVxL7bJmt1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241035; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dygIx0j1OHWFx1U7iSU+E/yVGwrrZIOhF+fnTVlAKlc=; b=lB2srtV7HWFvDbx+qm4IGXOVSa4n79RZgPsKzXdUzfz0Q73hUC+DN5cEZASbAJykn8w30O3YL+kh9+UbxBrQdwqPBnSLunc9OZ8Gvs6wb5nnnJkngP8S6DRb/iY+KXUv/SkpTUEzICpEmsKsy1NqjptxKbNcvbkYdi3EDFt6sKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241035864272.46269644347797; Fri, 11 Jul 2025 06:37:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDui-0005jY-KY; Fri, 11 Jul 2025 09:35:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu2-0004Wn-3Z for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:04 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtx-00038P-L1 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:01 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3a582e09144so1375057f8f.1 for ; Fri, 11 Jul 2025 06:34:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240896; x=1752845696; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dygIx0j1OHWFx1U7iSU+E/yVGwrrZIOhF+fnTVlAKlc=; b=uc/SzQsIFDwgEaC1T9p47qPTH+si8US6xbwPqB4vpuIADD5B4Hw2cMuGBunjW3rUyz fa5zzzYFCTfgLmfd/IXWicFEjY6X/yypPVPrOQVjWFZRCtYKogAcZz3aBVIzhFQbJZnx ECjPj0qCzq2K9ARTjSveBylMWtm6w9cEbhzzzIzPu92WRZeoq7Vggz5PjqTI1RIWY0O2 JcuGfLv5jxdND8xnJOeAJWib6U3wlYx/JRWL022G0Z9mzRSJmkMg7adDvWFbFAYF+jj1 LBePJaABnJdKv76uirjJHTKnASsz6YDmrw+wavXYZpo3RMgOVAuFEVDBM6utiWhBf9Pb 6Q9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240896; x=1752845696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dygIx0j1OHWFx1U7iSU+E/yVGwrrZIOhF+fnTVlAKlc=; b=kBBG5Sx0d2xIeCib5g3BMUgqZ9VRdRmgB27VqXGWo7sl7P0o7OVqiFbBpyEUt7ZDWl Nx5Cwlsa8bq2ZR6ift3Dlc1fFjjTrVpPi4cb8X5P8NoJ/V6GQpPiy7jltFA3HZsDgj+L 4KTU1zswRCcOmhNOgXot4vzDegUem09SeEtjaYQKO7GwOwI3DmqwLPP+lNv5Xk0qD9iU ICQlWZmx4Yq+rRdzjHNci00oF3PDWKhBPUyTAGQA8J6y+73AY1+F6v8EqBob4sRvdJHU hqkDZ1OXpAqgqRxrKwJ1EwknuHsZ2qTorhRTvfWyq7MGhyXLToF/1XVY+mO+TaaWrUTK cQmQ== X-Gm-Message-State: AOJu0YyPQQwmy/kImwj2sWkrA7oDmCZdSd9lgy4t4rOvWcozj3nSS9IL 626ijKWPYGHYT51Woih/r30B/XRcvzvQY9zc3M+fmsoyKaM8Gmv9NukiFQNs6MLPm81h5F9glAz 8c8Po X-Gm-Gg: ASbGncsNgVlMWAOxgP2bTLaUwEcgV/v/HDJz3neWBWnxPMQXhhuYR6VPGU38iYjFvs3 I2shewcfyrg0Nx9DqaNIlMnNb5jRquTzaavOaCe+U9qzSvO17PorPhkznwiUwxwQosfkJ6nFQie jDBv6znHUXnecJLn80zj+BA0ZmbXCbMfQBL9UwP97y3F+CM2Mstdc0SmnV6tD73KNnwnWI5bdqh a45lo5TVNh7G+FqFcERW4P6PJGdoOvwQbJyra6WCWaLO6a8c7azFOdRAOqIujBG9w+LwCDmT8vm USnQJS8fSFwOdxgOeKjZLtaQW8KsE+OG1lEHWMG0XytTMGpG41v+JQQAXtixy1KwAYHg2oigSUh VJgFQcxkOoh38oEDHdAiv/1b3goRy X-Google-Smtp-Source: AGHT+IFiTlWl02aqHeSU26/oyyIJEqjLfbs5A8MaQWEJJH6sKyZNpQFyWMZHL/GXSE4DqfK75RQh/g== X-Received: by 2002:a05:6000:4a11:b0:3a4:e6d7:6160 with SMTP id ffacd0b85a97d-3b5f2db1496mr2000194f8f.6.1752240895561; Fri, 11 Jul 2025 06:34:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] target/arm: Split out AT insns to tcg/cpregs-at.c Date: Fri, 11 Jul 2025 14:34:16 +0100 Message-ID: <20250711133429.1423030-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241036734116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Split out all "system instructions for address translation". While mapped into "cpregs", these are instructions, and thus are handled in hardware by virtualization. They are all priviledged, and thus not reachable for user-only. Signed-off-by: Richard Henderson Message-id: 20250707151547.196393-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 + target/arm/helper.c | 514 +----------------------------------- target/arm/tcg/cpregs-at.c | 519 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 4 files changed, 525 insertions(+), 512 deletions(-) create mode 100644 target/arm/tcg/cpregs-at.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 21a8d67eddf..bcaf8965fc6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1871,6 +1871,8 @@ void define_debug_regs(ARMCPU *cpu); =20 /* Add the cpreg definitions for TLBI instructions */ void define_tlb_insn_regs(ARMCPU *cpu); +/* Add the cpreg definitions for AT instructions */ +void define_at_insn_regs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) @@ -1981,5 +1983,6 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); * specified by mask changing to the values in val. */ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); +bool arm_pan_enabled(CPUARMState *env); =20 #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index c1b684e3d1c..0883246905f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -270,7 +270,7 @@ void init_cpreg_list(ARMCPU *cpu) g_list_free(keys); } =20 -static bool arm_pan_enabled(CPUARMState *env) +bool arm_pan_enabled(CPUARMState *env) { if (is_a64(env)) { if ((arm_hcr_el2_eff(env) & (HCR_NV | HCR_NV1)) =3D=3D (HCR_NV | H= CR_NV1)) { @@ -3448,402 +3448,6 @@ static void par_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) } } =20 -#ifndef CONFIG_USER_ONLY -/* get_phys_addr() isn't present for user-mode-only targets */ - -static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (ri->opc2 & 4) { - /* - * The ATS12NSO* operations must trap to EL3 or EL2 if executed in - * Secure EL1 (which can only happen if EL3 is AArch64). - * They are simply UNDEF if executed from NS EL1. - * They function normally from EL2 or EL3. - */ - if (arm_current_el(env) =3D=3D 1) { - if (arm_is_secure_below_el3(env)) { - if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_EL2; - } - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_UNDEFINED; - } - } - return CP_ACCESS_OK; -} - -#ifdef CONFIG_TCG -static int par_el1_shareability(GetPhysAddrResult *res) -{ - /* - * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC - * memory -- see pseudocode PAREncodeShareability(). - */ - if (((res->cacheattrs.attrs & 0xf0) =3D=3D 0) || - res->cacheattrs.attrs =3D=3D 0x44 || res->cacheattrs.attrs =3D=3D = 0x40) { - return 2; - } - return res->cacheattrs.shareability; -} - -static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - ARMSecuritySpace ss) -{ - bool ret; - uint64_t par64; - bool format64 =3D false; - ARMMMUFaultInfo fi =3D {}; - GetPhysAddrResult res =3D {}; - - /* - * I_MXTJT: Granule protection checks are not performed on the final - * address of a successful translation. This is a translation not a - * memory reference, so "memop =3D none =3D 0". - */ - ret =3D get_phys_addr_with_space_nogpc(env, value, access_type, 0, - mmu_idx, ss, &res, &fi); - - /* - * ATS operations only do S1 or S1+S2 translations, so we never - * have to deal with the ARMCacheAttrs format for S2 only. - */ - assert(!res.cacheattrs.is_s2_format); - - if (ret) { - /* - * Some kinds of translation fault must cause exceptions rather - * than being reported in the PAR. - */ - int current_el =3D arm_current_el(env); - int target_el; - uint32_t syn, fsr, fsc; - bool take_exc =3D false; - - if (fi.s1ptw && current_el =3D=3D 1 - && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { - /* - * Synchronous stage 2 fault on an access made as part of the - * translation table walk for AT S1E0* or AT S1E1* insn - * executed from NS EL1. If this is a synchronous external abo= rt - * and SCR_EL3.EA =3D=3D 1, then we take a synchronous externa= l abort - * to EL3. Otherwise the fault is taken as an exception to EL2, - * and HPFAR_EL2 holds the faulting IPA. - */ - if (fi.type =3D=3D ARMFault_SyncExternalOnWalk && - (env->cp15.scr_el3 & SCR_EA)) { - target_el =3D 3; - } else { - env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi.s1ns) { - env->cp15.hpfar_el2 |=3D HPFAR_NS; - } - target_el =3D 2; - } - take_exc =3D true; - } else if (fi.type =3D=3D ARMFault_SyncExternalOnWalk) { - /* - * Synchronous external aborts during a translation table walk - * are taken as Data Abort exceptions. - */ - if (fi.stage2) { - if (current_el =3D=3D 3) { - target_el =3D 3; - } else { - target_el =3D 2; - } - } else { - target_el =3D exception_target_el(env); - } - take_exc =3D true; - } - - if (take_exc) { - /* Construct FSR and FSC using same logic as arm_deliver_fault= () */ - if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || - arm_s1_regime_using_lpae_format(env, mmu_idx)) { - fsr =3D arm_fi_to_lfsc(&fi); - fsc =3D extract32(fsr, 0, 6); - } else { - fsr =3D arm_fi_to_sfsc(&fi); - fsc =3D 0x3f; - } - /* - * Report exception with ESR indicating a fault due to a - * translation table walk for a cache maintenance instruction. - */ - syn =3D syn_data_abort_no_iss(current_el =3D=3D target_el, 0, - fi.ea, 1, fi.s1ptw, 1, fsc); - env->exception.vaddress =3D value; - env->exception.fsr =3D fsr; - raise_exception(env, EXCP_DATA_ABORT, syn, target_el); - } - } - - if (is_a64(env)) { - format64 =3D true; - } else if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* - * ATS1Cxx: - * * TTBCR.EAE determines whether the result is returned using the - * 32-bit or the 64-bit PAR format - * * Instructions executed in Hyp mode always use the 64bit format - * - * ATS1S2NSOxx uses the 64bit format if any of the following is tr= ue: - * * The Non-secure TTBCR.EAE bit is set to 1 - * * The implementation includes EL2, and the value of HCR.VM is 1 - * - * (Note that HCR.DC makes HCR.VM behave as if it is 1.) - * - * ATS1Hx always uses the 64bit format. - */ - format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); - - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || - mmu_idx =3D=3D ARMMMUIdx_E10_1 || - mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { - format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); - } else { - format64 |=3D arm_current_el(env) =3D=3D 2; - } - } - } - - if (format64) { - /* Create a 64-bit PAR */ - par64 =3D (1 << 11); /* LPAE bit always set */ - if (!ret) { - par64 |=3D res.f.phys_addr & ~0xfffULL; - if (!res.f.attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ - par64 |=3D par_el1_shareability(&res) << 7; /* SH */ - } else { - uint32_t fsr =3D arm_fi_to_lfsc(&fi); - - par64 |=3D 1; /* F */ - par64 |=3D (fsr & 0x3f) << 1; /* FS */ - if (fi.stage2) { - par64 |=3D (1 << 9); /* S */ - } - if (fi.s1ptw) { - par64 |=3D (1 << 8); /* PTW */ - } - } - } else { - /* - * fsr is a DFSR/IFSR value for the short descriptor - * translation table format (with WnR always clear). - * Convert it to a 32-bit PAR. - */ - if (!ret) { - /* We do not set any attribute bits in the PAR */ - if (res.f.lg_page_size =3D=3D 24 - && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); - } else { - par64 =3D res.f.phys_addr & 0xfffff000; - } - if (!res.f.attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - } else { - uint32_t fsr =3D arm_fi_to_sfsc(&fi); - - par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | - ((fsr & 0xf) << 1) | 1; - } - } - return par64; -} -#endif /* CONFIG_TCG */ - -static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - uint64_t par64; - ARMMMUIdx mmu_idx; - int el =3D arm_current_el(env); - ARMSecuritySpace ss =3D arm_security_space(env); - - switch (ri->opc2 & 6) { - case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ - switch (el) { - case 3: - if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { - mmu_idx =3D ARMMMUIdx_E30_3_PAN; - } else { - mmu_idx =3D ARMMMUIdx_E3; - } - break; - case 2: - g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ - /* fall through */ - case 1: - if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { - mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; - } else { - mmu_idx =3D ARMMMUIdx_Stage1_E1; - } - break; - default: - g_assert_not_reached(); - } - break; - case 2: - /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ - switch (el) { - case 3: - mmu_idx =3D ARMMMUIdx_E30_0; - break; - case 2: - g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ - mmu_idx =3D ARMMMUIdx_Stage1_E0; - break; - case 1: - mmu_idx =3D ARMMMUIdx_Stage1_E0; - break; - default: - g_assert_not_reached(); - } - break; - case 4: - /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_E10_1; - ss =3D ARMSS_NonSecure; - break; - case 6: - /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_E10_0; - ss =3D ARMSS_NonSecure; - break; - default: - g_assert_not_reached(); - } - - par64 =3D do_ats_write(env, value, access_type, mmu_idx, ss); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} - -static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - uint64_t par64; - - /* There is no SecureEL2 for AArch32. */ - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, - ARMSS_NonSecure); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} - -static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - /* - * R_NYXTL: instruction is UNDEFINED if it applies to an Exception lev= el - * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. Th= is can - * only happen when executing at EL3 because that combination also cau= ses an - * illegal exception return. We don't need to check FEAT_RME either, b= ecause - * scr_write() ensures that the NSE bit is not set otherwise. - */ - if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) =3D=3D SCR_NSE) { - return CP_ACCESS_UNDEFINED; - } - return CP_ACCESS_OK; -} - -static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3 && - !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { - return CP_ACCESS_UNDEFINED; - } - return at_e012_access(env, ri, isread); -} - -static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { - return CP_ACCESS_TRAP_EL2; - } - return at_e012_access(env, ri, isread); -} - -static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - ARMMMUIdx mmu_idx; - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); - bool for_el3 =3D false; - ARMSecuritySpace ss; - - switch (ri->opc2 & 6) { - case 0: - switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ - if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { - mmu_idx =3D regime_e20 ? - ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; - } else { - mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage= 1_E1; - } - break; - case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; - break; - case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_E3; - for_el3 =3D true; - break; - default: - g_assert_not_reached(); - } - break; - case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; - break; - case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; - break; - case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; - break; - default: - g_assert_not_reached(); - } - - ss =3D for_el3 ? arm_security_space(env) : arm_security_space_below_el= 3(env); - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx,= ss); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} -#endif - /* Return basic MPU access permission bits. */ static uint32_t simple_mpu_ap_bits(uint32_t val) { @@ -5094,53 +4698,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, -#ifndef CONFIG_USER_ONLY - /* 64 bit address translation operations */ - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E1R, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E1W, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E0R, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E0W, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, - /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ - { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, { .name =3D "PAR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, @@ -5148,7 +4705,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fgt =3D FGT_PAR_EL1, .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), .writefn =3D par_write }, -#endif /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_ticab = }, @@ -5751,33 +5307,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, #ifndef CONFIG_USER_ONLY - /* - * Unlike the other EL2-related AT operations, these must - * UNDEF from EL3 if EL2 is not implemented, which is why we - * define them here rather than with the rest of the AT ops. - */ - { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, - .writefn =3D ats_write64 }, - /* - * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE - * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 - * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se - * to behave as if SCR.NS was 1. - */ - { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, - { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, /* @@ -7704,32 +7233,6 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { #endif }; =20 -#ifndef CONFIG_USER_ONLY -static const ARMCPRegInfo ats1e1_reginfo[] =3D { - { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E1RP, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .fgt =3D FGT_ATS1E1WP, - .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, -}; - -static const ARMCPRegInfo ats1cp_reginfo[] =3D { - { .name =3D "ATS1CPRP", - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write }, - { .name =3D "ATS1CPWP", - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write }, -}; -#endif - /* * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field @@ -7773,6 +7276,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) #ifndef CONFIG_USER_ONLY if (tcg_enabled()) { define_tlb_insn_regs(cpu); + define_at_insn_regs(cpu); } #endif =20 @@ -8506,12 +8010,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par= _s), offsetoflow32(CPUARMState, cp15.par_n= s) }, .writefn =3D par_write}, -#ifndef CONFIG_USER_ONLY - /* This underdecoding is safe because the reginfo is NO_RAW. */ - { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 = =3D 0, .opc2 =3D CP_ANY, - .access =3D PL1_W, .accessfn =3D ats_access, - .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAI= SES_EXC }, -#endif }; =20 /* @@ -8917,14 +8415,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } -#ifndef CONFIG_USER_ONLY - if (cpu_isar_feature(aa64_ats1e1, cpu)) { - define_arm_cp_regs(cpu, ats1e1_reginfo); - } - if (cpu_isar_feature(aa32_ats1e1, cpu)) { - define_arm_cp_regs(cpu, ats1cp_reginfo); - } -#endif if (cpu_isar_feature(aa64_uao, cpu)) { define_one_arm_cp_reg(cpu, &uao_reginfo); } diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c new file mode 100644 index 00000000000..398a61d3989 --- /dev/null +++ b/target/arm/tcg/cpregs-at.c @@ -0,0 +1,519 @@ +/* + * System instructions for address translation + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu-features.h" +#include "internals.h" +#include "cpregs.h" + + +static int par_el1_shareability(GetPhysAddrResult *res) +{ + /* + * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC + * memory -- see pseudocode PAREncodeShareability(). + */ + if (((res->cacheattrs.attrs & 0xf0) =3D=3D 0) || + res->cacheattrs.attrs =3D=3D 0x44 || res->cacheattrs.attrs =3D=3D = 0x40) { + return 2; + } + return res->cacheattrs.shareability; +} + +static uint64_t do_ats_write(CPUARMState *env, uint64_t value, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + ARMSecuritySpace ss) +{ + bool ret; + uint64_t par64; + bool format64 =3D false; + ARMMMUFaultInfo fi =3D {}; + GetPhysAddrResult res =3D {}; + + /* + * I_MXTJT: Granule protection checks are not performed on the final + * address of a successful translation. This is a translation not a + * memory reference, so "memop =3D none =3D 0". + */ + ret =3D get_phys_addr_with_space_nogpc(env, value, access_type, 0, + mmu_idx, ss, &res, &fi); + + /* + * ATS operations only do S1 or S1+S2 translations, so we never + * have to deal with the ARMCacheAttrs format for S2 only. + */ + assert(!res.cacheattrs.is_s2_format); + + if (ret) { + /* + * Some kinds of translation fault must cause exceptions rather + * than being reported in the PAR. + */ + int current_el =3D arm_current_el(env); + int target_el; + uint32_t syn, fsr, fsc; + bool take_exc =3D false; + + if (fi.s1ptw && current_el =3D=3D 1 + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + /* + * Synchronous stage 2 fault on an access made as part of the + * translation table walk for AT S1E0* or AT S1E1* insn + * executed from NS EL1. If this is a synchronous external abo= rt + * and SCR_EL3.EA =3D=3D 1, then we take a synchronous externa= l abort + * to EL3. Otherwise the fault is taken as an exception to EL2, + * and HPFAR_EL2 holds the faulting IPA. + */ + if (fi.type =3D=3D ARMFault_SyncExternalOnWalk && + (env->cp15.scr_el3 & SCR_EA)) { + target_el =3D 3; + } else { + env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi.s1ns) { + env->cp15.hpfar_el2 |=3D HPFAR_NS; + } + target_el =3D 2; + } + take_exc =3D true; + } else if (fi.type =3D=3D ARMFault_SyncExternalOnWalk) { + /* + * Synchronous external aborts during a translation table walk + * are taken as Data Abort exceptions. + */ + if (fi.stage2) { + if (current_el =3D=3D 3) { + target_el =3D 3; + } else { + target_el =3D 2; + } + } else { + target_el =3D exception_target_el(env); + } + take_exc =3D true; + } + + if (take_exc) { + /* Construct FSR and FSC using same logic as arm_deliver_fault= () */ + if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, mmu_idx)) { + fsr =3D arm_fi_to_lfsc(&fi); + fsc =3D extract32(fsr, 0, 6); + } else { + fsr =3D arm_fi_to_sfsc(&fi); + fsc =3D 0x3f; + } + /* + * Report exception with ESR indicating a fault due to a + * translation table walk for a cache maintenance instruction. + */ + syn =3D syn_data_abort_no_iss(current_el =3D=3D target_el, 0, + fi.ea, 1, fi.s1ptw, 1, fsc); + env->exception.vaddress =3D value; + env->exception.fsr =3D fsr; + raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + } + } + + if (is_a64(env)) { + format64 =3D true; + } else if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* + * ATS1Cxx: + * * TTBCR.EAE determines whether the result is returned using the + * 32-bit or the 64-bit PAR format + * * Instructions executed in Hyp mode always use the 64bit format + * + * ATS1S2NSOxx uses the 64bit format if any of the following is tr= ue: + * * The Non-secure TTBCR.EAE bit is set to 1 + * * The implementation includes EL2, and the value of HCR.VM is 1 + * + * (Note that HCR.DC makes HCR.VM behave as if it is 1.) + * + * ATS1Hx always uses the 64bit format. + */ + format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || + mmu_idx =3D=3D ARMMMUIdx_E10_1 || + mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { + format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); + } else { + format64 |=3D arm_current_el(env) =3D=3D 2; + } + } + } + + if (format64) { + /* Create a 64-bit PAR */ + par64 =3D (1 << 11); /* LPAE bit always set */ + if (!ret) { + par64 |=3D res.f.phys_addr & ~0xfffULL; + if (!res.f.attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + par64 |=3D (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ + par64 |=3D par_el1_shareability(&res) << 7; /* SH */ + } else { + uint32_t fsr =3D arm_fi_to_lfsc(&fi); + + par64 |=3D 1; /* F */ + par64 |=3D (fsr & 0x3f) << 1; /* FS */ + if (fi.stage2) { + par64 |=3D (1 << 9); /* S */ + } + if (fi.s1ptw) { + par64 |=3D (1 << 8); /* PTW */ + } + } + } else { + /* + * fsr is a DFSR/IFSR value for the short descriptor + * translation table format (with WnR always clear). + * Convert it to a 32-bit PAR. + */ + if (!ret) { + /* We do not set any attribute bits in the PAR */ + if (res.f.lg_page_size =3D=3D 24 + && arm_feature(env, ARM_FEATURE_V7)) { + par64 =3D (res.f.phys_addr & 0xff000000) | (1 << 1); + } else { + par64 =3D res.f.phys_addr & 0xfffff000; + } + if (!res.f.attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + } else { + uint32_t fsr =3D arm_fi_to_sfsc(&fi); + + par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | + ((fsr & 0xf) << 1) | 1; + } + } + return par64; +} + +static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + uint64_t par64; + ARMMMUIdx mmu_idx; + int el =3D arm_current_el(env); + ARMSecuritySpace ss =3D arm_security_space(env); + + switch (ri->opc2 & 6) { + case 0: + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ + switch (el) { + case 3: + if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { + mmu_idx =3D ARMMMUIdx_E30_3_PAN; + } else { + mmu_idx =3D ARMMMUIdx_E3; + } + break; + case 2: + g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ + /* fall through */ + case 1: + if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { + mmu_idx =3D ARMMMUIdx_Stage1_E1_PAN; + } else { + mmu_idx =3D ARMMMUIdx_Stage1_E1; + } + break; + default: + g_assert_not_reached(); + } + break; + case 2: + /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ + switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_E30_0; + break; + case 2: + g_assert(ss !=3D ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit o= nly */ + mmu_idx =3D ARMMMUIdx_Stage1_E0; + break; + case 1: + mmu_idx =3D ARMMMUIdx_Stage1_E0; + break; + default: + g_assert_not_reached(); + } + break; + case 4: + /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ + mmu_idx =3D ARMMMUIdx_E10_1; + ss =3D ARMSS_NonSecure; + break; + case 6: + /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ + mmu_idx =3D ARMMMUIdx_E10_0; + ss =3D ARMSS_NonSecure; + break; + default: + g_assert_not_reached(); + } + + par64 =3D do_ats_write(env, value, access_type, mmu_idx, ss); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + uint64_t par64; + + /* There is no SecureEL2 for AArch32. */ + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, + ARMSS_NonSecure); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + /* + * R_NYXTL: instruction is UNDEFINED if it applies to an Exception lev= el + * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. Th= is can + * only happen when executing at EL3 because that combination also cau= ses an + * illegal exception return. We don't need to check FEAT_RME either, b= ecause + * scr_write() ensures that the NSE bit is not set otherwise. + */ + if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) =3D=3D SCR_NSE) { + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; +} + +static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3 && + !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { + return CP_ACCESS_UNDEFINED; + } + return at_e012_access(env, ri, isread); +} + +static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { + return CP_ACCESS_TRAP_EL2; + } + return at_e012_access(env, ri, isread); +} + +static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + ARMMMUIdx mmu_idx; + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); + bool for_el3 =3D false; + ARMSecuritySpace ss; + + switch (ri->opc2 & 6) { + case 0: + switch (ri->opc1) { + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm =3D=3D 9 && arm_pan_enabled(env)) { + mmu_idx =3D regime_e20 ? + ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; + } else { + mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage= 1_E1; + } + break; + case 4: /* AT S1E2R, AT S1E2W */ + mmu_idx =3D hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; + break; + case 6: /* AT S1E3R, AT S1E3W */ + mmu_idx =3D ARMMMUIdx_E3; + for_el3 =3D true; + break; + default: + g_assert_not_reached(); + } + break; + case 2: /* AT S1E0R, AT S1E0W */ + mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; + break; + case 4: /* AT S12E1R, AT S12E1W */ + mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; + break; + case 6: /* AT S12E0R, AT S12E0W */ + mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; + break; + default: + g_assert_not_reached(); + } + + ss =3D for_el3 ? arm_security_space(env) : arm_security_space_below_el= 3(env); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx,= ss); +} + +static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (ri->opc2 & 4) { + /* + * The ATS12NSO* operations must trap to EL3 or EL2 if executed in + * Secure EL1 (which can only happen if EL3 is AArch64). + * They are simply UNDEF if executed from NS EL1. + * They function normally from EL2 or EL3. + */ + if (arm_current_el(env) =3D=3D 1) { + if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_UNDEFINED; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo vapa_ats_reginfo[] =3D { + /* This underdecoding is safe because the reginfo is NO_RAW. */ + { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, + .access =3D PL1_W, .accessfn =3D ats_access, + .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, +}; + +static const ARMCPRegInfo v8_ats_reginfo[] =3D { + /* 64 bit address translation operations */ + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1R, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1W, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0R, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E0W, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ + { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, +}; + +static const ARMCPRegInfo el2_ats_reginfo[] =3D { + /* + * Unlike the other EL2-related AT operations, these must + * UNDEF from EL3 if EL2 is not implemented, which is why we + * define them here rather than with the rest of the AT ops. + */ + { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, + /* + * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 + * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se + * to behave as if SCR.NS was 1. + */ + { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, + { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, +}; + +static const ARMCPRegInfo ats1e1_reginfo[] =3D { + { .name =3D "AT_S1E1RP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1RP, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1WP, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, +}; + +static const ARMCPRegInfo ats1cp_reginfo[] =3D { + { .name =3D "ATS1CPRP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + { .name =3D "ATS1CPWP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, +}; + +void define_at_insn_regs(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + + if (arm_feature(env, ARM_FEATURE_VAPA)) { + define_arm_cp_regs(cpu, vapa_ats_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, v8_ats_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) + || (arm_feature(env, ARM_FEATURE_EL3) + && arm_feature(env, ARM_FEATURE_V8))) { + define_arm_cp_regs(cpu, el2_ats_reginfo); + } + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index c59f0f03a1b..895facdc30b 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -64,6 +64,7 @@ arm_common_ss.add(files( )) =20 arm_common_system_ss.add(files( + 'cpregs-at.c', 'hflags.c', 'iwmmxt_helper.c', 'neon_helper.c', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241127; cv=none; d=zohomail.com; s=zohoarc; b=QjCE4sv+Fnezwo7HVMZETS9PzyLxPAttsZVHXsZJ2NRi6JFLtBW6CtXx2Rh6CesSIufIKVe08zrCjTd3I4HgC1U+lJxxomQ5I9ZNGNBa6g9QJx0az6qz5Xo+7q/F1wDppCReCs5mCaoYc81LBAg37hcllkVpj6xdX1GyXb/jSnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241127; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=P/aT65CnJxDva/a/2mZbBvUJeTQnjZ3uBUOL5IQWhdU=; b=BzAvvJ4ZXsQa2vfw9bScspsqSAivnZWkUL1ChIoolJqE4DnMV2Y1jYdbD7I5eH5PD43sthgf7YfkjKyZBS9fyzum4zUwZxY9y0a4Q3aPAW0rVfqJOBmmLxwjTD0xvg6eMXCEm0U43NYDxPx1VUvrCWsKVnYrseGc9dI2ZmBRVe8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241127265237.50709857947004; Fri, 11 Jul 2025 06:38:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuq-0006Bt-Ia; Fri, 11 Jul 2025 09:35:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu4-0004X1-Pv for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:06 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtz-00039I-9r for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:03 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3a50956e5d3so1704263f8f.1 for ; Fri, 11 Jul 2025 06:34:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240897; x=1752845697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P/aT65CnJxDva/a/2mZbBvUJeTQnjZ3uBUOL5IQWhdU=; b=duo1Tzv/AZsKj95YlhuweeCyJN+HpLzoDURiNDDJqnhj1Dq8t0w+U4woKxcW4SvDJi wAHmelxcqmqZ/GXVY7nBoGk1FWu90cDgZBfKWPDQlXi8lU56se9PL0Q/VfMJJ6/LJz9h 2wE9dHWf8imh2gGwMRcbcDvOsFB6sl8CUa8at4N1u8j4f0r3bmiXn6qarvFYuO7UNp48 fSPoxNcaD4UKskxqKE7XzytLtbRJmsbHBaEByGHNy40zF678sVRPhUU6tzyt/Ad8eQ5s LKG6my+N7ruOcMgCPGYmZcuc1Qu50Tm2WyMXvx9ii1FjvnTmUjuO2UmzkPkMetnL1Kmg YB9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240897; x=1752845697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P/aT65CnJxDva/a/2mZbBvUJeTQnjZ3uBUOL5IQWhdU=; b=fUNrrPBG394AkijuWSMrMkf2AFA6NO6xZxPy2GyZxmFRueOTe2dQAaSWac0OTDfY7R S0HeFwAFkPsC0nSIYaM9FO++OsEzye3exwD81gXgvFtU5DBdoxAN7foJPQREKqbadacC VZT/Uu5asg4FYOpqNCRIVWTQSXbvMn2/8R2K40latmwma5m1WasAu7VX3ouPMZI7M0J/ P2UcBPC5Dy745Lh0WUUL5/E+S5oLXUttHpSEDVwSuAqr2vRGV6hMgE/kfn3lbnuMw/Yz 9ZBt1kCckz+GbEch3+0xt9FBgGebT3PJM60C/CLZkl+pxSbYyZozspHgu7nz9Jpoo084 kWYA== X-Gm-Message-State: AOJu0YwhYNhMZe2GHoRPJXrzTZfY6tj61l6+K5QBVg5akXDUxak3TfAb y0zYjqMdBNdEitPyiNxPeShwY531z6ECT+ew6EwTn0CmEGiEyNkqWIntRceMabXNbMGAxSHoCSt zapXd X-Gm-Gg: ASbGnctSXApx6/Nj2160s72Bf+d9WJo14pa+7qS99TNpdFnCJCRWYVxLGCOT6WVE795 k6GUIHIwEJpW5+nKqOlFcypXI/3Fwwr6uC1ecka2CuRMVxaAiy/C59Tf1IwzYKoTE4RylSFrnJy M7sGfLvsndGLmxj1v0cX2ol1P8vs34tHpF9bEriYwubEz8IPEZweypBdOkqyt4OdF4fhK2wDVS9 m74ya4IdMrqqLvxMpHGnX4a3nRX+wnZ0sBjscpediBWem08dJnek5zy5s53GgRylCbDgetUKrJk H2eFhXmN0UFR8QEcrPVYM8RtdIUukpo+yn1vyrfg+uqoMZf0qSSOx6eAR1aYxrJ6QcPhsfF8pXo tj4P9OWRi8Fe8PrYUGUSTmxjpH3Gn1y9cHQeZTUw= X-Google-Smtp-Source: AGHT+IEMEYQA6R58udFK3wpGpREaEWrsJcRuUpSQSCsNN3LC61M7IfrsD3O5d1k3zkN3RZIwsaknPg== X-Received: by 2002:a05:6000:2d03:b0:3b1:9259:3ead with SMTP id ffacd0b85a97d-3b5f188ea57mr2619339f8f.28.1752240896829; Fri, 11 Jul 2025 06:34:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/36] target/arm: Split out performance monitor regs to cpregs-pmu.c Date: Fri, 11 Jul 2025 14:34:17 +0100 Message-ID: <20250711133429.1423030-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241130045116600 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250707151547.196393-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 3 + target/arm/internals.h | 2 + target/arm/cpregs-pmu.c | 1309 +++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 1287 +------------------------------------- target/arm/meson.build | 2 + 5 files changed, 1319 insertions(+), 1284 deletions(-) create mode 100644 target/arm/cpregs-pmu.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c1a7ae37356..c9506aa6d57 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1065,6 +1065,9 @@ void arm_cp_write_ignore(CPUARMState *env, const ARMC= PRegInfo *ri, /* CPReadFn that can be used for read-as-zero behaviour */ uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); =20 +/* CPReadFn that just reads the value from ri->fieldoffset */ +uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri); + /* CPWriteFn that just writes the value to ri->fieldoffset */ void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index bcaf8965fc6..c4765e44893 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1873,6 +1873,8 @@ void define_debug_regs(ARMCPU *cpu); void define_tlb_insn_regs(ARMCPU *cpu); /* Add the cpreg definitions for AT instructions */ void define_at_insn_regs(ARMCPU *cpu); +/* Add the cpreg definitions for PM cpregs */ +void define_pm_cpregs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c new file mode 100644 index 00000000000..0f295b1376c --- /dev/null +++ b/target/arm/cpregs-pmu.c @@ -0,0 +1,1309 @@ +/* + * QEMU ARM CP Register PMU insns + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/icount.h" +#include "hw/irq.h" +#include "cpu.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "internals.h" + + +#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ + +/* + * Check for traps to performance monitor registers, which are controlled + * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. + */ +static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* + * Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function + */ + uint64_t (*get_count)(CPUARMState *); + /* + * Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. + */ + int64_t (*ns_per_count)(uint64_t); +} pm_event; + +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t cycles_get_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return cpu_get_host_ticks(); +#endif +} + +#ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; +} + +static bool instructions_supported(CPUARMState *env) +{ + /* Precise instruction counting */ + return icount_enabled() =3D=3D ICOUNT_PRECISE; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + assert(icount_enabled() =3D=3D ICOUNT_PRECISE); + return (uint64_t)icount_get_raw(); +} + +static int64_t instructions_ns_per(uint64_t icount) +{ + assert(icount_enabled() =3D=3D ICOUNT_PRECISE); + return icount_to_ns((int64_t)icount); +} +#endif + +static bool pmuv3p1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); +} + +static bool pmuv3p4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero = */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + +static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per, + }, +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per, + }, + { .number =3D 0x011, /* CPU_CYCLES, Cycle */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per, + }, +#endif + { .number =3D 0x023, /* STALL_FRONTEND */ + .supported =3D pmuv3p1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x024, /* STALL_BACKEND */ + .supported =3D pmuv3p1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x03c, /* STALL */ + .supported =3D pmuv3p4_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, +}; + +/* + * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range = of + * events (i.e. the statistical profiling extension), this implementation + * should first be updated to something sparse instead of the current + * supported_event_map[] array. + */ +#define MAX_EVENT_ID 0x3c +#define UNSUPPORTED_EVENT UINT16_MAX +static uint16_t supported_event_map[MAX_EVENT_ID + 1]; + +/* + * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map + * of ARM event numbers to indices in our pm_events array. + * + * Note: Events in the 0x40XX range are not currently supported. + */ +void pmu_init(ARMCPU *cpu) +{ + unsigned int i; + + /* + * Empty supported_event_map and cpu->pmceid[01] before adding support= ed + * events to them + */ + for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { + supported_event_map[i] =3D UNSUPPORTED_EVENT; + } + cpu->pmceid0 =3D 0; + cpu->pmceid1 =3D 0; + + for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { + const pm_event *cnt =3D &pm_events[i]; + assert(cnt->number <=3D MAX_EVENT_ID); + /* We do not currently support events in the 0x40xx range */ + assert(cnt->number <=3D 0x3f); + + if (cnt->supported(&cpu->env)) { + supported_event_map[cnt->number] =3D i; + uint64_t event_mask =3D 1ULL << (cnt->number & 0x1f); + if (cnt->number & 0x20) { + cpu->pmceid1 |=3D event_mask; + } else { + cpu->pmceid0 |=3D event_mask; + } + } + } +} + +/* + * Check at runtime whether a PMU event is supported for the current machi= ne + */ +static bool event_supported(uint16_t number) +{ + if (number > MAX_EVENT_ID) { + return false; + } + return supported_event_map[number] !=3D UNSUPPORTED_EVENT; +} + +static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + /* + * Performance monitor registers user accessibility is controlled + * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable + * trapping to EL2 or EL3 for other accesses. + */ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + + if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { + return CP_ACCESS_TRAP_EL1; + } + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_swinc(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* SW: software increment write trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 1)) !=3D 0 + && !isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_selr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_ccntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* CR: cycle counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 2)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +/* + * Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) +{ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited =3D false, filtered; + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + uint64_t mdcr_el2; + uint8_t hpmn; + + /* + * We might be called for M-profile cores where MDCR_EL2 doesn't + * exist and arm_mdcr_el2_eff() will assert, so this early-exit check + * must be before we read that value. + */ + if (!arm_feature(env, ARM_FEATURE_PMU)) { + return false; + } + + mdcr_el2 =3D arm_mdcr_el2_eff(env); + hpmn =3D mdcr_el2 & MDCR_HPMN; + + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter =3D=3D 31)) { + e =3D env->cp15.c9_pmcr & PMCRE; + } else { + e =3D mdcr_el2 & MDCR_HPME; + } + enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); + + /* Is event counting prohibited? */ + if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { + prohibited =3D mdcr_el2 & MDCR_HPMD; + } + if (secure) { + prohibited =3D prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); + } + + if (counter =3D=3D 31) { + /* + * The cycle counter defaults to running. PMCR.DP says "disable + * the cycle counter when event counting is prohibited". + * Some MDCR bits disable the cycle counter specifically. + */ + prohibited =3D prohibited && env->cp15.c9_pmcr & PMCRDP; + if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + if (secure) { + prohibited =3D prohibited || (env->cp15.mdcr_el3 & MDCR_SC= CD); + } + if (el =3D=3D 2) { + prohibited =3D prohibited || (mdcr_el2 & MDCR_HCCD); + } + } + } + + if (counter =3D=3D 31) { + filter =3D env->cp15.pmccfiltr_el0; + } else { + filter =3D env->cp15.c14_pmevtyper[counter]; + } + + p =3D filter & PMXEVTYPER_P; + u =3D filter & PMXEVTYPER_U; + nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m =3D arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el =3D=3D 0) { + filtered =3D secure ? u : u !=3D nsu; + } else if (el =3D=3D 1) { + filtered =3D secure ? p : p !=3D nsk; + } else if (el =3D=3D 2) { + filtered =3D !nsh; + } else { /* EL3 */ + filtered =3D m !=3D p; + } + + if (counter !=3D 31) { + /* + * If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support + */ + uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; + if (!event_supported(event)) { + return false; + } + } + + return enabled && !prohibited && !filtered; +} + +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + +static bool pmccntr_clockdiv_enabled(CPUARMState *env) +{ + /* + * Return true if the clock divider is enabled and the cycle counter + * is supposed to tick only once every 64 clock cycles. This is + * controlled by PMCR.D, but if PMCR.LC is set to enable the long + * (64-bit) cycle counter PMCR.D has no effect. + */ + return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) =3D=3D PMCRD; +} + +static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) +{ + /* Return true if the specified event counter is configured to be 64 b= it */ + + /* This isn't intended to be used with the cycle counter */ + assert(counter < 31); + + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* + * MDCR_EL2.HLP still applies even when EL2 is disabled in the + * current security state, so we don't use arm_mdcr_el2_eff() here. + */ + bool hlp =3D env->cp15.mdcr_el2 & MDCR_HLP; + int hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; + + if (counter >=3D hpmn) { + return hlp; + } + } + return env->cp15.c9_pmcr & PMCRLP; +} + +/* + * Ensure c15_ccnt is the guest-visible count so that operations such as + * enabling/disabling the counter or filtering, modifying the count itself, + * etc. can be done logically. This is essentially a no-op if the counter = is + * not enabled at the time of the call. + */ +static void pmccntr_op_start(CPUARMState *env) +{ + uint64_t cycles =3D cycles_get_count(env); + + if (pmu_counter_enabled(env, 31)) { + uint64_t eff_cycles =3D cycles; + if (pmccntr_clockdiv_enabled(env)) { + eff_cycles /=3D 64; + } + + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \ + 1ull << 63 : 1ull << 31; + if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { + env->cp15.c9_pmovsr |=3D (1ULL << 31); + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; + } + env->cp15.c15_ccnt_delta =3D cycles; +} + +/* + * If PMCCNTR is enabled, recalculate the delta between the clock and the + * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to + * pmccntr_op_start. + */ +static void pmccntr_op_finish(CPUARMState *env) +{ + if (pmu_counter_enabled(env, 31)) { +#ifndef CONFIG_USER_ONLY + /* Calculate when the counter will next overflow */ + uint64_t remaining_cycles =3D -env->cp15.c15_ccnt; + if (!(env->cp15.c9_pmcr & PMCRLC)) { + remaining_cycles =3D (uint32_t)remaining_cycles; + } + int64_t overflow_in =3D cycles_ns_per(remaining_cycles); + + if (overflow_in > 0) { + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } + } +#endif + + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; + if (pmccntr_clockdiv_enabled(env)) { + prev_cycles /=3D 64; + } + env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; + } +} + +static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) +{ + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; + uint64_t count =3D 0; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + count =3D pm_events[event_idx].get_count(env); + } + + if (pmu_counter_enabled(env, counter)) { + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + uint64_t overflow_mask =3D pmevcntr_is_64_bit(env, counter) ? + 1ULL << 63 : 1ULL << 31; + + if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mas= k) { + env->cp15.c9_pmovsr |=3D (1 << counter); + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; +} + +static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) +{ + if (pmu_counter_enabled(env, counter)) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D -(env->cp15.c14_pmevcntr[counter] + 1); + int64_t overflow_in; + + if (!pmevcntr_is_64_bit(env, counter)) { + delta =3D (uint32_t)delta; + } + overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in > 0) { + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } + } +#endif + + env->cp15.c14_pmevcntr_delta[counter] -=3D + env->cp15.c14_pmevcntr[counter]; + } +} + +void pmu_op_start(CPUARMState *env) +{ + unsigned int i; + pmccntr_op_start(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_start(env, i); + } +} + +void pmu_op_finish(CPUARMState *env) +{ + unsigned int i; + pmccntr_op_finish(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_finish(env, i); + } +} + +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + +void arm_pmu_timer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* + * Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + +static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmu_op_start(env); + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt =3D 0; + } + + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + + env->cp15.c9_pmcr &=3D ~PMCR_WRITABLE_MASK; + env->cp15.c9_pmcr |=3D (value & PMCR_WRITABLE_MASK); + + pmu_op_finish(env); +} + +static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t pmcr =3D env->cp15.c9_pmcr; + + /* + * If EL2 is implemented and enabled for the current security state, r= eads + * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR= .HPMN. + */ + if (arm_current_el(env) <=3D 1 && arm_is_el2_enabled(env)) { + pmcr &=3D ~PMCRN_MASK; + pmcr |=3D (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; + } + + return pmcr; +} + +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + uint64_t overflow_mask, new_pmswinc; + + for (i =3D 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + pmevcntr_op_start(env, i); + + /* + * Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + overflow_mask =3D pmevcntr_is_64_bit(env, i) ? + 1ULL << 63 : 1ULL << 31; + + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { + env->cp15.c9_pmovsr |=3D (1 << i); + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + + pmevcntr_op_finish(env, i); + } + } +} + +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t ret; + pmccntr_op_start(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_op_finish(env); + return ret; +} + +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are + * accessed. + */ + env->cp15.c9_pmselr =3D value & 0x1f; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + env->cp15.c15_ccnt =3D value; + pmccntr_op_finish(env); +} + +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t cur_val =3D pmccntr_read(env, NULL); + + pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); +} + +static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; + pmccntr_op_finish(env); +} + +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); + pmccntr_op_finish(env); +} + +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + +static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmu_op_start(env); + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmcnten |=3D value; + pmu_op_finish(env); +} + +static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmu_op_start(env); + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmcnten &=3D ~value; + pmu_op_finish(env); +} + +static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); +} + +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); +} + +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) +{ + if (counter =3D=3D 31) { + pmccfiltr_write(env, ri, value); + } else if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + + /* + * If this counter's event type is changing, store the current + * underlying count for the new type in c14_pmevcntr_delta[counter= ] so + * pmevcntr_op_finish has the correct baseline when it converts ba= ck to + * a delta. + */ + uint16_t old_event =3D env->cp15.c14_pmevtyper[counter] & + PMXEVTYPER_EVTCOUNT; + uint16_t new_event =3D value & PMXEVTYPER_EVTCOUNT; + if (old_event !=3D new_event) { + uint64_t count =3D 0; + if (event_supported(new_event)) { + uint16_t event_idx =3D supported_event_map[new_event]; + count =3D pm_events[event_idx].get_count(env); + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; + } + + env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; + pmevcntr_op_finish(env, counter); + } + /* + * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + * PMSELR value is equal to or greater than the number of implemented + * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. + */ +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 31) { + return env->cp15.pmccfiltr_el0; + } else if (counter < pmu_num_counters(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* + * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; + } +} + +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + env->cp15.c14_pmevtyper[counter] =3D value; + + /* + * pmevtyper_rawwrite is called between a pair of pmu_op_start and + * pmu_op_finish calls when loading saved state for a migration. Becau= se + * we're potentially updating the type of event here, the value writte= n to + * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a + * different counter type. Therefore, we need to set this value to the + * current count for the counter type we're writing so that pmu_op_fin= ish + * has the correct count for its calculation. + */ + uint16_t event =3D value & PMXEVTYPER_EVTCOUNT; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + env->cp15.c14_pmevcntr_delta[counter] =3D + pm_events[event_idx].get_count(env); + } +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ + value &=3D MAKE_64BIT_MASK(0, 32); + } + if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_op_finish(env, counter); + } + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. + */ +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + uint64_t ret; + pmevcntr_op_start(env, counter); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmevcntr_op_finish(env, counter); + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0= */ + ret &=3D MAKE_64BIT_MASK(0, 32); + } + return ret; + } else { + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. + */ + return 0; + } +} + +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + return env->cp15.c14_pmevcntr[counter]; +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.c9_pmuserenr =3D value & 0xf; + } else { + env->cp15.c9_pmuserenr =3D value & 1; + } +} + +static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* We have no event counters so only the C bit can be changed */ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); +} + +static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); +} + +static const ARMCPRegInfo v7_pm_reginfo[] =3D { + /* + * Performance monitors are implementation defined in v7, + * but with an ARM recommended set of registers, which we + * follow. + * + * Performance registers fall into three categories: + * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) + * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) + * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) + * For the cases controlled by PMUSERENR we must set .access to PL0_RW + * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. + */ + { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenset_write, + .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, + .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, + .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write, + .type =3D ARM_CP_ALIAS | ARM_CP_IO }, + { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCNTEN, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, + .access =3D PL0_RW, .type =3D ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .fgt =3D FGT_PMSWINC_EL0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .writefn =3D pmswinc_write }, + { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fgt =3D FGT_PMSELR_EL0, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), + .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, + .raw_writefn =3D raw_write}, + { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, + .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, + .fgt =3D FGT_PMSELR_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), + .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, + { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, + .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, + .fgt =3D FGT_PMCCNTR_EL0, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, + .accessfn =3D pmreg_access_ccntr }, + { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .fgt =3D FGT_PMCCNTR_EL0, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue =3D 0, }, + { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCCFILTR_EL0, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), + .resetvalue =3D 0, }, + { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, + .fgt =3D FGT_PMEVTYPERN_EL0, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .fgt =3D FGT_PMEVCNTRN_EL0, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), + .resetvalue =3D 0, + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, + .resetvalue =3D 0x0 }, + { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .fgt =3D FGT_PMINTEN, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, +}; + +static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMOVS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, +}; + +void define_pm_cpregs(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + + if (arm_feature(env, ARM_FEATURE_V7)) { + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + static const ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL0_RW, + .fgt =3D FGT_PMCR_EL0, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, + .readfn =3D pmcr_read, .raw_readfn =3D raw_read, + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + const ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fgt =3D FGT_PMCR_EL0, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D cpu->isar.reset_pmcr_el0, + .readfn =3D pmcr_read, .raw_readfn =3D raw_read, + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + define_arm_cp_regs(cpu, v7_pm_reginfo); + + for (unsigned i =3D 0, pmcrn =3D pmu_num_counters(env); i < pmcrn;= i++) { + g_autofree char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d= ", i); + g_autofree char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCN= TR%d_EL0", i); + g_autofree char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER= %d", i); + g_autofree char *pmevtyper_el0_name =3D g_strdup_printf("PMEVT= YPER%d_EL0", i); + + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVCNTRN_EL0, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .accessfn =3D pmreg_access_xevcntr }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 &= (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access_xevcntr, + .type =3D ARM_CP_IO, + .fgt =3D FGT_PMEVCNTRN_EL0, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fgt =3D FGT_PMEVTYPERN_EL0, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 = & (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .fgt =3D FGT_PMEVTYPERN_EL0, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .raw_writefn =3D pmevtyper_rawwrite }, + }; + define_arm_cp_regs(cpu, pmev_regs); + } + } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_V8)) { + const ARMCPRegInfo v8_pm_reginfo[] =3D { + { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, + { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D cpu->pmceid0 }, + { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, + { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D cpu->pmceid1 }, + }; + define_arm_cp_regs(cpu, v8_pm_reginfo); + } + + if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .fgt =3D FGT_PMCEIDN_EL0, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } + + if (cpu_isar_feature(any_pmuv3p4, cpu)) { + static const ARMCPRegInfo v84_pmmir =3D { + .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .fgt =3D FGT_PMMIR_EL1, + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } +} diff --git a/target/arm/helper.c b/target/arm/helper.c index 0883246905f..0c1299ff841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -38,11 +38,9 @@ #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" =20 -#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ - static void switch_mode(CPUARMState *env, int mode); =20 -static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) +uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) { assert(ri->fieldoffset); if (cpreg_field_is_64bit(ri)) { @@ -319,25 +317,6 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMStat= e *env, return CP_ACCESS_UNDEFINED; } =20 -/* - * Check for traps to performance monitor registers, which are controlled - * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. - */ -static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - - if (el < 2 && (mdcr_el2 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -681,283 +660,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, }; =20 -typedef struct pm_event { - uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ - /* If the event is supported on this CPU (used to generate PMCEID[01])= */ - bool (*supported)(CPUARMState *); - /* - * Retrieve the current count of the underlying event. The programmed - * counters hold a difference from the return value from this function - */ - uint64_t (*get_count)(CPUARMState *); - /* - * Return how many nanoseconds it will take (at a minimum) for count e= vents - * to occur. A negative value indicates the counter will never overflo= w, or - * that the counter has otherwise arranged for the overflow bit to be = set - * and the PMU interrupt to be raised on overflow. - */ - int64_t (*ns_per_count)(uint64_t); -} pm_event; - -static bool event_always_supported(CPUARMState *env) -{ - return true; -} - -static uint64_t swinc_get_count(CPUARMState *env) -{ - /* - * SW_INCR events are written directly to the pmevcntr's by writes to - * PMSWINC, so there is no underlying count maintained by the PMU itse= lf - */ - return 0; -} - -static int64_t swinc_ns_per(uint64_t ignored) -{ - return -1; -} - -/* - * Return the underlying cycle count for the PMU cycle counters. If we're = in - * usermode, simply return 0. - */ -static uint64_t cycles_get_count(CPUARMState *env) -{ -#ifndef CONFIG_USER_ONLY - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#else - return cpu_get_host_ticks(); -#endif -} - -#ifndef CONFIG_USER_ONLY -static int64_t cycles_ns_per(uint64_t cycles) -{ - return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; -} - -static bool instructions_supported(CPUARMState *env) -{ - /* Precise instruction counting */ - return icount_enabled() =3D=3D ICOUNT_PRECISE; -} - -static uint64_t instructions_get_count(CPUARMState *env) -{ - assert(icount_enabled() =3D=3D ICOUNT_PRECISE); - return (uint64_t)icount_get_raw(); -} - -static int64_t instructions_ns_per(uint64_t icount) -{ - assert(icount_enabled() =3D=3D ICOUNT_PRECISE); - return icount_to_ns((int64_t)icount); -} -#endif - -static bool pmuv3p1_events_supported(CPUARMState *env) -{ - /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); -} - -static bool pmuv3p4_events_supported(CPUARMState *env) -{ - /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); -} - -static uint64_t zero_event_get_count(CPUARMState *env) -{ - /* For events which on QEMU never fire, so their count is always zero = */ - return 0; -} - -static int64_t zero_event_ns_per(uint64_t cycles) -{ - /* An event which never fires can never overflow */ - return -1; -} - -static const pm_event pm_events[] =3D { - { .number =3D 0x000, /* SW_INCR */ - .supported =3D event_always_supported, - .get_count =3D swinc_get_count, - .ns_per_count =3D swinc_ns_per, - }, -#ifndef CONFIG_USER_ONLY - { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ - .supported =3D instructions_supported, - .get_count =3D instructions_get_count, - .ns_per_count =3D instructions_ns_per, - }, - { .number =3D 0x011, /* CPU_CYCLES, Cycle */ - .supported =3D event_always_supported, - .get_count =3D cycles_get_count, - .ns_per_count =3D cycles_ns_per, - }, -#endif - { .number =3D 0x023, /* STALL_FRONTEND */ - .supported =3D pmuv3p1_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, - { .number =3D 0x024, /* STALL_BACKEND */ - .supported =3D pmuv3p1_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, - { .number =3D 0x03c, /* STALL */ - .supported =3D pmuv3p4_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, -}; - -/* - * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range = of - * events (i.e. the statistical profiling extension), this implementation - * should first be updated to something sparse instead of the current - * supported_event_map[] array. - */ -#define MAX_EVENT_ID 0x3c -#define UNSUPPORTED_EVENT UINT16_MAX -static uint16_t supported_event_map[MAX_EVENT_ID + 1]; - -/* - * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map - * of ARM event numbers to indices in our pm_events array. - * - * Note: Events in the 0x40XX range are not currently supported. - */ -void pmu_init(ARMCPU *cpu) -{ - unsigned int i; - - /* - * Empty supported_event_map and cpu->pmceid[01] before adding support= ed - * events to them - */ - for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { - supported_event_map[i] =3D UNSUPPORTED_EVENT; - } - cpu->pmceid0 =3D 0; - cpu->pmceid1 =3D 0; - - for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { - const pm_event *cnt =3D &pm_events[i]; - assert(cnt->number <=3D MAX_EVENT_ID); - /* We do not currently support events in the 0x40xx range */ - assert(cnt->number <=3D 0x3f); - - if (cnt->supported(&cpu->env)) { - supported_event_map[cnt->number] =3D i; - uint64_t event_mask =3D 1ULL << (cnt->number & 0x1f); - if (cnt->number & 0x20) { - cpu->pmceid1 |=3D event_mask; - } else { - cpu->pmceid0 |=3D event_mask; - } - } - } -} - -/* - * Check at runtime whether a PMU event is supported for the current machi= ne - */ -static bool event_supported(uint16_t number) -{ - if (number > MAX_EVENT_ID) { - return false; - } - return supported_event_map[number] !=3D UNSUPPORTED_EVENT; -} - -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* - * Performance monitor registers user accessibility is controlled - * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable - * trapping to EL2 or EL3 for other accesses. - */ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - - if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { - return CP_ACCESS_TRAP_EL1; - } - if (el < 2 && (mdcr_el2 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* ER: event counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0 - && isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_swinc(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* SW: software increment write trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 1)) !=3D 0 - && !isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_selr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* ER: event counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_ccntr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* CR: cycle counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 2)) !=3D 0 - && isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - /* * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. * We use these to decide whether we need to wrap a write to MDCR_EL2 @@ -967,684 +669,6 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState = *env, (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) =20 -/* - * Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing - * the current EL, security state, and register configuration. - */ -static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) -{ - uint64_t filter; - bool e, p, u, nsk, nsu, nsh, m; - bool enabled, prohibited =3D false, filtered; - bool secure =3D arm_is_secure(env); - int el =3D arm_current_el(env); - uint64_t mdcr_el2; - uint8_t hpmn; - - /* - * We might be called for M-profile cores where MDCR_EL2 doesn't - * exist and arm_mdcr_el2_eff() will assert, so this early-exit check - * must be before we read that value. - */ - if (!arm_feature(env, ARM_FEATURE_PMU)) { - return false; - } - - mdcr_el2 =3D arm_mdcr_el2_eff(env); - hpmn =3D mdcr_el2 & MDCR_HPMN; - - if (!arm_feature(env, ARM_FEATURE_EL2) || - (counter < hpmn || counter =3D=3D 31)) { - e =3D env->cp15.c9_pmcr & PMCRE; - } else { - e =3D mdcr_el2 & MDCR_HPME; - } - enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); - - /* Is event counting prohibited? */ - if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { - prohibited =3D mdcr_el2 & MDCR_HPMD; - } - if (secure) { - prohibited =3D prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); - } - - if (counter =3D=3D 31) { - /* - * The cycle counter defaults to running. PMCR.DP says "disable - * the cycle counter when event counting is prohibited". - * Some MDCR bits disable the cycle counter specifically. - */ - prohibited =3D prohibited && env->cp15.c9_pmcr & PMCRDP; - if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { - if (secure) { - prohibited =3D prohibited || (env->cp15.mdcr_el3 & MDCR_SC= CD); - } - if (el =3D=3D 2) { - prohibited =3D prohibited || (mdcr_el2 & MDCR_HCCD); - } - } - } - - if (counter =3D=3D 31) { - filter =3D env->cp15.pmccfiltr_el0; - } else { - filter =3D env->cp15.c14_pmevtyper[counter]; - } - - p =3D filter & PMXEVTYPER_P; - u =3D filter & PMXEVTYPER_U; - nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); - nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); - nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); - m =3D arm_el_is_aa64(env, 1) && - arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); - - if (el =3D=3D 0) { - filtered =3D secure ? u : u !=3D nsu; - } else if (el =3D=3D 1) { - filtered =3D secure ? p : p !=3D nsk; - } else if (el =3D=3D 2) { - filtered =3D !nsh; - } else { /* EL3 */ - filtered =3D m !=3D p; - } - - if (counter !=3D 31) { - /* - * If not checking PMCCNTR, ensure the counter is setup to an even= t we - * support - */ - uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; - if (!event_supported(event)) { - return false; - } - } - - return enabled && !prohibited && !filtered; -} - -static void pmu_update_irq(CPUARMState *env) -{ - ARMCPU *cpu =3D env_archcpu(env); - qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && - (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); -} - -static bool pmccntr_clockdiv_enabled(CPUARMState *env) -{ - /* - * Return true if the clock divider is enabled and the cycle counter - * is supposed to tick only once every 64 clock cycles. This is - * controlled by PMCR.D, but if PMCR.LC is set to enable the long - * (64-bit) cycle counter PMCR.D has no effect. - */ - return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) =3D=3D PMCRD; -} - -static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) -{ - /* Return true if the specified event counter is configured to be 64 b= it */ - - /* This isn't intended to be used with the cycle counter */ - assert(counter < 31); - - if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { - return false; - } - - if (arm_feature(env, ARM_FEATURE_EL2)) { - /* - * MDCR_EL2.HLP still applies even when EL2 is disabled in the - * current security state, so we don't use arm_mdcr_el2_eff() here. - */ - bool hlp =3D env->cp15.mdcr_el2 & MDCR_HLP; - int hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; - - if (counter >=3D hpmn) { - return hlp; - } - } - return env->cp15.c9_pmcr & PMCRLP; -} - -/* - * Ensure c15_ccnt is the guest-visible count so that operations such as - * enabling/disabling the counter or filtering, modifying the count itself, - * etc. can be done logically. This is essentially a no-op if the counter = is - * not enabled at the time of the call. - */ -static void pmccntr_op_start(CPUARMState *env) -{ - uint64_t cycles =3D cycles_get_count(env); - - if (pmu_counter_enabled(env, 31)) { - uint64_t eff_cycles =3D cycles; - if (pmccntr_clockdiv_enabled(env)) { - eff_cycles /=3D 64; - } - - uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; - - uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \ - 1ull << 63 : 1ull << 31; - if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { - env->cp15.c9_pmovsr |=3D (1ULL << 31); - pmu_update_irq(env); - } - - env->cp15.c15_ccnt =3D new_pmccntr; - } - env->cp15.c15_ccnt_delta =3D cycles; -} - -/* - * If PMCCNTR is enabled, recalculate the delta between the clock and the - * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to - * pmccntr_op_start. - */ -static void pmccntr_op_finish(CPUARMState *env) -{ - if (pmu_counter_enabled(env, 31)) { -#ifndef CONFIG_USER_ONLY - /* Calculate when the counter will next overflow */ - uint64_t remaining_cycles =3D -env->cp15.c15_ccnt; - if (!(env->cp15.c9_pmcr & PMCRLC)) { - remaining_cycles =3D (uint32_t)remaining_cycles; - } - int64_t overflow_in =3D cycles_ns_per(remaining_cycles); - - if (overflow_in > 0) { - int64_t overflow_at; - - if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - overflow_in, &overflow_at)) { - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); - } - } -#endif - - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; - if (pmccntr_clockdiv_enabled(env)) { - prev_cycles /=3D 64; - } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; - } -} - -static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) -{ - - uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; - uint64_t count =3D 0; - if (event_supported(event)) { - uint16_t event_idx =3D supported_event_map[event]; - count =3D pm_events[event_idx].get_count(env); - } - - if (pmu_counter_enabled(env, counter)) { - uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; - uint64_t overflow_mask =3D pmevcntr_is_64_bit(env, counter) ? - 1ULL << 63 : 1ULL << 31; - - if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mas= k) { - env->cp15.c9_pmovsr |=3D (1 << counter); - pmu_update_irq(env); - } - env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; - } - env->cp15.c14_pmevcntr_delta[counter] =3D count; -} - -static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) -{ - if (pmu_counter_enabled(env, counter)) { -#ifndef CONFIG_USER_ONLY - uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; - uint16_t event_idx =3D supported_event_map[event]; - uint64_t delta =3D -(env->cp15.c14_pmevcntr[counter] + 1); - int64_t overflow_in; - - if (!pmevcntr_is_64_bit(env, counter)) { - delta =3D (uint32_t)delta; - } - overflow_in =3D pm_events[event_idx].ns_per_count(delta); - - if (overflow_in > 0) { - int64_t overflow_at; - - if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - overflow_in, &overflow_at)) { - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); - } - } -#endif - - env->cp15.c14_pmevcntr_delta[counter] -=3D - env->cp15.c14_pmevcntr[counter]; - } -} - -void pmu_op_start(CPUARMState *env) -{ - unsigned int i; - pmccntr_op_start(env); - for (i =3D 0; i < pmu_num_counters(env); i++) { - pmevcntr_op_start(env, i); - } -} - -void pmu_op_finish(CPUARMState *env) -{ - unsigned int i; - pmccntr_op_finish(env); - for (i =3D 0; i < pmu_num_counters(env); i++) { - pmevcntr_op_finish(env, i); - } -} - -void pmu_pre_el_change(ARMCPU *cpu, void *ignored) -{ - pmu_op_start(&cpu->env); -} - -void pmu_post_el_change(ARMCPU *cpu, void *ignored) -{ - pmu_op_finish(&cpu->env); -} - -void arm_pmu_timer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - /* - * Update all the counter values based on the current underlying count= s, - * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso - * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a - * counter may expire. - */ - pmu_op_start(&cpu->env); - pmu_op_finish(&cpu->env); -} - -static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmu_op_start(env); - - if (value & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt =3D 0; - } - - if (value & PMCRP) { - unsigned int i; - for (i =3D 0; i < pmu_num_counters(env); i++) { - env->cp15.c14_pmevcntr[i] =3D 0; - } - } - - env->cp15.c9_pmcr &=3D ~PMCR_WRITABLE_MASK; - env->cp15.c9_pmcr |=3D (value & PMCR_WRITABLE_MASK); - - pmu_op_finish(env); -} - -static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint64_t pmcr =3D env->cp15.c9_pmcr; - - /* - * If EL2 is implemented and enabled for the current security state, r= eads - * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR= .HPMN. - */ - if (arm_current_el(env) <=3D 1 && arm_is_el2_enabled(env)) { - pmcr &=3D ~PMCRN_MASK; - pmcr |=3D (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; - } - - return pmcr; -} - -static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - unsigned int i; - uint64_t overflow_mask, new_pmswinc; - - for (i =3D 0; i < pmu_num_counters(env); i++) { - /* Increment a counter's count iff: */ - if ((value & (1 << i)) && /* counter's bit is set */ - /* counter is enabled and not filtered */ - pmu_counter_enabled(env, i) && - /* counter is SW_INCR */ - (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { - pmevcntr_op_start(env, i); - - /* - * Detect if this write causes an overflow since we can't pred= ict - * PMSWINC overflows like we can for other events - */ - new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; - - overflow_mask =3D pmevcntr_is_64_bit(env, i) ? - 1ULL << 63 : 1ULL << 31; - - if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { - env->cp15.c9_pmovsr |=3D (1 << i); - pmu_update_irq(env); - } - - env->cp15.c14_pmevcntr[i] =3D new_pmswinc; - - pmevcntr_op_finish(env, i); - } - } -} - -static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint64_t ret; - pmccntr_op_start(env); - ret =3D env->cp15.c15_ccnt; - pmccntr_op_finish(env); - return ret; -} - -static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and - * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the - * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are - * accessed. - */ - env->cp15.c9_pmselr =3D value & 0x1f; -} - -static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - env->cp15.c15_ccnt =3D value; - pmccntr_op_finish(env); -} - -static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint64_t cur_val =3D pmccntr_read(env, NULL); - - pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); -} - -static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; - pmccntr_op_finish(env); -} - -static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - /* M is not accessible from AArch32 */ - env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | - (value & PMCCFILTR); - pmccntr_op_finish(env); -} - -static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) -{ - /* M is not visible in AArch32 */ - return env->cp15.pmccfiltr_el0 & PMCCFILTR; -} - -static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmu_op_start(env); - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmcnten |=3D value; - pmu_op_finish(env); -} - -static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmu_op_start(env); - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmcnten &=3D ~value; - pmu_op_finish(env); -} - -static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmovsr &=3D ~value; - pmu_update_irq(env); -} - -static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmovsr |=3D value; - pmu_update_irq(env); -} - -static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value, const uint8_t counter) -{ - if (counter =3D=3D 31) { - pmccfiltr_write(env, ri, value); - } else if (counter < pmu_num_counters(env)) { - pmevcntr_op_start(env, counter); - - /* - * If this counter's event type is changing, store the current - * underlying count for the new type in c14_pmevcntr_delta[counter= ] so - * pmevcntr_op_finish has the correct baseline when it converts ba= ck to - * a delta. - */ - uint16_t old_event =3D env->cp15.c14_pmevtyper[counter] & - PMXEVTYPER_EVTCOUNT; - uint16_t new_event =3D value & PMXEVTYPER_EVTCOUNT; - if (old_event !=3D new_event) { - uint64_t count =3D 0; - if (event_supported(new_event)) { - uint16_t event_idx =3D supported_event_map[new_event]; - count =3D pm_events[event_idx].get_count(env); - } - env->cp15.c14_pmevcntr_delta[counter] =3D count; - } - - env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; - pmevcntr_op_finish(env, counter); - } - /* - * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when - * PMSELR value is equal to or greater than the number of implemented - * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. - */ -} - -static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, - const uint8_t counter) -{ - if (counter =3D=3D 31) { - return env->cp15.pmccfiltr_el0; - } else if (counter < pmu_num_counters(env)) { - return env->cp15.c14_pmevtyper[counter]; - } else { - /* - * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). - */ - return 0; - } -} - -static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - pmevtyper_write(env, ri, value, counter); -} - -static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - env->cp15.c14_pmevtyper[counter] =3D value; - - /* - * pmevtyper_rawwrite is called between a pair of pmu_op_start and - * pmu_op_finish calls when loading saved state for a migration. Becau= se - * we're potentially updating the type of event here, the value writte= n to - * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a - * different counter type. Therefore, we need to set this value to the - * current count for the counter type we're writing so that pmu_op_fin= ish - * has the correct count for its calculation. - */ - uint16_t event =3D value & PMXEVTYPER_EVTCOUNT; - if (event_supported(event)) { - uint16_t event_idx =3D supported_event_map[event]; - env->cp15.c14_pmevcntr_delta[counter] =3D - pm_events[event_idx].get_count(env); - } -} - -static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - return pmevtyper_read(env, ri, counter); -} - -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); -} - -static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); -} - -static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value, uint8_t counter) -{ - if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { - /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ - value &=3D MAKE_64BIT_MASK(0, 32); - } - if (counter < pmu_num_counters(env)) { - pmevcntr_op_start(env, counter); - env->cp15.c14_pmevcntr[counter] =3D value; - pmevcntr_op_finish(env, counter); - } - /* - * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. - */ -} - -static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint8_t counter) -{ - if (counter < pmu_num_counters(env)) { - uint64_t ret; - pmevcntr_op_start(env, counter); - ret =3D env->cp15.c14_pmevcntr[counter]; - pmevcntr_op_finish(env, counter); - if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { - /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0= */ - ret &=3D MAKE_64BIT_MASK(0, 32); - } - return ret; - } else { - /* - * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. - */ - return 0; - } -} - -static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - pmevcntr_write(env, ri, value, counter); -} - -static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - return pmevcntr_read(env, ri, counter); -} - -static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - assert(counter < pmu_num_counters(env)); - env->cp15.c14_pmevcntr[counter] =3D value; - pmevcntr_write(env, ri, value, counter); -} - -static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - assert(counter < pmu_num_counters(env)); - return env->cp15.c14_pmevcntr[counter]; -} - -static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); -} - -static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); -} - -static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - env->cp15.c9_pmuserenr =3D value & 0xf; - } else { - env->cp15.c9_pmuserenr =3D value & 1; - } -} - -static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* We have no event counters so only the C bit can be changed */ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pminten |=3D value; - pmu_update_irq(env); -} - -static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pminten &=3D ~value; - pmu_update_irq(env); -} - static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1874,171 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* - * Performance monitors are implementation defined in v7, - * but with an ARM recommended set of registers, which we - * follow. - * - * Performance registers fall into three categories: - * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) - * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) - * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) - * For the cases controlled by PMUSERENR we must set .access to PL0_RW - * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. - */ - { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenset_write, - .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCNTEN, - .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, .type =3D = ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCNTEN, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, - .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCNTEN, - .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write, - .type =3D ARM_CP_ALIAS | ARM_CP_IO }, - { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCNTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenclr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .type =3D ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), - .accessfn =3D pmreg_access, - .fgt =3D FGT_PMOVS, - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMOVS, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, - .fgt =3D FGT_PMSWINC_EL0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .writefn =3D pmswinc_write }, - { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, - .fgt =3D FGT_PMSWINC_EL0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .writefn =3D pmswinc_write }, - { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, - .fgt =3D FGT_PMSELR_EL0, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), - .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, - .raw_writefn =3D raw_write}, - { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, - .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, - .fgt =3D FGT_PMSELR_EL0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), - .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, - .fgt =3D FGT_PMCCNTR_EL0, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, - .accessfn =3D pmreg_access_ccntr }, - { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, - .fgt =3D FGT_PMCCNTR_EL0, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, - .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCCFILTR_EL0, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .resetvalue =3D 0, }, - { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCCFILTR_EL0, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), - .resetvalue =3D 0, }, - { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access, - .fgt =3D FGT_PMEVTYPERN_EL0, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access, - .fgt =3D FGT_PMEVTYPERN_EL0, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access_xevcntr, - .fgt =3D FGT_PMEVCNTRN_EL0, - .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, - { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access_xevcntr, - .fgt =3D FGT_PMEVCNTRN_EL0, - .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, - { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), - .resetvalue =3D 0, - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, - .resetvalue =3D 0x0 }, - { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .fgt =3D FGT_PMINTEN, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, .raw_writefn =3D raw_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, .access =3D PL1_R, @@ -2121,25 +980,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, }; =20 -static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { - /* PMOVSSET is not implemented in v7 before v7ve */ - { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMOVS, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsset_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMOVS, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsset_write, - .raw_writefn =3D raw_write }, -}; - static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -6356,105 +5196,6 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 -static void define_pmu_regs(ARMCPU *cpu) -{ - /* - * v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn =3D pmu_num_counters(&cpu->env); - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_RW, - .fgt =3D FGT_PMCR_EL0, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, - .readfn =3D pmcr_read, .raw_readfn =3D raw_read, - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fgt =3D FGT_PMCR_EL0, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->isar.reset_pmcr_el0, - .readfn =3D pmcr_read, .raw_readfn =3D raw_read, - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i =3D 0; i < pmcrn; i++) { - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); - ARMCPRegInfo pmev_regs[] =3D { - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fgt =3D FGT_PMEVCNTRN_EL0, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, - .accessfn =3D pmreg_access_xevcntr }, - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess_xevcntr, - .type =3D ARM_CP_IO, - .fgt =3D FGT_PMEVCNTRN_EL0, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, - .raw_readfn =3D pmevcntr_rawread, - .raw_writefn =3D pmevcntr_rawwrite }, - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fgt =3D FGT_PMEVTYPERN_EL0, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, - .fgt =3D FGT_PMEVTYPERN_EL0, - .type =3D ARM_CP_IO, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, - .raw_writefn =3D pmevtyper_rawwrite }, - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } - if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { - ARMCPRegInfo v81_pmu_regs[] =3D { - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } - if (cpu_isar_feature(any_pmuv3p4, cpu)) { - static const ARMCPRegInfo v84_pmmir =3D { - .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, - .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, - .fgt =3D FGT_PMMIR_EL1, - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &v84_pmmir); - } -} - #ifndef CONFIG_USER_ONLY /* * We don't know until after realize whether there's a GICv3 @@ -7385,9 +6126,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_V6K)) { define_arm_cp_regs(cpu, v6k_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_V7VE)) { - define_arm_cp_regs(cpu, pmovsset_cp_reginfo); - } if (arm_feature(env, ARM_FEATURE_V7)) { ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, @@ -7400,7 +6138,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); - define_pmu_regs(cpu); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } @@ -7656,26 +6393,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D 0 }, - { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, - { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D cpu->pmceid0 }, - { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, - { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .fgt =3D FGT_PMCEIDN_EL0, - .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { @@ -8514,6 +7231,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ccsidr2_reginfo); } =20 + define_pm_cpregs(cpu); + #ifndef CONFIG_USER_ONLY /* * Register redirections and aliases must be done last, diff --git a/target/arm/meson.build b/target/arm/meson.build index 7aa81e30aba..07d9271aa4d 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -22,6 +22,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c', )) arm_user_ss.add(files( + 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', 'vfp_fpscr.c', @@ -36,6 +37,7 @@ arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'cortex-regs.c', + 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', 'machine.c', --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241030803786.9556011591943; Fri, 11 Jul 2025 06:37:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDv9-0007SN-QC; Fri, 11 Jul 2025 09:36:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu4-0004X2-Q3 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:06 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDtz-00039U-Kk for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:04 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4530921461aso13857985e9.0 for ; Fri, 11 Jul 2025 06:34:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240898; x=1752845698; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yJpsUbLyNcANLnSnQf19yaGPSwfDJstWb2tmsgZQyko=; b=vs42TLur7bsCJ9TEnof0/QViBZ4EA24rw9mnoV8GIx72kwyiyZMHZqV9U9hG1+14Dn L52ne2bq7cIJK7X07jDfh2dmlL6WNqxcTjihMU0OKviqW+JappwrU3T9D8e4ATR0YPHO 2Z1bRU7NZodcAwO0j+u81gLPDF6EJaF0jZST5nCPSlwsJ2D2dX8veFPuWd/VnIGyRHo1 rilmdUlTqZNvQk12PLICVwJ+d2WPfznu+KeRxIb1eQei4PRX3sECJ1JsZZMW8weK8Ijn pqRXanS98nSZbR28uxJr0wTBRK0d2NflHSVRQGU/U5f0h/JjhfOnYn3iQxmUvrtUo03B t5iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240898; x=1752845698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yJpsUbLyNcANLnSnQf19yaGPSwfDJstWb2tmsgZQyko=; b=RQZnYcYvl81GN1vlwrw6hMh9CoesUD3aaISc8iqQAWt6NmY4Fowg5WN7w0ATdP3faV FhoqzlwMIf5NZuk3mMI57R0RRxZBmKRLa5ekuZnxf/dCcRpPfMKxVch9Ak/6GLODICTY X5GxID5hxn2tDPk49ZjhhUEN/W48u3Chj6n2/5yxXw1wo6vTj911fpzatuKCtEWVoGOw ++RZBnoEjyD9vJCKnWcQ7CDxcjmvC/ZDmagnXa8DCxKG0WU8sGbf/T+c0viwn7/RLMcl /di3fDZ78e3mc+/guWqi83DjKwkplrPUd3yr/DCMGlxmHn83b5PqJYyqy1YrARY3xB8r 9KEA== X-Gm-Message-State: AOJu0Yy3tLrIn32bWYCG0D45ohQJTUclicbPZ9di4gK7dBgyEIumTklA 3WO6RWmDRcIRDojAqz4qPiNwyTEjmqQMzgVIhsvZKhF1sbt748KxHe2DjMW2vfbZOMu/bMwoUu2 0F/DJ X-Gm-Gg: ASbGncsNr1a/Z7R5cEjav5wtLa4/CiR9EpoGmFO5fJwDQliStO3y4ala1lF5CaLNejQ UTgnb4tSDJIgc1cVAIL3O86mrarSQt3njWeRTGWW8WCK5NkZkZQShWV0v7IDqqIij8y8rzXAvsJ V8BBA/mOs2fxrMGTXkPi/1xymJHhA4Gc/C92niGUvLuy4NBxhz9+1xqlWRzaeVng6aguR/lvnpm sE/kUng76oUVJVwe4Qcut+qxe0BoA1FiayHUTCg9WLHjlcbt7Rt+V7iJ/8r5aU29Ckcmk0uw1nI 1a8XSUFo9lnBoEhL5G83D+Vcyfqk1zzQP9ubKukJ1VZ4qyFm4IbtNCQsPByOWZJK5ewEmKIujIY Ws5cWplng4SsQmBL+n1/yWv9IkqdD X-Google-Smtp-Source: AGHT+IHmDjd6IBufunn+VXUbW45gEy2L5kG1BIp/bGnrz4HrD/HhnppUFhmPn2QSvyKnWtzFwDWHpg== X-Received: by 2002:a05:600c:3d8f:b0:43c:fbba:41ba with SMTP id 5b1f17b1804b1-45565edca7emr21236675e9.28.1752240897891; Fri, 11 Jul 2025 06:34:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/36] target/arm: Don't enforce NSE, NS check for EL3->EL3 returns Date: Fri, 11 Jul 2025 14:34:18 +0100 Message-ID: <20250711133429.1423030-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1752241032396116600 Content-Type: text/plain; charset="utf-8" In the Arm ARM, rule R_TYTWB that defines illegal exception return cases includes the case: If FEAT_RME is implemented, then if SCR_EL3.{NSE, NS} is {1, 0}, an exception return from EL3 to a lower Exception level Our implementation of this check fails to check that the return is to a lower exception level, so it will incorrectly fire on EL3->EL3 exception returns. Fix the check condition. This requires us to move it further down in the function to a point where we know the new_el value. Fixes: 35aa6715ddcd9 ("target/arm: Catch illegal-exception-return from EL3 = with bad NSE/NS") Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3016 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250704165636.261888-1-peter.maydell@linaro.org --- target/arm/tcg/helper-a64.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index c66d521278c..71c6c44ee8a 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -658,15 +658,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64= _t new_pc) spsr &=3D ~PSTATE_SS; } =20 - /* - * FEAT_RME forbids return from EL3 with an invalid security state. - * We don't need an explicit check for FEAT_RME here because we enforce - * in scr_write() that you can't set the NSE bit without it. - */ - if (cur_el =3D=3D 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) =3D=3D= SCR_NSE) { - goto illegal_return; - } - new_el =3D el_from_spsr(spsr); if (new_el =3D=3D -1) { goto illegal_return; @@ -678,6 +669,17 @@ void HELPER(exception_return)(CPUARMState *env, uint64= _t new_pc) goto illegal_return; } =20 + /* + * FEAT_RME forbids return from EL3 to a lower exception level + * with an invalid security state. + * We don't need an explicit check for FEAT_RME here because we enforce + * in scr_write() that you can't set the NSE bit without it. + */ + if (cur_el =3D=3D 3 && new_el < 3 && + (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) =3D=3D SCR_NSE) { + goto illegal_return; + } + if (new_el !=3D 0 && arm_el_is_aa64(env, new_el) !=3D return_to_aa64) { /* Return to an EL which is configured for a different register wi= dth */ goto illegal_return; --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241127; cv=none; d=zohomail.com; s=zohoarc; b=F1K2SKAmg4UwoT2/6ly0wkezjbGXEY95GoWux9kGUNjNlr20oPWH0blFjmBudsKEKjeb4nr/0pD6/03sKlAo3KNN8jGQS8zLSypFtH7euyWcQa2WiKHH8R1Q9Kvgm2SUWFB7r+bgo5vZCJwKvk5mXecq0wpqqJG2MhHdUbc9sME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241127; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tnq7IbYE5RKAsvS2Bxpq4+1qdk4LhwMgwm937ZzNCaw=; b=Spr0bk/EQzDaEps4rzbNc9clkiy8Xmo+dOUElv1tWlv4KTNyz0aPAbNZYgRWkp8SvufWTp0aT6I7uIdjm3220lQQL1Le6ghgQ5DnJ2z7E0Xmly5LYfNuRctXKbUYwcYMxOAoWAkgaLscSEKber4IhInl81BLv1SFZCr2KybWH2U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241127888559.724286385114; Fri, 11 Jul 2025 06:38:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDum-0005vE-68; Fri, 11 Jul 2025 09:35:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu3-0004Wr-IL for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:06 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu0-00039w-SV for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:03 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4550709f2c1so4525925e9.3 for ; Fri, 11 Jul 2025 06:35:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240899; x=1752845699; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tnq7IbYE5RKAsvS2Bxpq4+1qdk4LhwMgwm937ZzNCaw=; b=V+4pJ+YVbNoGqlYE9VmLCBzN9IKFkhMBZbvPfAtjrHRb0HfROw53LH+b1CxWtvw1Pb qFx8FUwBdJJkGdEuX1qYil9vJDlnHAWHRwJejk5WwEm9skQGkmeOfKpXGd2yec5jGUeX 5cw1ZGUasjJFWEed3+HDb6F4MrjHqzJhvM0Dug9QpeFdCi3SKq1PVRQgDBMcv4r37nIp v4LwFNIbf0CypZV2ARnJfEAuWibYyQbV1P0xhiMDBEnJtvt24RFdehjFHS8n38BWV38Q HEBfjjr25zd0L0J5GVFdDMc1gvgzyMYzHKveDN1MADxx7mzvYUrmVWke1HxMZ/wrRNaD qtvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240899; x=1752845699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tnq7IbYE5RKAsvS2Bxpq4+1qdk4LhwMgwm937ZzNCaw=; b=YYzWEBTNMS2rMfXOF5oW/2S1bT77tSW+ifvQKNyB8fwm11DOlykFc7mozgkPrvifux m9z7rkHEtK9syLpHHEWVsor4mj9l/h+29FCJ2nYRjAUPNoygjxqW37OzhpPmWkQNM6EB Q11biTMGkEAmS4gqBXXhwSI1RPsZrTAk2nrtoAie1iSUJvfjQ6PcVo5t8eRnEg/p3Hzh FJphK5ce0pfaNBdWsZn8wtvpBd2432obQHPMNmRiwe+G47traMsSecC7+lj16utuO58k hsoTelLAUyOgj+gLLqGfvFqjJT2closZx0u54RKhxbxl6gC6C9bUtoksILIn3TaTuUB3 I7og== X-Gm-Message-State: AOJu0YwQXqJTAsJ/DK2QN+VTpyf3dh4cvhpL2RXxMFs0aYXuO+4gtdve donFWbQmCqmhNlxX1rqNok/BWMMckMvLDSuBXBZbsLoCdQQyVQBuw/ZUB2BfC3KA/5bGJsBvFH1 995hk X-Gm-Gg: ASbGncvpGPD4ztNoPArR/KWCQp5ulEDTcGNkRR2ZaynIUAhRndP4rasTuNA0G6qsBlN zyNvxW+oXrpookyuyqUgFAd31ZknZDKAA/hohIVEZqy5M3yq26Hz4vPqa2qZeTg29pEz2mlH2jR XMpGx265fUMZ00TPPlUwQL7d6NS9fKwIXs12AipJDmrVnf18k5/t5dyo1wnHI8qCpvKcOsRcamw Cor2jwDGuph3Y7zeorEWcARXJauAzlBteAXSQZqk6bSdNaaDYRTPlR1cE5dPio2T07JEJy3IhNr fPdIfxMAw8VRuHi7ozrKROsBITihI7IJIboatvwE0FWfEtl28+oXv7dGo9rqLpCBPL8rI/Hws29 NWkZlIqxp7PZaiB4T4MaQu7wE7cVy X-Google-Smtp-Source: AGHT+IEtsFw5LE/Vgg0zO6MD31+lRph7HhXP6w+dBbP6b0YVVRkFt5HX6qpMg+e1W1CBGFp8TU49ag== X-Received: by 2002:a05:600c:8b84:b0:454:aedd:96fb with SMTP id 5b1f17b1804b1-454f4275fa0mr28996815e9.29.1752240898909; Fri, 11 Jul 2025 06:34:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/36] hw/arm/fsl-imx8mp: Wire VIRQ and VFIQ Date: Fri, 11 Jul 2025 14:34:19 +0100 Message-ID: <20250711133429.1423030-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241129572116600 From: Bernhard Beschow Allows to run KVM guests inside the imx8mp-evk machine. Fixes: a4eefc69b237 ("hw/arm: Add i.MX 8M Plus EVK board") CC: qemu-stable Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- hw/arm/fsl-imx8mp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 23e662c16ca..866f4d1d740 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -356,6 +356,10 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); sysbus_connect_irq(gicsbd, i + ms->smp.cpus, qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicsbd, i + 2 * ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicsbd, i + 3 * ms->smp.cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } } =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241144; cv=none; d=zohomail.com; s=zohoarc; b=c0Tb2CUWe756xNuhH5ScwLyGoHSL+qUx8sG1bD9ecIt6EW6Bs3JN+DQE3sRppCRT5xJZ4p0OUCJOPfzYPA6ugpjZZ2kOyC33XHqZiyQH/6YWiPx5YwX3/RjG1DzDATYk39GRgCegmGtqsZVVVJWgcHSrk1rvPekrB0BLEludbpg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241144; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=SmuGdusT+795T8OqqPDbbZnsjy/qkrk4vaiaLtn1uU8=; b=WRUQ9P9Ht6fH5j/07vKdryAPsVYMo33ol455cEixDkM8uKl99BfB8MWDxZfKFQ4VFWEXwDz85RMecTvlH1zoIRKML9iVfNWwse+Ytvwi4a382d31oMMw9Hz+9hvyee15dgcVSpEij2EW6JFOvWxvzkYkFBBYbE/G60dNSZ6FRLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241144406958.3799853461808; Fri, 11 Jul 2025 06:39:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuz-0006iT-0I; Fri, 11 Jul 2025 09:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu4-0004X3-QC for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:06 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu1-0003AP-O5 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:03 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4537fdec39fso6622065e9.0 for ; Fri, 11 Jul 2025 06:35:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.34.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:34:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240900; x=1752845700; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SmuGdusT+795T8OqqPDbbZnsjy/qkrk4vaiaLtn1uU8=; b=cNr9ZriCYfUY5lBqdqqOL+9NTxZsNyL0zEczLsX80fiuJL2e+dU82bPGrm7zgTxZSR PMIGHze2pfgS0Je422ZdFA1uxwGxS5hVS13Pd4OzPBrTOoyfebvv/R3O4S3Ej7GpaFnM JUWOqagpGzhQYUVwyDmn3Uu7V5p7lsGlFevNNAanULvBK+iNa3Guhx/zScdfhgsvUKiB AuOC/JxwC4cgdBAp6r9uAjbkETY0H6FmhFeaJccQuA+PlfYAzTGWcqz5Kn9CZt90kRCu 0J+knDZJgBTvsbJk5j6Jp8yIkkEOujT+3l0w2TUJF/ZbPJdCWGF/tEH9+WDHaj+4rgme IdWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240900; x=1752845700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SmuGdusT+795T8OqqPDbbZnsjy/qkrk4vaiaLtn1uU8=; b=MUlmpt2K3EwHklJPqQJU9kUnJqq9Jbr8DMcLRrH+gPnnOfw19zTXy2ZG996ZP9Avqi 7zK/zA5xv41SV8VG5+OKVKLgEokBSVk/UnRldPGisgj2ZhcOtWywsfYmpc6N/2U9Wlkc alGBMmHkvRDM4RmNNJymsAlx+7ZVUUHxvu5UZIpCJxHiyXAIUlmynWf7r+NGU8pEeHCP uvdGks5RUYW2u8hOGt9uDFESrdsmV6BKv9+uMSDXujODamwRAjEFBHdQAbKlDPq/nUSs Y+LcFYM6eWslcrUAVheUn1/38IOTzlk9RLUfr/NU+FdM4UyCa7WEvZaK5ETMWcgvyX5U e+fg== X-Gm-Message-State: AOJu0YzIDrhAX3I6yGVXeO/QmA58E3BniPDeX6sL26sOqdFZIpTWtSPN HBKq9oPcLqYcaPVigKQJeiSH5nWzUBSM+k3Dj2rI5eja5fTJd9Y4OUcZF22q61mKhYc838vaiQf CwvWF X-Gm-Gg: ASbGncu8eCLEjXAWo2zrvc9j4Y41ureUWZe6EqUtFXYnFQyvGCp2hLIblLAJ//bQcwC nHAlC1TaBJKEeW4Hnz8hlktbBlOQVpeEs4VgfZ3AygSyEjrjdHA1Zy+jU8raBGOaL1AEh1utkfq BxkSMnb5qwZBJHOBmGHt/7SjaLJsTIeoDAekklkgtnmbfIhjBigI1PmSuWx1yFn+KOLgfxUhryG d2riE1YxfdTt9xIKpRzwotfjZFyNN7NwrLbhcA1m6lxiJitHm3S/6NC7S+325TxzBjxyrpLqdyY PLp7dXBzm7uW/D3OD4kxDbsqSB6dv26Px0QYRl6931lmKPXCPgHt9MpHJjmMeY7WQQgEDg6EZgc UJ3Ha2dLOIvVFtoblQynbnNdNEPq8 X-Google-Smtp-Source: AGHT+IEG3I4h/1toVgrwbxsnGVl5zJoGzVEayRUUaBgx/H/LtoScrm9SFwuA7srgnvWhxGETf4lZhQ== X-Received: by 2002:a05:600c:3b05:b0:450:cd50:3c64 with SMTP id 5b1f17b1804b1-454f4274eb3mr34040715e9.31.1752240899935; Fri, 11 Jul 2025 06:34:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/36] hw/arm: Allow setting KVM vGIC maintenance IRQ Date: Fri, 11 Jul 2025 14:34:20 +0100 Message-ID: <20250711133429.1423030-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241146041116600 Content-Type: text/plain; charset="utf-8" From: Haibo Xu Allow virt arm machine to set the interrupt ID for the KVM GIC maintenance interrupt. This setting must be done before the KVM_DEV_ARM_VGIC_CTRL_INIT hence the choice to perform the setting in the GICv3 realize instead of proceeding the same way as kvm_arm_pmu_set_irq(). Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Message-id: 20250707164129.1167837-2-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/intc/arm_gicv3_common.h | 1 + hw/arm/virt.c | 3 +++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_kvm.c | 21 +++++++++++++++++++++ 4 files changed, 26 insertions(+) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index a3d6a0e5077..c18503869f9 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -231,6 +231,7 @@ struct GICv3State { uint32_t num_cpu; uint32_t num_irq; uint32_t revision; + uint32_t maint_irq; bool lpi_enable; bool nmi_support; bool security_extn; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 394e8b53018..c9f39919370 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -833,6 +833,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); } + } else if (vms->virt) { + qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", + ARCH_GIC_MAINT_IRQ); } } else { if (!kvm_irqchip_in_kernel()) { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 1cee68193ca..e438d8c042d 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -612,6 +612,7 @@ static const Property arm_gicv3_common_properties[] =3D= { DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), + DEFINE_PROP_UINT32("maintenance-interrupt-id", GICv3State, maint_irq, = 0), /* * Compatibility property: force 8 bits of physical priority, even * if the CPU being emulated should have fewer. diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3be3bf6c28d..b30aac7aee1 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -22,6 +22,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/arm/virt.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "system/kvm.h" @@ -825,6 +826,26 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) return; } =20 + if (s->maint_irq) { + int ret; + + ret =3D kvm_device_check_attr(s->dev_fd, + KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); + if (!ret) { + error_setg_errno(errp, errno, + "VGICv3 setting maintenance IRQ is not " + "supported by this host kernel"); + return; + } + + ret =3D kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IR= Q, 0, + &s->maint_irq, true, errp); + if (ret) { + error_setg_errno(errp, errno, "Failed to set VGIC maintenance = IRQ"); + return; + } + } + multiple_redist_region_allowed =3D kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241204; cv=none; d=zohomail.com; s=zohoarc; b=l2qrGikAbDjxGUrVC+BhNAg80Py/sjlTFa0IWiiXM8XvXULhZ+HDo53bqyrWtTF8pbgME7LEZXkOZW7fC+yAeODpcDKbatMYx0WZljWTLptDnLiir8HdIuXJvlj78XIaVIuZb1/a8K7Gx1OZzdj+3zzssau/RDn2xv+KaiHa1FU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241204; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uTXqJiKgfiB3QVh055cqmNddLyPU05fki5TAKLA/ZXA=; b=QxDm5i9TpOkgL72ofGAjfkKOUwlXqi7EvSFF1Q/IXY5DyUyK+VI01/c4W3QeJm2T/Vjbf2YnB94jx1Q9y9uZYrmepY3qi4S/Y6h0jGVQoDAcjMjL3yoi6ck5K345GxirwbQK0HEpKTHWCiP9xWErwCLTd1QG7FhzXaoT74mOLx0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241204388388.2008141155327; Fri, 11 Jul 2025 06:40:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDul-0005tA-4x; Fri, 11 Jul 2025 09:35:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu5-0004X8-1H for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:07 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu2-0003BB-N0 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:04 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3a510432236so1586098f8f.0 for ; Fri, 11 Jul 2025 06:35:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240901; x=1752845701; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uTXqJiKgfiB3QVh055cqmNddLyPU05fki5TAKLA/ZXA=; b=bP4punfSNMliHszV4JtUpntRws9here+yeHCGzeZVXVC9O/uggG6U+jIBg9eZqLf88 wbE6YA4CjjK/NZ6+pL9vwji6D+RbT44UVBripiGqIKv3rYThrKkoAjDaBYnhmpnXwfA+ 9uPfN/4HC8xEQpmiHpVm1UGbxkL+rbuLNB3xNvknsP0vxPC2CmFJEjbcrgudvdHellHB Mb3G0mnCzVEyutmVoWvGPcPUnDHvTlSnOwlG7pEoTF5laxI9a9q50GQJGNMkCyLHih7T NXTUnzo71g701OdAF2X/muXRcdwfQ39IinNfYqYQNrD6t9ZXWM9+TYdnkDWFjCCrS40K /5CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240901; x=1752845701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uTXqJiKgfiB3QVh055cqmNddLyPU05fki5TAKLA/ZXA=; b=E9xKkRiz22ZnTbnuFzEkdyeZb2eJGT1lOSeztSbqeJAs10ZzkPexsQJ5Rhlg8aqYjM 3//u2/G4weiq8TXvrsg4CN6WaszOfhcjfu/XPeTjyyjYcMPEe3WnHRYFeggl3j2kKxe4 J0JJe0g2anCxLF7rEYg4camMv6J8djLVIDe4WFRdgDuKMEXTRrVJbHhqfLjA/Icon4fb QKilj936lr2XnDRSJAsH7kqaru1mV/BJ7Dvx9qyrBCFcWkp9kQ1YHxA4Vrq3DcB/PM3U x1RpjBYmiYdljUX/tao1uZ2D+P21nzBQiAN2JNflNfVPifd4TD4qpfVvqJ6No880sg3m w7MA== X-Gm-Message-State: AOJu0YzcGs7lYZ9yQZaFuhJGzyclBo8QuX0Q0RvzT/n4+1wU2oUmLISN 7NdX4HuCaSL6nIuDlhQRusBUlzydT1e96ltCCRXACf1qDERt/QEFTwOKem64b7yDaBbXQk3im/5 AwAm5 X-Gm-Gg: ASbGncuIEEiFM1zsVO0LssyI1I7bgdfgubyVxWDhdQxhnKA78598NUY9hElsKWLq1O3 CF6qBCxtJ96ie7mBAcXlvyjAaPS6nDxhmwrxU03kRhnwSo3az4B3BDMAVZ682/cLEZ0c1a6ZNlo 3zYjcI7z6DP1irZtKVqSlocY1W+ccNC/Xfw1C6Ag/5djlDdi9snL5d6dcnA2aWR5vsW2weBddPy KUy8tySx8xibKg6fSC3wwUdSmsor0HjHGZYGTqGozNpFv0ERpoOWnEQ5PB3fQ7aUzmj92+5jnYG SSJz9K7lciIBM9X24JatmvRjxVBO6JAmCwaMWfOTfj8yn+oWOGOuGTk5Edva7iMXCzlsaxqA+Gz ejLD482Nxx8jxu5f8GSEL1YQKclGa X-Google-Smtp-Source: AGHT+IE3ZGbVoWSIwDYDfxvxpuao+ZOWXY94HhVG7gXy/mK6vcCN3d5Jcac2K/D1PuW2dV/Eel99lQ== X-Received: by 2002:a05:6000:2089:b0:3a6:e1bb:a083 with SMTP id ffacd0b85a97d-3b5f2dd2e52mr2849125f8f.25.1752240900941; Fri, 11 Jul 2025 06:35:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/36] target/arm/kvm: Add helper to detect EL2 when using KVM Date: Fri, 11 Jul 2025 14:34:21 +0100 Message-ID: <20250711133429.1423030-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241206890116600 From: Haibo Xu Introduce query support for KVM_CAP_ARM_EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20250707164129.1167837-3-eric.auger@redhat.com Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 7 +++++++ target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 7dc83caed5c..b4cad051551 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -191,6 +191,13 @@ bool kvm_arm_sve_supported(void); */ bool kvm_arm_mte_supported(void); =20 +/** + * kvm_arm_el2_supported: + * + * Returns true if KVM can enable EL2 and false otherwise. + */ +bool kvm_arm_el2_supported(void); + /** * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 34e57fab011..c93462c5b9b 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -47,6 +47,11 @@ bool kvm_arm_mte_supported(void) return false; } =20 +bool kvm_arm_el2_supported(void) +{ + return false; +} + /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8ab0d692d36..9fdf354f3bc 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1763,6 +1763,11 @@ bool kvm_arm_aarch32_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); } =20 +bool kvm_arm_el2_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL2); +} + bool kvm_arm_sve_supported(void) { return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241097; cv=none; d=zohomail.com; s=zohoarc; b=TyjmwrgLEIsM2ZnernLH7ts3r/5qwpG4T9Drz9jtiMF3GkeNRWkrVyCHYt//iGxB/EVF8PRZFCUagGwunuC1mHzOqJnfEkUbzRWRNSg6MpaMmeWDEobj/PLpm0c8Y0shfjCi4iQarQVrj5OWb4n5BoNE3qjB8h7RGib/ZxxnSu8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241097; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=WR2J2zJH+rNDC6JrmtA+Lka4FOQFLeYlEicPF+0JcK4=; b=J87o2reMreaJ8RYFkFGuUpxbPan8td+2n6Fvvto5GJcyFWDIIo4kH1yq+3ignBq24Hf7WD4yCqWnHMxietY0Ge/mtaRER0gGpGxuSiko1srjkB1jw6jxBADTnUF3YNhGqICjEHYbwZE/fT7rxEQVur8qEGt6NqoPIeJAwmaiXy8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241097740148.7851465264721; Fri, 11 Jul 2025 06:38:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDus-0006K7-II; Fri, 11 Jul 2025 09:35:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu7-0004XX-8O for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:11 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu4-0003Bg-Gi for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:06 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4537fdec33bso12537725e9.1 for ; Fri, 11 Jul 2025 06:35:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240902; x=1752845702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WR2J2zJH+rNDC6JrmtA+Lka4FOQFLeYlEicPF+0JcK4=; b=HCwaW2OU7MtVB1CerE3usBaZE6dmScQpZ9/OcNHEcWwp2JdwDFcNoLQbeDSBMBg+wx aKfeAUJfXRqL+IXrKOIXkD0CGHo3EIJ4EbUWJu+JkeH64JX1Di9OHHExFxrJuAVOm2n6 N0bAyRjwwaJXZITejaW+qUiL+qfZDI4FKk33GCxsrrN+uYa3XZG2i7Ff3My4tIY9fK8V a9wBWDGoc5JmnQLa+yrCfPKp35ja7lUzKA9TjcoUW301cLCzlgvWVuLIBZShmcVuNjNp k/ukxU1B9WQ89DkODGo5WH7ZKmmjo4jlI3dYTkVHJBurrHYSk+t3OJvOCNFKDEs6bn2/ PS6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240902; x=1752845702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WR2J2zJH+rNDC6JrmtA+Lka4FOQFLeYlEicPF+0JcK4=; b=ixGs78aqy+ehGPbIXU4R/RGuI4ODroKwJfUomq/xHkIypvABkF8Ccg2blcCjnRtFbI bvg2UJmHER0SDB6UkPdmLOK1fZl7l8Io9qVeYeaLZTlkDyZMfCi6bH1hz40SHtNpP0xW BHjxlQCmA8HuIDtPLNHbn5CCLpxC4pm39YPgWP0r530VPUWabAqwE62nidx76o6HfU/M CBZcu9s5z6ecaSvX7I3acYFXFF2oPy625vNrsEHqS+r1nkLf7O+2WzdAYFF0GilJXjxl vMdopNEWMLdrPm4EDrW3o58mDK1OzBvUxF3jLWp53PCN00Z8RU9Eu6oChSf5Yvo1OZOz ymsg== X-Gm-Message-State: AOJu0YwEOslK9P4XIMVbirMX7dfGsdfQoYdRl3dg2BV0S7foJpJXeP08 /GTtOQSN2XDfTMRQWAlcZwavDTFvHUTgf5erJxiyYtmkWNldOPfYEPJwd9OLm5jgBdddIa3KspA cgbJj X-Gm-Gg: ASbGncsEAHgRnKTqONTlMwOnQiQwAr1ARg1bCqER2QVg16Js4FNgZhaqTo4QVgpWssc gkg5DQDShryGoj9y7+WaRymMhLi1CeUGsWzUuRGBGyiZL1K9k6wOqLV1s1v4bxhkWfDD/2uCMbY LKz0QEOfBnj97WtxzG1JkHGkYIS92/k4LX8rsZ8wjWELBCnP+chAD0O1QSkINMn3eaH6XzTFUOk +C0jZj1inExqyVQSv3/hZSObs15s8cAgVooVsx1ECe81sI8+xIuypn+1xR8Ia0KLV0AFCjaF6BB 4V4DmNrCFPLNnuOlIauWN8Ot6dV21HJBE//Dn0haNrTpZQzpIgKV93mKsII/KWB5L8dKRtbtlcS RWlgm+4EM/FAVfTIEu5D0IsKJgPBQ X-Google-Smtp-Source: AGHT+IGnwClQrp9HmS4pVkheSS6sfKP5A9/hta470XaTJ/KxWYdes0Zzgwbkkw4buiSvfdxqJjjBzA== X-Received: by 2002:a05:600c:1c21:b0:43c:fe15:41cb with SMTP id 5b1f17b1804b1-454ec1342c8mr29682005e9.15.1752240901817; Fri, 11 Jul 2025 06:35:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/36] target/arm: Enable feature ARM_FEATURE_EL2 if EL2 is supported Date: Fri, 11 Jul 2025 14:34:22 +0100 Message-ID: <20250711133429.1423030-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241099311116600 Content-Type: text/plain; charset="utf-8" From: Haibo Xu KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2. In case the host does support NV, expose the feature. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson Message-id: 20250707164129.1167837-4-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9fdf354f3bc..66723448554 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -251,6 +251,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) */ int fdarray[3]; bool sve_supported; + bool el2_supported; bool pmu_supported =3D false; uint64_t features =3D 0; int err; @@ -270,6 +271,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; } =20 + /* + * Ask for EL2 if supported. + */ + el2_supported =3D kvm_arm_el2_supported(); + if (el2_supported) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; + } + /* * Ask for Pointer Authentication if supported, so that we get * the unsanitized field values for AA64ISAR1_EL1. @@ -423,6 +432,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) features |=3D 1ULL << ARM_FEATURE_AARCH64; features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; =20 + if (el2_supported) { + features |=3D 1ULL << ARM_FEATURE_EL2; + } + ahcf->features =3D features; =20 return true; @@ -1888,6 +1901,9 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); } + if (cpu->has_el2 && kvm_arm_el2_supported()) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; + } =20 /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cpu); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241100; cv=none; d=zohomail.com; s=zohoarc; b=DF+DtSUZEAtwm0n9vavUsIClEAdnU97zjgZWeYSaj8LmqttJx7OA5+EyKeWykN3ZfWB/78i0jdcvsxPk1jtoV4gu0DlyXe7sRE0d5YNvllkEqo+xOQbobTFD/Foq4HcOMt6PY/8B8sj6h6x30TYPXTSE0OFHWTth+SQNz+b4xww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241100; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hksHQb99/pB3ZFE24pZ19Vblf7IkY7OyO3TtExD2Tgs=; b=SeVZEu5cl3br+ZY4fIF1ejrhpCA05VKpfHJjTl7Keoi6keOPMXcyr7HX5lUfLIrYF57PuF4skppp6iJTqb2Fn5Onm57KgGVwUMdUqrhcBoLYSJ36Ff95QSfXj4FhdoRQlcE83kxG2ur1XUM4SJ9izc/PbJiSzG80iYpVSJ+y8Ww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241100251558.1995001809929; Fri, 11 Jul 2025 06:38:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDvB-0007bW-Cl; Fri, 11 Jul 2025 09:36:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu6-0004XF-AH for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:07 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu4-0003KE-G7 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:05 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-454aaade1fbso21794295e9.3 for ; Fri, 11 Jul 2025 06:35:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240903; x=1752845703; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hksHQb99/pB3ZFE24pZ19Vblf7IkY7OyO3TtExD2Tgs=; b=Ttqn/ykLeyKHn6WsmiKbiD1koNMqqs6rX13DcbGwmFujhR2kbUrXTU5Yfyq78p4tAP 8zi5eWilXDTmAuYa12oXNcg4b54iwpMlcG4u5PNcsAsbtZxVlORgP/J5CNMm6Wm/SNJW YewtIsnLHgtpopNhzfYaLW066Pu9u9N/wxeENZ4Hksc2Jz7RPAMzH441KyzrVGJX2x+r ucOe6RYjZKmPPQ1tU0Gnb8huKd+QHaEa8ZYHgWU6m+j2G4gdVhstq7WsWkmHd8gVokAE czEQHFzCeoVqnk//EnvlRpiklNSWHH9/C/RcYAP2yRpnLburUvSeU37xIu1Nv6LQYtN4 aAQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240903; x=1752845703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hksHQb99/pB3ZFE24pZ19Vblf7IkY7OyO3TtExD2Tgs=; b=Px9FxdGEJLGhTu82TU4OBFm6f5DeliGxWBz9Jqmqy110aJY5C/t/5krA8tzNQbOOSz HDhEowg7OWDNLW48BXKjLnpcBB7WVGCMJcWcYm5rBDLG1xALYXrzPj3qLgCSzHGtgHKM Gn7OECPjCcbI5w+tbfZvmVKQKZlMxLj5s+Kti8HZBHP0xkWOrDV5aM1bw2vi7wDqrv3k u+lqMGSHAhyZupA+z1+bDRLuGMzkkRqu08lHCZvfofsO/erTh5qjlO0pK33ua2p9EXtp cRrAWbyD6OHge8wnh+ks8TLospjgqjAggiqhVJICrFsuj5Hs8+RZegetrigScMBl4hWt RP2w== X-Gm-Message-State: AOJu0YzotgVPhaz6hqtnxYpfR03eq8DvZB1YEK8roTD/AxgqOa9L8hwc HYXsQZW+Oiz6lpBmP2U/3H/+zLeCmv09TWWXfIP5DOoGHmPjf7nUZ5X624n6IHodq1raSX1iaLY zO6Q6 X-Gm-Gg: ASbGncuc3Vl1CsXiuWSvlattAJ2XMMWxyZWEI0fRAnhbU84n/rjqdp0SR//WexN3bpl NGXVv59P6XH3Q//d0D1cgxd1COaGSZSllO27m6nEpNSjGNjlf9zhvbeWZodjNARu8INHRV1mlV/ VxjmeGvP1m3IkqttKWhyeM3keJ1/2ZwjzW9+QKq+2RE9e9sRxoAr7k2XpDjoEpM2qQnXWd4KLUz ZbdfNHfTyTWUONzzjv4B3oJRKXg5FcXEWwG/xg2GRHlpgYh5O60FCz+OvikwmVCiqN+oQEBDaIo bKE/3f9ptb2MNCLjph17nKgPWX6lCgbnhEfPeCSwVjORtk5+PGzjjd5cpDOHZapgDDV820ZWd84 mQZAcXFbtp0oTY1zvSGfZyjNjRv+y X-Google-Smtp-Source: AGHT+IHmlOtG5Kw1ES7lLzQnuaXpmSsm5MQ7i15J/xVHEAJI4Eb1P13Yc+6YBr72oDW/nv5sqW5Z9w== X-Received: by 2002:a05:600c:3d8b:b0:450:cf00:20f5 with SMTP id 5b1f17b1804b1-454ec164bc7mr33558155e9.9.1752240902814; Fri, 11 Jul 2025 06:35:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt Date: Fri, 11 Jul 2025 14:34:23 +0100 Message-ID: <20250711133429.1423030-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241101313116600 Content-Type: text/plain; charset="utf-8" From: Eric Auger We may be miss some NV related GIC register save/restore. Until we complete the study, let's add a migration blocker when the maintenance IRQ is set. Signed-off-by: Eric Auger Message-id: 20250707164129.1167837-5-eric.auger@redhat.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index b30aac7aee1..8ed88e74299 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -827,8 +827,16 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) } =20 if (s->maint_irq) { + Error *kvm_nv_migration_blocker =3D NULL; int ret; =20 + error_setg(&kvm_nv_migration_blocker, + "Live migration disabled because KVM nested virt is ena= bled"); + if (migrate_add_blocker(&kvm_nv_migration_blocker, errp)) { + error_free(kvm_nv_migration_blocker); + return; + } + ret =3D kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); if (!ret) { --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241242; cv=none; d=zohomail.com; s=zohoarc; b=kS2ySP9xqAtPInUAH9s3PPQzsp1Q9ATGlAzVvgHWAQOBm9JqzAiJSFZ2Ra5MfSGfsJuAhXDDhE7b2Hfxm5h5dQAZnP3GLiybhDlN75zr5l+v3hdQTBXnVNDzV6y7GrEQkD2nBGg6+Sw2z0GSCYHmgrd/PJFlWb57mAeJ5aU4FOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241242; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3KkAwbN1hZEC2FoNhPdG0KBNKiVsXfiwU6S1weZwVek=; b=hM3CnHBwRz8uvCnaNt+aTjdK8VuFY9Zs5oZqVwirlx+yNnkBKwQG0X4dDqj47QM4Kqan3wl9PgzItEPBd1UOgIZj+8x+X5Id0kD2nG+wRs2XZImlvgIQRYhg5dG1AHDu8fu4Ly/aoU3yz6QRMl5dOuMwZZFCF/+cA+hisQpwaYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175224124215475.83380590298384; Fri, 11 Jul 2025 06:40:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuy-0006eA-9L; Fri, 11 Jul 2025 09:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu7-0004Xq-KH for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:11 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu5-0003Nf-OG for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:07 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-454f428038eso6894685e9.2 for ; Fri, 11 Jul 2025 06:35:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240904; x=1752845704; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3KkAwbN1hZEC2FoNhPdG0KBNKiVsXfiwU6S1weZwVek=; b=YOlY1Syfewh5mmGUwk/O8puHGAC1KMzX/PUNkLXSZaZcfXX1MaGeUVqYK0kIWEniIM FDiM2dDbJi9CNZ36k30QwwjNII7KdmjlamERIEWGpWoFK2b2nwy82lwo1zIq9NkZyARb dZJUl+o7q9P/8zkUVXrlnp4GHMQSJODowyBQZjvHMMtlmftQD2s5nmqQwm4Thn1hBGDm iHn+n93zXV2WhrVOLtdIWgT/ZHm79eZxo+wY7vr7W4hiUiqgtRk2l50OSSxx5rP4JRqT 3byukVjIA4aWSterbQKUCAe5vxnSlTsJGsR44HJ+6NykGAtjLwxaiLjQvLTx6gyf9pQR sI3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240904; x=1752845704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3KkAwbN1hZEC2FoNhPdG0KBNKiVsXfiwU6S1weZwVek=; b=JEnFVST41F3Ih1X6sW4Z/FIYZk28jNfS2zdiiGoN1LcsrtkiP1Nz+I1LbUPvcN4LNe cy4VR1F9NQo3ckV2QyVs0CXGidKKJyZ4te6S9ndJl4fGwK8ML9AxP81I7ujaOe5be6oK AKKlcjVD7u/K3uXFMDt8PhfyN6iB/vukZ0/sQbHAoa45xPuNvDOd2J4I1qRp2BdWKF0q GAnRrfdeVEvPTqihcp2Mb1ci1tyN8pSZT1PC/iWkGiU8fdTivgJ3qUqim9LuxEdUJfBT 1QPXYz9gVIrJtJdc2uxi39j7XPbrb+RBPxsdQpFGtQK+bH/hV8bCEgMySYBT++IQvVMl /c/g== X-Gm-Message-State: AOJu0YzbPGVqd8X+i9oXb/r1xsmjZvQT2XEeVaD9YTIctMjolZoDVC0j 7GRrOPmTcWil6BLWWnINq4rNT+i5F0CZqhJOPTZmkhcwSNiO2aGZtvYg+krtCU5DnckqVNnEnff R8SZx X-Gm-Gg: ASbGncs8h74jTsWlQAsylWoF+euS7ERToMKkxrOpG1E+Skt+gwwpdKh4k+kpJXKntRt LCeVsozwdZggSSXT4DdvpHy873RzV+lvR2b2PE7RBRNec8vIG4t0cF45baR5lCX6GjMoPp8Xaoq SlIVSAu4akhyl813UPBmv1hBIHiuDlcNpC7rJZv4wFNaEASqhcsFU8ngNdjmzUtO4iLXahKuX51 wefpvMNO9h40J/HAkZ5tP7kE5XdphaFKg0lzPav7dpjnBGibgC4VCEdV4D9CC/RcpWWE29KJxii BiVfcxRTZAy+Q02qGFIm2kcivNAMSXaFbHVmjT9c9q66lIuM5ylvpPzoD2QwPeA/U1f1qzYZux2 oF/WvmtzIjtPEm0LqvTT/KPP1tdbE X-Google-Smtp-Source: AGHT+IE6H5Gc5o93MnQyjSKh7N465kjYDs/s29fC67QCd+EbdvgQnCIccLkbYv1Ns+gFg3fu2ppmLA== X-Received: by 2002:a05:600c:1d14:b0:454:afb1:3bcb with SMTP id 5b1f17b1804b1-455f7ed2d73mr4248325e9.25.1752240903743; Fri, 11 Jul 2025 06:35:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/36] hw/arm/virt: Allow virt extensions with KVM Date: Fri, 11 Jul 2025 14:34:24 +0100 Message-ID: <20250711133429.1423030-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241243296116600 Content-Type: text/plain; charset="utf-8" Up to now virt support on guest has been only supported with TCG. Now it becomes feasible to use it with KVM acceleration. Check neither in-kernel GICv3 nor aarch64=3Doff is used along with KVM EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson Message-id: 20250707164129.1167837-6-eric.auger@redhat.com [PMM: make "kernel doesn't have EL2 support" error message distinct from the old "QEMU doesn't have KVM EL2 support" one] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c9f39919370..8070ff7b113 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -797,6 +797,13 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) default: g_assert_not_reached(); } + + if (kvm_enabled() && vms->virt && + (revision !=3D 3 || !kvm_irqchip_in_kernel())) { + error_report("KVM EL2 is only supported with in-kernel GICv3"); + exit(1); + } + vms->gic =3D qdev_new(gictype); qdev_prop_set_uint32(vms->gic, "revision", revision); qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); @@ -2092,6 +2099,10 @@ static void virt_post_cpus_gic_realized(VirtMachineS= tate *vms, memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NU= LL); memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); } + if (!aarch64 && vms->virt) { + error_report("KVM does not support EL2 on an AArch32 vCPU"); + exit(1); + } =20 CPU_FOREACH(cpu) { if (pmu) { @@ -2237,7 +2248,13 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && !tcg_enabled() && !qtest_enabled()) { + if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) { + error_report("mach-virt: host kernel KVM does not support providin= g " + "Virtualization extensions to the guest CPU"); + exit(1); + } + + if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled())= { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240971; cv=none; d=zohomail.com; s=zohoarc; b=HXiYISobHlE8cVjvru1UmTXtBETFuHKn6O6d01IcgZ5vL5uZFnPu1rnxmAkDFviqBdu0BmtrxQxGuQ0iLpCNGFyQU7IFfRAINOVlmBelSBjMv1hprhLeWiqAum6rjkc7Fbzh7AEgUc8O0bBH0ZXF7LF8Hm9cKViUFu1nSoC0ZDI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240971; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZrgtnfXgpymE8G7muX/kBHKLDatZv3Oqto0HtHHZgd4=; b=Xofo9MsNkRKLU8oUnKHWDhOLwzJmdYdKMkZ9AZGMD1ybY0sE+merEO1P3eQ/dlHn6nEypalw5fHJ4rmsHMb6jDrigFlgnVIrKuwRFJcFGYOplgwguGSvhEyywidvuzFLCCBzYsNRjgDB6fnJyZssuKfYFfftZyXGyVC6wDXtJ/o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240971813891.6701720807533; Fri, 11 Jul 2025 06:36:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDut-0006QL-Vu; Fri, 11 Jul 2025 09:35:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDu9-0004Y3-0Z for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:12 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu6-0003OU-W8 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:08 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4538a2fc7ffso22735595e9.0 for ; Fri, 11 Jul 2025 06:35:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240905; x=1752845705; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZrgtnfXgpymE8G7muX/kBHKLDatZv3Oqto0HtHHZgd4=; b=ifUDadW0amhQY3PyvcTbzEfxyxi19iH/7pAvhPpKbOR3Z5x33BmchSxF5naMM+Eg7k cSd1OuSro7olX47vulzkn48q0HWANgP+3y1M9ILfEnEabGfOzZ+Dx9T7mBhmT3maW4F8 h2b2NYl6xEerB8NbtdHE2jpN7Rn4/wlRBQQ+RTIf8Gf0oWWZvRZ/XKb1Dof6LvddrWyO G5VoOXAEJzWLOIZBPQrCoa3MgRVu3hls45Ecz2+/RfNFMQ9py5pZxNf5OC3qSY+5DhiB +W4Vsev/uQz8IjRGIDcVxrZqR7ZEwc27WpSWX4YS84oPci9q6443OlqScvWPNW1HTCD3 Q7bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240905; x=1752845705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZrgtnfXgpymE8G7muX/kBHKLDatZv3Oqto0HtHHZgd4=; b=Cq67ktxMifxPTq85lDjchzuUwbhP3egBeYUnOL3QfT4HTuH1I2xO2Z9ZCn3Tt+0tP8 FhuDiIbsJ+Nz8zcRNnK6KD0YRedfKQb9pdQev0Drnc3KHvOkQF1Iq5Q8HQXQHfPYUjW0 flIaXjXSZO3SeoC0TpXgf3GIFl5Jg9FUop5yhQayWgxtvSyX3cBrlNJSrzV0ACHEhTdG yUKyMY3o+Iy9wdrIfzMeUVdfpVsc9V+DrM9A7QpeN+dKzD/oE0pWOlrIXzZlxhi0iWJM 3QXeGANEQMkFM/ODrdYoW+SUBbAkDp4tW5cXnd3246VQjGb4bZN03qb1AjU4Svp4TjMn vdLQ== X-Gm-Message-State: AOJu0YyuTiek5n6onFwc/n9INoQjY4co6YXkfCf7Ga0Wvw+QzKXS48ZX 0unTongUqeIDsI4yLGPIBcFglS+8EHkFk8fST56EGKFuvz7wt0n//sdyjgUWpnupD2/uGtQ+DFL lhIml X-Gm-Gg: ASbGncvjMLRmPBPVCIlu8WHCgzWVjIgg1uUloGQ4pSYAiWK5yB4hR/rExKJldLKUlUl idU4zDwuwpLhQg1f+jQvn8fELPmUzPYmVBB3xp9J/qPkdefgEbuGJrnUszs3z4sx7G5wrhvl6ut 8VDnFBRnYfZQmbVD13XtpWg5g8fVbuTJSpITFePX3b/IldNuB7qDA8pQ4byYPhHdONbHHu3KZsu GJ4MXrpn5kr0KzrqwxiSXFTwhxWh+ez0GPTyogu7t2lnSOF4/UMIot5wWzwSz+LZzerRDQA6Sf5 qZH673RadtGKnXZpOLy338d6+IaRo3Vk0YPCRHF03SJhWqd8acPyNM3roKhdBF0rQ3JWP+UAk5K Yu5kUJF6p06NmQOY9JH3Tv0STJS6U X-Google-Smtp-Source: AGHT+IGroGCGlc5enOx05alGi4vzxRhX9nd9whTwu3rLYuXeWfMvQfj5m0vhYM7MqPehenLrDR1y6Q== X-Received: by 2002:a05:600c:a418:b0:43d:174:2668 with SMTP id 5b1f17b1804b1-454db7b297bmr56648445e9.0.1752240904733; Fri, 11 Jul 2025 06:35:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/36] system/qdev: Remove pointless NULL check in qdev_device_add_from_qdict Date: Fri, 11 Jul 2025 14:34:25 +0100 Message-ID: <20250711133429.1423030-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240973732116600 From: Philippe Mathieu-Daud=C3=A9 Coverity reported a unnecessary NULL check: qemu/system/qdev-monitor.c: 720 in qdev_device_add_from_qdict() 683 /* create device */ 684 dev =3D qdev_new(driver); ... 719 err_del_dev: >>> CID 1590192: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "dev" suggests that it may be null, but it has alre= ady been dereferenced on all paths leading to the check. 720 if (dev) { 721 object_unparent(OBJECT(dev)); 722 object_unref(OBJECT(dev)); 723 } 724 return NULL; 725 } Indeed, unlike qdev_try_new() which can return NULL, qdev_new() always returns a heap pointer (or aborts). Remove the unnecessary assignment and check. Fixes: f3a85056569 ("qdev/qbus: add hidden device support") Resolves: Coverity CID 1590192 (Null pointer dereferences) Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- system/qdev-monitor.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index 5588ed2047d..2ac92d0a076 100644 --- a/system/qdev-monitor.c +++ b/system/qdev-monitor.c @@ -628,7 +628,7 @@ DeviceState *qdev_device_add_from_qdict(const QDict *op= ts, DeviceClass *dc; const char *driver, *path; char *id; - DeviceState *dev =3D NULL; + DeviceState *dev; BusState *bus =3D NULL; QDict *properties; =20 @@ -717,10 +717,9 @@ DeviceState *qdev_device_add_from_qdict(const QDict *o= pts, return dev; =20 err_del_dev: - if (dev) { - object_unparent(OBJECT(dev)); - object_unref(OBJECT(dev)); - } + object_unparent(OBJECT(dev)); + object_unref(OBJECT(dev)); + return NULL; } =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241213; cv=none; d=zohomail.com; s=zohoarc; b=lRtaCB2IFoCNauZGNt50FwYGkyflJ7m+Getkql9c0UMVuqkS6d9gH28hTyLIm0o+LSAFewAPKhClAnymTkzqpyg/UP64JmcWEH/yVQdVWBXCiiaBkdbj70z0EcdJYmMGqvpgEtxeUjyXkNr66tmHOUqlQ3SfUaT0eUBI6fKAuVE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241213; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=rt9y+/Q3kbLfenOke8pPv0fzPqohcdD2CUbik7idoc0=; b=KiLwl7qVRExEqwqXUw5eg2GaMPSFOfJzDArY12NYiHbWLCwdjJLby9Ft9BqISGFpQKG0NvvA0ziE0yYCryzLreG9BkqfQEtSNLzVnw/4HOOa2s5GTZkcxDZGEH9WLGVOfUjQwM6iWkX1nISZzQaeAkFWw9igniXp0hxWFafxJcc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241213089430.0929978372641; Fri, 11 Jul 2025 06:40:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDuy-0006gz-MU; Fri, 11 Jul 2025 09:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDuA-0004YB-Cj for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:12 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu7-0003PO-Cu for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:10 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4555f89b236so6495285e9.1 for ; Fri, 11 Jul 2025 06:35:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240906; x=1752845706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rt9y+/Q3kbLfenOke8pPv0fzPqohcdD2CUbik7idoc0=; b=kgZ2YKtZBprQR4OyaTQv1ymLgXxFzYe25ThgNJ4EFCh4A24na/SyyCiAUedxyLcfIU BLDM+jfAxS3RIKGy44s6G8OGthu9/NQv5X7fxzBoALxNAZ5jQCLy4HHzArBGQjAhqaGw ltep/kHyhXT8TcLcgdUSOfjBCAkonXAHJTg3rNOnvVET2isRNUr7LE8YgkXf1/0OK3H+ OBVApXd69BA4mYzCFQsjurXlWyM56Gt92Wa6p5pvDLefjZFE37XfDWbZBF0VC1WMflHx 3qW0eKDhFqEhX9wPzE0cSYjGxhcWZLRN1TvnSVK2KHrlxSz79m+ADSyeVsbUflM6JzRR GMqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240906; x=1752845706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rt9y+/Q3kbLfenOke8pPv0fzPqohcdD2CUbik7idoc0=; b=ULLT99CQRnFrseHGTlCMxrPZp+cNnj1+E91euRj2hsvKLt+/SMoOGDckJhDpL+J95T mpixQ078WhTeUlNPrB1fY3/06Lbm7A9SC71HB9+W8egcweU6CHEwqU4qCWNOTBp/iLfs PhVsqTuQIyYG94dCPCZ1l1Z+813SKzziYClQfeutEWKkveOa3shSA5d03h0VPl+w5DBS D15m687sNIWgs3dyuEN+YCFa7iSC9qZEBf19q85d+7pN+ES2Nz3FUuTvAvEr5GgDpHbw ti3mpdEyiQ3LiQrEqg1hvALGm2TM89bLRQnHkBeDofNc7ZAchKsVIm6rL6gnGGNNSATl YMnA== X-Gm-Message-State: AOJu0YySFznZS6RAcXjIEkOtSXA2CK5cTAm+DgB+aME/Mx3Q5c98cZGI 6lQz73TvBPnYAjJKoHNKCaefX6WcQdp8LC7NPDSD8Ib5VxYMi5q1jIiXO+2jG5UapgpYqsRWssS +fnxN X-Gm-Gg: ASbGncv99khjugq8Imt/q7VF1X9AsyvwzIkJgQIVRUCcKfJakqmoCFHCo44F5T4v8KV X+QqHmDKP4aeUy/3kK3fIGusvvPWNBrRwBdbssH+t1g9FJqkpgdEDlzYB/2fjeyoRwdkYNVHr+k Ku54yOeGft2bmvbX8w6/7n4vnbgOJQ7W4hahy18bAWbwNS/nEpZuS7JfKiLTC7mx1VZxK2I1J9A kxHvHrxvdVjYxEm6mSOOPL6TMs8HOW31aWpIIzrV2TCBtw0DYvPlNjJUKWCBrLoO3KJHGhLDSoF nVAiG7WkswIeg5LEmf9y/MDhf2QjpHuGPak7ZyLH7vMn6E7Agz14Axhs0hk8Z4ooY0C1lBdbkNo UyzwMug1ovP+LQ6VVEpjas7LE4Pe9HTjnrSD+x7g= X-Google-Smtp-Source: AGHT+IHCB//tHl9uAR1WVTQAjs3fDJrj+1/k6lV2nQkDwoFQxDNzEqrgDWqFN8s6mWaAZX0jDaTCzg== X-Received: by 2002:a05:600c:3595:b0:442:f8e7:25ef with SMTP id 5b1f17b1804b1-454ec15e5c5mr30323905e9.11.1752240905739; Fri, 11 Jul 2025 06:35:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/36] hw/arm/virt-acpi-build: Don't create ITS id mappings by default Date: Fri, 11 Jul 2025 14:34:26 +0100 Message-ID: <20250711133429.1423030-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241214859116600 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum Commit d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables when its=3Doff") moved ITS group node generation under the its=3Don conditi= on. However, it still creates rc_its_idmaps unconditionally, which results in duplicate ID mappings in the IORT table. Fixes:d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables = when its=3Doff") Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Donald Dutile Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index c3b9b3f6ea4..0dfb8ec2c35 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -358,12 +358,6 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) /* Sort the smmu idmap by input_base */ g_array_sort(rc_smmu_idmaps, iort_idmap_compare); =20 - /* - * Knowing the ID ranges from the RC to the SMMU, it's possible to - * determine the ID ranges from RC that are directed to the ITS. - */ - create_rc_its_idmaps(rc_its_idmaps, rc_smmu_idmaps); - nb_nodes =3D 2; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps->len; =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241258; cv=none; d=zohomail.com; s=zohoarc; b=Gp+TA1GYiLKmzv+aKBZpwccw1ee6tgh/rsZLso2qRzVmKzFIjFZJW5K6iz1OSFBOZLRwDhCLXM90f1EzTM3iFm7sjxY3rNQhqNt368G5bMDEWx7tYmgmv6oVXwAZp1FJQ2Sy5mGjqAbg9FzzXGe6M6JtmNkJvcga/F5NHFD3aZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241258; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=T5QPHrTCpGb5IuxfuJs5tmL6/p8OyGGH647SOYA+1k8=; b=lnBJagf/YPQFgB6WklIpHiQ+uCwu7yB+3VUoRzPckbObFvrk6syYqqke31bUtXABOF3ao6a0t4MrrqLlbvoOtRemTsg5ZNFCzoGzEqrD3u/JzBwCAaghUcHw68hFMRvraCXdWCeEmU00hQG88Kbr6Su5sQuOUzBIKb3I2a0DulA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241258690829.0756360917882; Fri, 11 Jul 2025 06:40:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDvC-0007fW-WE; Fri, 11 Jul 2025 09:36:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDuA-0004YL-I2 for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:12 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu8-0003QE-Oc for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:10 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-454df871875so6294185e9.0 for ; Fri, 11 Jul 2025 06:35:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240907; x=1752845707; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=T5QPHrTCpGb5IuxfuJs5tmL6/p8OyGGH647SOYA+1k8=; b=RP/V8aOBoiUmVHPPdfTZxB0vWkEYuOJs+NLZhGzR6GHc9UHxIhrLtybbGnI5uZ9uBW hncPoQAHYct3Uv/oQKnngznNzTnRzOS83cWYveT9Nr3O0WaPJ7LQ0XdWn/bmEWk8uKrn sTHE+vcWnFHvP33BvgpfyBOg4MYSqTPwIUJK9E5qiZQGJpZuURNbuK1AqJCKYBCq4as4 JlZriW/y8uToflwoR06MboUjojhE3/psCoy1PWBWIkQ+2SyvxrAnwqTrP0cnNNoH2Eys hKqWFBQ9qmPeUcglb2hpuW4u278xLe4ge+Z7+t8apBuJ/XLNyJNY3dBNT1ALh4soQA1y yMMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240907; x=1752845707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T5QPHrTCpGb5IuxfuJs5tmL6/p8OyGGH647SOYA+1k8=; b=LxJdKV+nHKbkXiA5G63HZGAn3cYhUsfN/4N9OcJ2XuinhUMs3ek8w9whhTwsGv3d09 NmMOv2wgtvWBEdbyW3PzyZn/EsKg2WMnx5LeErxCS/AGAFohep8dNuyzGsamvn+acTaZ 7xGBligM+xyTvjCb3ccgeEu7RkHzVVI39fYRhF87GE5wbIGr9ltaJXKzLvHEOrC4zdYV SIAoJGfNAksrbTuDKQVFY8037FaGJzut7A5nXp3KR5ueQFRV1FmFX6iDpnry+RvN4OsN sTuJOYEVnSFhaKX9YWIP3BP95V2jG4GlRyT/GusB+24mppYBFTEoqJLbZlPRbEYnSZUQ VN9Q== X-Gm-Message-State: AOJu0YzswKaHfBGqXozR/vU5d+67qKXEZS7BNVVKwsPhrj7O/OxvsIz2 APm+45nRDF4P1NXcncgFXxkGmpW5lAr9CCeoEiK2Di7uxSHFyH14HK1HSH26Qxg6F92/54CAwne kOFu5 X-Gm-Gg: ASbGncv18JyjpChG+3LuuqDSYCj4YngzNrAJ/+7VpNpHsAIv/BKlme2fEQNLAh+IvYh kdE710vXnfdSm//dwsQJ1XNFIkTjkaV1It3+8iSVHNYkRpbWwv2Go20naKEO5Gp73cbdIpCjGCi wHeC9SDhVGBtdxO5pwbTCcsOBaxhhacxr7IzculICjFJ/sRuvEvBs4nR3tFgVFXrST5TSUJuqqG j7O8b/kPXHS04eMInYdRVvD5s8gnB3AE756vIqyAf3epfn2O1nCezghRYvf5tJ+MNNzoOHbbvpz G8bnKRcapaVzP4pc4e3KXcRw4ySLueMBqbXWs502o3s1IAB/xr8j9Dtf81CKywNa200LVN6dCwy /p8QpqbQ/hSy8SNhc1YTJ7JC2KWGl X-Google-Smtp-Source: AGHT+IEDK6hGHlOjgHNHFgmZCBaXzNAul7c7LikdfmtAskEIzXSUw0XAd8m36clxTklU0z6z+XhOpg== X-Received: by 2002:a05:600c:c116:b0:453:6424:48a2 with SMTP id 5b1f17b1804b1-45576a7e0f5mr26438545e9.10.1752240906771; Fri, 11 Jul 2025 06:35:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/36] target/arm: Remove helper_sme2_luti4_4b Date: Fri, 11 Jul 2025 14:34:27 +0100 Message-ID: <20250711133429.1423030-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241259438116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This function isn't used. Resolves: Coverity CID 1612139 Signed-off-by: Richard Henderson Message-id: 20250710173945.115428-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/helper.h | 1 - target/arm/tcg/vec_helper.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h index d9565c80697..0a006d95142 100644 --- a/target/arm/tcg/helper.h +++ b/target/arm/tcg/helper.h @@ -1209,6 +1209,5 @@ DEF_HELPER_FLAGS_4(sme2_luti4_2b, TCG_CALL_NO_RWG, vo= id, ptr, ptr, env, i32) DEF_HELPER_FLAGS_4(sme2_luti4_2h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) DEF_HELPER_FLAGS_4(sme2_luti4_2s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) =20 -DEF_HELPER_FLAGS_4(sme2_luti4_4b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) DEF_HELPER_FLAGS_4(sme2_luti4_4h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) DEF_HELPER_FLAGS_4(sme2_luti4_4s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i3= 2) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 0603db09093..bae6165b505 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -3526,7 +3526,6 @@ DO_SME2_LUT(4,1,s, 4) DO_SME2_LUT(4,2,b, 1) DO_SME2_LUT(4,2,h, 2) DO_SME2_LUT(4,2,s, 4) -DO_SME2_LUT(4,4,b, 1) DO_SME2_LUT(4,4,h, 2) DO_SME2_LUT(4,4,s, 4) =20 --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752241230; cv=none; d=zohomail.com; s=zohoarc; b=lwKVuFndNsvP2Ph8V2YzF2IsoVpz5Aw5msGIxRCKLn5YApkGXL88i9HaOqHt2QB65GFBHPAL6DsgRdR63Q/Igt+jfVlIrB9B61Mc0/yjJQYCTxOmYbrc9NOYSalnxSpQmZc1umUQFzCieAwRPjSDwZ5GuOGB+hUmBHtG6nz6q1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752241230; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=lS2nIjGxU16dkA6C/AG8JGKbnfQy87F/qy82QXJuWeI=; b=B/ix0NXd8Gx9Ka7pAEDv6MQ5elAUHP2MEIVx/W0x4GmqGkCI3GjTPy4zeJLHXf8Rxbr4GxOU95xPV2TCbe3byHDeFOgYgwZi/7ZRDZsnL7IJ8Gz1JxJtSuKAe2cnuCbcug980GQpM32A5uF41qhZ9b5C4MWG/vI2+NonMHC8Fu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752241230354206.8932557403008; Fri, 11 Jul 2025 06:40:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDv3-0006vQ-KW; Fri, 11 Jul 2025 09:36:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDuD-0004av-AR for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:15 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDu9-0003R0-9z for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:12 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-45526dec171so7656395e9.2 for ; Fri, 11 Jul 2025 06:35:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240908; x=1752845708; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lS2nIjGxU16dkA6C/AG8JGKbnfQy87F/qy82QXJuWeI=; b=RmS2mjg4XXtQp/wkepSh4OVXi1ia2ZrJ8cqLLbPjIsyax0gfOaJc0OMB8R+LbFWfha kiEEuy0MOHfsishew2VueGTrgak3hg9QLv1euTvflMrjtaT3ArQROt+GUw+IJQ4+R4Om VptVZ0iosYe/f1waTDHcUlSsq0UO+JKrpSZPrnU0+3/hIhOj/EPlJl/FCDzR4zQTIpzf ypAr+loXP3O7AtgEN7QR0AJvGukng1avnAT0a96RMavMI42n5ncfynin8R7hiwcOur9n JgowhXb3unXYyA3JyTA37f55mpZcrUi3G0KijdP97rY6HeJPk6Z1Kxx760ERBoTe5Kh0 Ommw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240908; x=1752845708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lS2nIjGxU16dkA6C/AG8JGKbnfQy87F/qy82QXJuWeI=; b=lcxane7ZbNuO1G4N1pO5LhTDeUQ049DROrnLVttRp2/0z/1tks/VIo+0vqvViQv/kk wAQtA+rBYmdeoNHdoxzT+QxH7HwMDFCtaMzJwAt9o7mH3yGtuKqk5LHK8qXs6G9Girw2 SP8RFqHztWXti7depL1KG6F+oInXDF+BiJAzmDsatGYZ3So0jQQPRylVf1FdEBw82ps9 tMqyCeQuA4n/ZKCa7TzffoA9F21ZA1rd0d+7zIZb1QASy+48I86b09JyA5IApY64CLoB K1liOTpGF+6EN989+jq+S+CFhDE8MhRI6sFBJ3DRufcrbtkfqkqrOLmDNuh/nj/ef0UJ VXzA== X-Gm-Message-State: AOJu0Yy/nHdEN6NJwWBSooFQvo8Hwp28ZHkBxIO20s7awJDhMhnIYA14 WU0p6PeLkkpw+OcbYdYrG2oEgUcvotxPq3ZzzVrmch0MSHtF7g7yYEdh06ZjX9Hbq1/ipiqxyMw punyo X-Gm-Gg: ASbGncslOTXygRPrj+aJgotEMVKbbS2ezG9MgvlFHZKFUfpCe++EBF7PhmQgTdJUAHB 32jY97rq9L9Se5VuUiSLxB9QZeMAKtJ++mXPwxS0f6Q7F6aPOW5tC1L4ixdhC0ChexmQEYHbNtb FTklgZBiBfihSRJpyeR2HZ2jHi5FPQvXAUukdJuUq3ZFAoK7rhYvo99qp7ofaJDObTUzSGsUuj4 qfNiEBLD3+PNdY5hj8HOeoHxMfwkoZYkOKg/5ZI+mfJd7Hy5nFg3Pqf8+jA3lyymHK371IBoKIj VLMTtqmNXo7DUGPoI7qswkXDf8TVXEiMYtLAId8BTNeftlBsAZZHGA5Cf6y58FaBmhylhs/3yBm kEWtPBgI/IMyt7XAoFz6A+umTWlOk X-Google-Smtp-Source: AGHT+IG/AM6vOPTpmiMfZdzF53IbDJg5Dxxnzn8+C7pOxrv2IP4rI4ElJBf/TtspcI6XFxkYJ4bmJQ== X-Received: by 2002:a05:600c:8b2a:b0:453:7b2b:ed2e with SMTP id 5b1f17b1804b1-454ec2727dcmr28392355e9.24.1752240907667; Fri, 11 Jul 2025 06:35:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/36] docs/system: arm: Add max78000 board description Date: Fri, 11 Jul 2025 14:34:28 +0100 Message-ID: <20250711133429.1423030-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752241231300116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson This adds the target guide for the max78000FTHR Signed-off-by: Jackson Donaldson Message-id: 20250711110626.624534-2-jcksn@duck.com [PMM: Moved doc to correct place in index; made underlines correct length; added missing trailing newline; added SPDX] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/max78000.rst | 37 ++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 38 insertions(+) create mode 100644 docs/system/arm/max78000.rst diff --git a/docs/system/arm/max78000.rst b/docs/system/arm/max78000.rst new file mode 100644 index 00000000000..3d95011fefd --- /dev/null +++ b/docs/system/arm/max78000.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Analog Devices max78000 board (``max78000fthr``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The max78000 is a Cortex-M4 based SOC with a RISC-V coprocessor. The RISC-= V coprocessor is not supported. + +Supported devices +----------------- + + * Instruction Cache Controller + * UART + * Global Control Register + * True Random Number Generator + * AES + +Notable unsupported devices +--------------------------- + + * I2C + * CNN + * CRC + * SPI + +Boot options +------------ + +The max78000 can be started using the ``-kernel`` option to load a +firmware at address 0 as the ROM. As the ROM normally jumps to software lo= aded +from the internal flash at address 0x10000000, loading your program there = is +generally advisable. If you don't have a copy of the ROM, the interrupt +vector table from user firmware will do. +Example: + +.. code-block:: bash + + $ qemu-system-arm -machine max78000fthr -kernel max78000.bin -device loa= der,file=3Dmax78000.bin,addr=3D0x10000000 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index b96a05a9206..a96d1867df1 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -71,6 +71,7 @@ Board-specific documentation .. toctree:: :maxdepth: 1 =20 + arm/max78000 arm/integratorcp arm/mps2 arm/musca --=20 2.43.0 From nobody Thu Dec 18 04:15:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752240987; cv=none; d=zohomail.com; s=zohoarc; b=oCEpsEOslYcTv8EyY1/stbNZYiviZJDQTuIX37IYRnJYbtx5/BM6s5sWP1Odx/8nSG8MLWprEg96/fGWqnaMJOxBKMOE5JALSPAQr2GOMIDJf6BQ2fUnsmIKF1lHYKEdOZASlyQ8SJqQ2hyboG6PCdmv3OY2KAO5FWaCjmzId5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752240987; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=CVN1z+tWl9V2/IAeWcoVzag1iP6PIT5deFW+qz0vQnE=; b=eOkVTsdakm6KHceKVUA0B0DBhv62QAHTag+rHSFKqhoTuhtfsFxa7zCesuKynznPCctVsbfSjgI0wr+ScEmkgM5OJ0sbaY5z9AVXQKXZtPHkZdVIdc3wLTQIRNG5RKOhoOGbqUGwqTMg/QrUVBo81KRhETQVBtwG5cmTRoAWWxE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752240987275555.50806388949; Fri, 11 Jul 2025 06:36:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaDv2-0006rR-DW; Fri, 11 Jul 2025 09:36:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaDuD-0004ar-AA for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:15 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uaDuA-0003Rj-VK for qemu-devel@nongnu.org; Fri, 11 Jul 2025 09:35:12 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-451e2f0d9c2so18653085e9.1 for ; Fri, 11 Jul 2025 06:35:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df0cdsm89734145e9.25.2025.07.11.06.35.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 06:35:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752240909; x=1752845709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CVN1z+tWl9V2/IAeWcoVzag1iP6PIT5deFW+qz0vQnE=; b=HnyQyU86H1um2vo554ZqQd9/WsiKxr2azRN2sEVX2ftmBFItPe2jdYV8cK/jWkVPvH K00EXj8Cp1l+G+z6sBwtvbeLMuXn9RqGF6Heh8sRVQfxdzRpenr7PjOuQK9Hm/54c7qG XOygdxm1XK0/ZVOxCP8WlqDMo7X1BEHpQjHlRb6XSlPVLbzGxp+7PhkokY2L6v3mjtmG lTLAY3MfSbO/SupjovaoeFOuIWHXVSEC3Nf4EL+zKB9kUttSeADf+PyPJ763sBsV5B2e 6elTxrvoneoKCMMPP/eflwiwh1XdVN2aH/s7oCN4OAfSuTV3otoe92BAhTqzbG/G1Pqk C6UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752240909; x=1752845709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CVN1z+tWl9V2/IAeWcoVzag1iP6PIT5deFW+qz0vQnE=; b=BhkeGOhLHivdFHt3azoDVQWFKK+mMAIz3wSqb/vIP6oHpkAHlmqaviXnUdo0Weutsy InIsP3QxulTXzrN1CoyKYFTQXO+AAACsLSPFJwDrteHL2IO5hBsSNXpPaL+gbdXahKz6 t/Kbc9uqflKD1PV3egIi4Ax6xDa5Jk3w7wWhgy3enor4aVOSHZONJU/ZgelaOv8CoHoR KgXbjduPCHIBe73hUbZM/C30RrjvS2po0rayyZBTIpOEDayF4WnNRNbVwlkoYnQyheiG SNQwGqyy4EfBtU+uQEER+p6vSwPYtf5oyrM5FviGAT7WhuC7e3pDmX3nTa5AwfSYp+hX TYeA== X-Gm-Message-State: AOJu0YxZpPbJO5/5kXdSPtlAc2MfFFGriG/GGw16jyXuFz7+Z3N88Xi5 hupC1eYcYIIGDf9i8P7olJ5ilLNXy3cqfi8O1htYxEUaw63/fdDI19asTAz81YMVBk6Bo6TSRNy 16cvu X-Gm-Gg: ASbGnctOJ0BKbaNxBNZk2+5paqpSH8pq2Qz0DGkEuUOy2IRuud6tYl2y4M8oIp7Bseb LGwQYLY+Z3C1CGFaSbZavLjBgInIqJiRV9U0jUtXWi6L1+RLZmUkw01aIZiQH1vrATe58J1YDBF LdEg/y6oYZ63h5FDCDmVGb7TReumEAHm0ksNHDkDAKeuZOxRuw4eh4gAlYWfExwD0S1Q1WqT+Po B9k2edf1bWz+QzClX7FlYeJv7gSSXujlN+fqzFTle52gxQxf0IK/OUWWA7OWdM6rBlOvTOH61nk 56ElKf1jJEQL5695GmDoGYOJkOpreRxznSCOQzYTf3gJWUDgWJZWjG4qFFK2xREE1B7IpY3FPwO +nsy6dox0bMOkbNYVg7cqS9QeH+UnULW29wbbJuA= X-Google-Smtp-Source: AGHT+IH9HxW9g+Zx/lTj0HcsoMmgK5ccTabBk6Ig2vhD9B+2vgvaPlBIquTLrseS91jpDvhTMcNoMw== X-Received: by 2002:a05:600c:4746:b0:453:7713:476c with SMTP id 5b1f17b1804b1-455bd8e63aemr21980345e9.2.1752240908883; Fri, 11 Jul 2025 06:35:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/36] tests/functional: Add a test for the MAX78000 arm machine Date: Fri, 11 Jul 2025 14:34:29 +0100 Message-ID: <20250711133429.1423030-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250711133429.1423030-1-peter.maydell@linaro.org> References: <20250711133429.1423030-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752240993094116600 Content-Type: text/plain; charset="utf-8" From: Jackson Donaldson Runs a binary from the max78000test repo used in developing the qemu implementation of the max78000 to verify that the machine and implemented devices generally still work. Signed-off-by: Jackson Donaldson Reviewed-by: Thomas Huth Message-id: 20250711110626.624534-3-jcksn@duck.com Signed-off-by: Peter Maydell --- tests/functional/meson.build | 1 + tests/functional/test_arm_max78000fthr.py | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100755 tests/functional/test_arm_max78000fthr.py diff --git a/tests/functional/meson.build b/tests/functional/meson.build index 050c9000b95..cd67e6d734e 100644 --- a/tests/functional/meson.build +++ b/tests/functional/meson.build @@ -138,6 +138,7 @@ tests_arm_system_thorough =3D [ 'arm_cubieboard', 'arm_emcraft_sf2', 'arm_integratorcp', + 'arm_max78000fthr', 'arm_microbit', 'arm_orangepi', 'arm_quanta_gsj', diff --git a/tests/functional/test_arm_max78000fthr.py b/tests/functional/t= est_arm_max78000fthr.py new file mode 100755 index 00000000000..a82980b0f7c --- /dev/null +++ b/tests/functional/test_arm_max78000fthr.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +# +# Functional test that checks the max78000fthr machine. +# Tests ICC, GCR, TRNG, AES, and UART +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import QemuSystemTest, Asset, exec_command_and_wait_for_pat= tern +from qemu_test import wait_for_console_pattern + + +class Max78000Machine(QemuSystemTest): + + ASSET_FW =3D Asset( + 'https://github.com/JacksonDonaldson/max78000Test/raw/main/build/m= ax78000.bin', + '86940b4bf60931bc6a8aa5db4b9f7f3cf8f64dbbd7ac534647980e536cf3adf7') + + def test_fthr(self): + self.set_machine('max78000fthr') + fw_path =3D self.ASSET_FW.fetch() + self.vm.set_console() + self.vm.add_args('-kernel', fw_path) + self.vm.add_args('-device', "loader,file=3D" + fw_path + ",addr=3D= 0x10000000") + self.vm.launch() + + wait_for_console_pattern(self, 'started') + + # i -> prints instruction cache values + exec_command_and_wait_for_pattern(self, 'i', 'CTRL: 00010001') + + # r -> gcr resets the machine + exec_command_and_wait_for_pattern(self, 'r', 'started') + + # z -> sets some memory, then has gcr zero it + exec_command_and_wait_for_pattern(self, 'z', 'initial value: 12345= 678') + wait_for_console_pattern(self, "after memz: 00000000") + + # t -> runs trng + exec_command_and_wait_for_pattern(self, 't', 'random data:') + + # a -> runs aes + exec_command_and_wait_for_pattern(self, 'a', + 'encrypted to : a47ca9dd e0df4c86 a070af6e 91710dec') + wait_for_console_pattern(self, + 'encrypted to : cab7a28e bf456751 9049fcea 8960494b') + +if __name__ =3D=3D '__main__': + QemuSystemTest.main() --=20 2.43.0