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a="65875708" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875708" X-CSE-ConnectionGUID: 1X/Rxy0oRcOUEC31dT+taA== X-CSE-MsgGUID: S5Gbzhy/TA+8p0gI5AEzPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894379" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu , Dapeng Mi , Tao Su Subject: [PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids Date: Fri, 11 Jul 2025 18:45:57 +0800 Message-Id: <20250711104603.1634832-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229563747116600 Add the cache model to SapphireRapids (v4) to better emulate its environment. The cache model is based on SapphireRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7f (127) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xf (15) number of sets =3D 0x10000 (65536) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 65536 (size synth) =3D 62914560 (60 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Reviewed-by: Dapeng Mi Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ce063fb6492..e9f3434b096c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2881,6 +2881,97 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches xeon_spr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 2048, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 15, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 65536, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 60 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_gnr_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -4887,6 +4978,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 4, + .note =3D "with spr-sp cache model", + .cache_info =3D &xeon_spr_cache_info, + }, { /* end of list */ } } }, --=20 2.34.1