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a="65875698" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875698" X-CSE-ConnectionGUID: wrI5XKviTy6Bt+nM7K14bA== X-CSE-MsgGUID: Ns3+FlWyT0CUlFiyZfF5Zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894352" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu , Dapeng Mi , Tao Su Subject: [PATCH v2 1/9] i386/cpu: Introduce cache model for SierraForest Date: Fri, 11 Jul 2025 18:45:55 +0800 Message-Id: <20250711104603.1634832-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229558951116600 Add the cache model to SierraForest (v3) to better emulate its environment. The cache model is based on SierraForest-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x80 (128) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 128 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7 (7) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x1000 (4096) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 4096 (size synth) =3D 4194304 (4 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1ff (511) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x24000 (147456) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 147456 (size synth) =3D 113246208 (108 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Reviewed-by: Dapeng Mi Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f88fe0c8697..a97ee3c2af43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2878,6 +2878,97 @@ static const CPUCaches epyc_turin_cache_info =3D { .no_invd_sharing =3D true, .complex_indexing =3D false, .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + } +}; + +static const CPUCaches xeon_srf_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 128, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 4096, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 4 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_MODULE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 147456, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 108 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, }, }; =20 @@ -5003,6 +5094,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with srf-sp cache model", + .cache_info =3D &xeon_srf_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229505; cv=none; d=zohomail.com; s=zohoarc; b=gWbLOc0N7eNTLOhYI9AYKzrUs1x11D5WC9pUfJb3SeoXNdgE6Qrmd+dl1sF3fkMpaj2HLzrOXGND55p95BypWpZS5xVZB80Rp29MN5awwaaMAMpmg31C+dawoTAwKNsLpFE8+MKqRTcxRgBivs6B+DkM0g6g0PlYG8vZHhwuzcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752229505; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: J1JYt11lRMavqMi2XuC/kQ== X-CSE-MsgGUID: +dfn4P88RgS6SxK7vraPsw== X-IronPort-AV: E=McAfee;i="6800,10657,11490"; a="65875703" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875703" X-CSE-ConnectionGUID: 6hnUyf7+SPigmjsIrPHmMQ== X-CSE-MsgGUID: PvNQcGkpT+ybdzM28jPvRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894366" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu , Dapeng Mi , Tao Su Subject: [PATCH v2 2/9] i386/cpu: Introduce cache model for GraniteRapids Date: Fri, 11 Jul 2025 18:45:56 +0800 Message-Id: <20250711104603.1634832-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229506508116600 Add the cache model to GraniteRapids (v3) to better emulate its environment. The cache model is based on GraniteRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0xff (255) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x48000 (294912) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 294912 (size synth) =3D 301989888 (288 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Reviewed-by: Dapeng Mi Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a97ee3c2af43..4ce063fb6492 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2881,6 +2881,97 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches xeon_gnr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 2048, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 294912, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 288 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_srf_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -4949,6 +5040,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with gnr-sp cache model", + .cache_info =3D &xeon_gnr_cache_info, + }, { /* end of list */ }, }, }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229562; cv=none; d=zohomail.com; s=zohoarc; b=KOO658I9rNTA3EgpvKmu8bw3bHwXhrTu0H42DzF28ySGmGjNGzYX6gCvd1iPMI8DnXSwwjN35ZWxGHZjQIxltjm/kxyVkx2vou+bpmu17bbfgXJY5CWBgSy9SFwLIrmLeRX4k5C0tYchCdL8RvJGcUYMmWoVfqDUs5ETdVBcdIg= ARC-Message-Signature: i=1; a=rsa-sha256; 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bh=06OcXVaxydeMp3sy0wKbWkoF3mbKesOZtzyfFSAZLRw=; b=jGF8qoSLqueMnu1BtuzwlGxwAOHy0OV4MHe5eWXcnmdFIEkyRFinihnb wne47u1KObveFg76YEx/B4UqrEqn8oDqh5O83M1czgyEDL3KkI5btOlqn 4JWYpjr8i1gQIIAcAwC1PGkXokVa9K6X8AA7Ik/v6e6EBYCUP54AUao+9 ortW1WK978qTi7OlaqE6vZeT+byiyu1cnKfhYtmrOWVTWEXRCDnKAXwow IZmN4x4Xfo+d+8peiBM6ig0QLERC1OvwudTusCaT6EtGOXXtfrMeAecVN kzenvK1vtPn0MiuzujYGV6JJx3Oes4XjpI0ZDyi1pqnTwFNzgXHYus1R/ Q==; X-CSE-ConnectionGUID: Dvo9zlOJQNOYR5awB/cxzg== X-CSE-MsgGUID: DcHPtLUaQgaCollonLgKwQ== X-IronPort-AV: E=McAfee;i="6800,10657,11490"; a="65875708" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875708" X-CSE-ConnectionGUID: 1X/Rxy0oRcOUEC31dT+taA== X-CSE-MsgGUID: S5Gbzhy/TA+8p0gI5AEzPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894379" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu , Dapeng Mi , Tao Su Subject: [PATCH v2 3/9] i386/cpu: Introduce cache model for SapphireRapids Date: Fri, 11 Jul 2025 18:45:57 +0800 Message-Id: <20250711104603.1634832-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229563747116600 Add the cache model to SapphireRapids (v4) to better emulate its environment. The cache model is based on SapphireRapids-SP (Scalable Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xc (12) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 49152 (48 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x1 (1) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x800 (2048) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 2048 (size synth) =3D 2097152 (2 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7f (127) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0xf (15) number of sets =3D 0x10000 (65536) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 65536 (size synth) =3D 62914560 (60 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Tejus GK Suggested-by: Jason Zeng Suggested-by: "Daniel P . Berrang=C3=A9" Reviewed-by: Dapeng Mi Reviewed-by: Tao Su Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4ce063fb6492..e9f3434b096c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2881,6 +2881,97 @@ static const CPUCaches epyc_turin_cache_info =3D { } }; =20 +static const CPUCaches xeon_spr_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 12, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 48 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 2048, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 2 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 15, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 65536, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 60 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches xeon_gnr_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -4887,6 +4978,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 4, + .note =3D "with spr-sp cache model", + .cache_info =3D &xeon_spr_cache_info, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229557; cv=none; d=zohomail.com; s=zohoarc; b=RC7pyfGrGNDbyO9zLShwo8vfTMHI/s7wNYhWW90sQznbV0M/C4rtOph4Aeoh4hYXXd8T7zfXGqyDVqMwuky9OIaaEPKVSk2MBoRGO2fsOmmJdNZlRpGbOCS/dhH9kM71YJygIgofwpspZoxtuNHEJeZGpwhTZEmvg1cX4HbEkzc= ARC-Message-Signature: i=1; a=rsa-sha256; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229558955116600 Content-Type: text/plain; charset="utf-8" From: Ewan Hai Add the cache model to YongFeng (v3) to better emulate its environment. Note, although YongFeng v2 was added after v10.0, it was also back ported to v10.0.2. Therefore, the new version (v3) is needed to avoid conflict. The cache model is as follows: --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x200 (512) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D true complex cache indexing =3D false number of sets (s) =3D 512 (size synth) =3D 262144 (256 KB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x0 (0) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x2000 (8192) WBINVD/INVD acts on lower caches =3D true inclusive to lower caches =3D true complex cache indexing =3D false number of sets (s) =3D 8192 (size synth) =3D 8388608 (8 MB) --- cache 4 --- cache type =3D no more caches (0) Tested-by: Yi Lai Signed-off-by: Ewan Hai Signed-off-by: Zhao Liu --- Changes Since v1: * Polish the note. Changes on the original codes: * Rearrange cache model fields to make them easier to check. * And add explanation of why v3 is needed. * Drop lines_per_tag field for L2 & L3. --- target/i386/cpu.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e9f3434b096c..5676e5526f40 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3154,6 +3154,105 @@ static const CPUCaches xeon_srf_cache_info =3D { }, }; =20 +static const CPUCaches yongfeng_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.ECX */ + .lines_per_tag =3D 1, + .size =3D 32 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + /* CPUID 0x80000005.EDX */ + .lines_per_tag =3D 1, + .size =3D 64 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 512, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D true, + .complex_indexing =3D false, + + /* CPUID 0x80000006.ECX */ + .size =3D 256 * KiB, + + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 8192, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D true, + .inclusive =3D true, + .complex_indexing =3D false, + + .size =3D 8 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -6433,6 +6532,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } } }, + { + .version =3D 3, + .note =3D "with the cache model", + .cache_info =3D &yongfeng_cache_info, + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229659; cv=none; d=zohomail.com; s=zohoarc; b=MLg/rhG8+CpuNM6bV+gU2yEXBxrexAhh54pC6iRsqXIJB/spWchTpnIWojQr82ltbvY/ZXgkJR9EIkURDTKiCzEN9fRkJfJxNbGuV8gAAxCgboDjxX6uuH+ANnbokl2WyDjf892APbzbe5uHFMyV8CuqKNQnizktj6gZ7l/YNQQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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bh=/dbJpXZ+WoEY+wWTUOHZZkTlAY66zw+zpoaPJAtvbjw=; b=KB5eJ/lhCbbZLWYhSzFGmHmepd5w3/URsTdPEWm47frT4PGpJCRhRMri CKLKY/Gj0Kpz0z8YboYBtOg0qCdn2WP+G44xCgGdFA1H81mVRj08W5MV1 VqYFf7IkZr47nglcmFu3yWZwMwHR6AEKFdGSAVtbmnAGrUgz4nnvpuK0G Eo51FIksami26GHDs5woCkxHCdDVqJz/r4YmGTwGZNlAhqUyzm7zlKyuP LjOB7cGHV+EfscXLZNR4G+LMKba61ExyTJY4rzefrn5Ia+Cl9J/R85JW0 4fdknKOasEqrh52u/Tq2ognp86zaZXAnCyradOKfVW1EuHH8dLjvP5jwE Q==; X-CSE-ConnectionGUID: hugTJbURRXW2DrFtDmh99A== X-CSE-MsgGUID: WIEyWdgJQQi8TSMz40YYXA== X-IronPort-AV: E=McAfee;i="6800,10657,11490"; a="65875719" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875719" X-CSE-ConnectionGUID: 09HYi2rTTCyvfFtcl4+bRQ== X-CSE-MsgGUID: Igb0fkN8SVuowwA6URQ3Iw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894398" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu , Dapeng Mi Subject: [PATCH v2 5/9] i386/cpu: Add a "x-force-cpuid-0x1f" property Date: Fri, 11 Jul 2025 18:45:59 +0800 Message-Id: <20250711104603.1634832-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229661737116600 Content-Type: text/plain; charset="utf-8" From: Manish Mishra Add a "x-force-cpuid-0x1f" property so that CPU models can enable it and have 0x1f CPUID leaf natually as the Host CPU. The advantage is that when the CPU model's cache model is already consistent with the Host CPU, for example, SRF defaults to l2 per module & l3 per package, 0x1f can better help users identify the topology in the VM. Adding 0x1f for specific CPU models should not cause any trouble in principle. This property is only enabled for CPU models that already have 0x1f leaf on the Host, so software that originally runs normally on the Host won't encounter issues in the Guest with corresponding CPU model. Conversely, some software that relies on checking 0x1f might have problems in the Guest due to the lack of 0x1f [*]. In summary, adding 0x1f is also intended to further emulate the Host CPU environment. [*]: https://lore.kernel.org/qemu-devel/PH0PR02MB738410511BF51B12DB09BE6CF6= AC2@PH0PR02MB7384.namprd02.prod.outlook.com/ Signed-off-by: Manish Mishra Co-authored-by: Xiaoyao Li Signed-off-by: Xiaoyao Li [Integrated and rebased 2 previous patches (ordered by post time)] Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Note: This patch integrates the idea from 2 previous posted patches (ordered by post time)[1] [2], following the s-o-b policy of "Re-starting abandoned work" in docs/devel/code-provenance.rst. [1]: From Manish: https://lore.kernel.org/qemu-devel/20240722101859.47408-1= -manish.mishra@nutanix.com/ [2]: From Xiaoyao: https://lore.kernel.org/qemu-devel/20240813033145.279307= -1-xiaoyao.li@intel.com/ --- Changes since RFC: * Rebase and rename the property as "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5676e5526f40..d27eeb1cb718 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9940,6 +9940,7 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, t= rue), + DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false= ), }; =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229661; cv=none; d=zohomail.com; s=zohoarc; b=MZ5NtBaxTvYSV59DGbtH+2TuOraw+OVALEXfZrRyqXjE3ELp9tte36XxkAFGhcZw83OcP0bQ9ki0QuSKa3F6j+NLaLGXAlC9ARFA5/y3BdtRU+vPPBGZhPEsxepl/F2QMmZyKnE2ld4Lm0nU1eyt0133fafcPPtJT20zaAxeHB0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229663705116600 Content-Type: text/plain; charset="utf-8" Host SierraForest CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d27eeb1cb718..2f19726a9397 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5387,8 +5387,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with srf-sp cache model", + .note =3D "with srf-sp cache model and 0x1f leaf", .cache_info =3D &xeon_srf_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229567; cv=none; d=zohomail.com; s=zohoarc; b=HKTCXsZ3ZpcOtX5Nn0vp+aw6Njm5Uw7fXSDorDz3GJoXjQp80tUMy4ViGXnAENDv0LE8EwoSsBjlbGsgOe9qumX1rOX3nbzx39L/DPFROTfjSvh3XI6hU5nkdkiZkYLQ1c1upCGB2t0RMFZoeaOuEhl93oQuGcgKqlFLoSfMhAY= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229568849116600 Content-Type: text/plain; charset="utf-8" Host GraniteRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2f19726a9397..02198872ede7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5237,8 +5237,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with gnr-sp cache model", + .note =3D "with gnr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_gnr_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ }, }, --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229574; cv=none; d=zohomail.com; s=zohoarc; b=fCiR4iibcrLGrtn4QoTRiIU3UFPdbpmAXbzFjJVc5B0OK0RQWaEesOpuuTmYHDkUjEIfo3bKBuKgSb6H6RdITuHwfk0U0I+P13ae3aUp/FSxiK/61rJ2LUjQqfyXpvW7e02bKulpC8U7RokYOiNzKi5fH/X5bqxxxLKQwKv6FcA= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229576880116600 Content-Type: text/plain; charset="utf-8" Host SapphireRapids CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Igor Mammedov Reviewed-by: Dapeng Mi Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes since RFC: * Rename the property to "x-force-cpuid-0x1f". (Igor) --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 02198872ede7..44394fa72248 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5079,8 +5079,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 4, - .note =3D "with spr-sp cache model", + .note =3D "with spr-sp cache model and 0x1f leaf", .cache_info =3D &xeon_spr_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ } } --=20 2.34.1 From nobody Sun Dec 14 02:01:14 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752229657; cv=none; d=zohomail.com; s=zohoarc; b=Q5QC9v6b6GyGSGu8CStLNzKDszUui3AJ7gDpCWTryImFx1VB/l0zv3b0irqx1M8DGqCdtFEK3nXhvavmo2uL0EXB3E0Ze4j5rr65Y2IGXvFapojpGd5nCLNv6moOYgfuTR+9E8x5f4PKelatRUTWo3KtuGruZScLIkeXGB5qny8= ARC-Message-Signature: i=1; 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bh=9uFL0qeomU0SB61XzpERu9/oG9C3jYtplLZUWWP9Gkg=; b=Z8PmYOp7ykTW0ESlQjiaN4zGXVvwY+0ZrTkU0N93IoOANB61RPJ+kOvr NiJADCP/GSGGEpHoHmD/tq8y5Uma9bJNsTpj8RpTVmiP29veIyl+nejE2 uXOEC1fpsiL0A4C4RU7DbSLhGl4Mz8+bVdisH/PVYHi4UgNKsUS5HkcKK xoNMLl/vM2LwQhkembK/eTwQCsD7HmvEro2/lhMaymzyFE42ImIFzLuAM LstFREBekUy2yxU0FrQTckGj0yCJ0xpMyZeiJ8GZnqyrd2YMWCJfaSpZp d4ueZUogzd9v5un0HIA7LxcdqLsVgxXEydBvyb+DWHYYHXBiPFXvb+T6d Q==; X-CSE-ConnectionGUID: ciYfPoaBRLSZIePBGxYCKw== X-CSE-MsgGUID: w50Ce7Q5Q3uPSobKZ7cHZg== X-IronPort-AV: E=McAfee;i="6800,10657,11490"; a="65875740" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="65875740" X-CSE-ConnectionGUID: 8mKjFfF0THqdhwZ9WAcWKA== X-CSE-MsgGUID: OmBRQ8VERd2Dtbefohv/vw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="156894444" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH v2 9/9] i386/cpu: Enable 0x1f leaf for YongFeng by default Date: Fri, 11 Jul 2025 18:46:03 +0800 Message-Id: <20250711104603.1634832-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711104603.1634832-1-zhao1.liu@intel.com> References: <20250711104603.1634832-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752229657618116600 Content-Type: text/plain; charset="utf-8" Host YongFeng CPU has 0x1f leaf by default, so that enable it for Guest CPU by default as well. Suggested-by: Ewan Hai Tested-by: Yi Lai Signed-off-by: Zhao Liu --- Changes Since v1: * New patch suggested by Ewan. --- target/i386/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 44394fa72248..8d67cadec2f2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6543,8 +6543,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with the cache model", + .note =3D "with the cache model and 0x1f leaf", .cache_info =3D &yongfeng_cache_info, + .props =3D (PropValue[]) { + { "x-force-cpuid-0x1f", "on" }, + } }, { /* end of list */ } } --=20 2.34.1