From nobody Fri Dec 19 06:31:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752228246; cv=none; d=zohomail.com; s=zohoarc; b=I0oUStUYpI9a4Ns9QaCaDMZZF+ipicJ35cf80N+qnIAFGd+26ya6r8pVMvtd9s/eI5d2jB3W42V7toq0IVAJtXf7Ucmjm9kH6nHvfnwwNWOoADfJSbpO0kchjPjWaVrxArNn9wuAbuRkdi40K7W+GnKOFF35CHI/G91tKrkShRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752228246; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Cl1uXL8p22znqLBNNHNmkP8u3WqiSG893BdAeYsMUe8=; b=KgkFUyfza4UdW94Z7qM25EueM7ODnt/Syweg2Ks2zQmZUIkzeI+rIjOknBd4jbBr2dxPseQ/hRObV9aH+jPvw2YBv+LVmzXpXuVRMjGte3KIO/qagUfRl8tHfHlFbnu7Q67jMGpzDnkQwIIKAKX5C6DLToItL+v1ATYZbty/2Qw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752228246189943.6424748999239; Fri, 11 Jul 2025 03:04:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uaAaC-0005Rs-8S; Fri, 11 Jul 2025 06:02:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaAZg-0003wv-Hg for qemu-devel@nongnu.org; Fri, 11 Jul 2025 06:01:48 -0400 Received: from mgamail.intel.com ([198.175.65.17]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uaAZe-0005cy-9n for qemu-devel@nongnu.org; Fri, 11 Jul 2025 06:01:48 -0400 Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2025 03:01:45 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa003.jf.intel.com with ESMTP; 11 Jul 2025 03:01:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752228106; x=1783764106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XIdoThL/w+88qJ0nzFUPEXeYz1YyOXsdwaPKHQb2Un8=; b=KWwYyYp+fZQOFq7il7Dn2MCGAjOVp4c/ZmSMvavRKBcsLzXM339ERKQm maDgcJSWfcBTwbBPNBn1F9+VISMJXdgpNl51DqNagbl/9jutbb7dMINml sLfir4XS/nh8qglGTYZtrOLQ4JZl3cLGDR+K9edNd2gOBJ664QQjk5TWK P+s1zRKxpa2hV17C9chYVc0WqAbBSqZXBJXMDdOMcGI73Oe9+rprAGBps eGxSd50rY1VQnYMvH0vwvwIeFqEITOxAAq+7NB0jhFr89TvdIBAe/+n0i vPQT3skJ+uEvsQ9e3TibBuounzBTxKANfPCLn+KI2BAeoDZIQkr0H5wt0 A==; X-CSE-ConnectionGUID: lw1veNEgSP2hv0gGIK9RFQ== X-CSE-MsgGUID: w85HEczXSiyke0vmZ9p5rw== X-IronPort-AV: E=McAfee;i="6800,10657,11490"; a="54496451" X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="54496451" X-CSE-ConnectionGUID: VE1FAdX3SfqhL5gNMRIQvQ== X-CSE-MsgGUID: vdtHbcFEQEqYm/U0kIVTnw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,303,1744095600"; d="scan'208";a="160662159" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org, Zhao Liu Subject: [PATCH v2 17/18] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D Date: Fri, 11 Jul 2025 18:21:42 +0800 Message-Id: <20250711102143.1622339-18-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711102143.1622339-1-zhao1.liu@intel.com> References: <20250711102143.1622339-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752228248834116600 Content-Type: text/plain; charset="utf-8" As preparation for merging cache_info_cpuid4 and cache_info_amd in X86CPUState, set legacy cache model based on vendor in the CPUID 0x8000001D leaf. For AMD CPU, select legacy AMD cache model (in cache_info_amd) as the default cache model like before, otherwise, select legacy Intel cache model (in cache_info_cpuid4). In fact, for Intel (and Zhaoxin) CPU, this change is safe because the extended CPUID level supported by Intel is up to 0x80000008. So Intel Guest doesn't have this 0x8000001D leaf. Although someone could bump "xlevel" up to 0x8000001D for Intel Guest, it's meaningless and this is undefined behavior. This leaf should be considered reserved, but the SDM does not explicitly state this. So, there's no need to specifically use vendor_cpuid_only_v2 to fix anything, as it doesn't even qualify as a fix since nothing is currently broken. Therefore, it is acceptable to select the default legacy cache model based on the vendor. For the CPUID 0x8000001D leaf, in X86CPUState, a unified cache_info is enough. It only needs to be initialized and configured with the corresponding legacy cache model based on the vendor. Tested-by: Yi Lai Signed-off-by: Zhao Liu --- target/i386/cpu.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fe1c118b284f..df13dbc63a3f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8082,7 +8082,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *edx =3D 0; } break; - case 0x8000001D: + case 0x8000001D: { + const CPUCaches *caches; + + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * Intel doesn't support this leaf so that Intel Guests don't + * have this leaf. This change is harmless to Intel CPUs. + */ + if (IS_AMD_CPU(env)) { + caches =3D &env->cache_info_amd; + } else { + caches =3D &env->cache_info_cpuid4; + } + *eax =3D 0; if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -8090,19 +8105,19 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + encode_cache_cpuid8000001d(caches->l1d_cache, topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + encode_cache_cpuid8000001d(caches->l1i_cache, topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + encode_cache_cpuid8000001d(caches->l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + encode_cache_cpuid8000001d(caches->l3_cache, topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ @@ -8113,6 +8128,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *edx &=3D CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; } break; + } case 0x8000001E: if (cpu->core_id <=3D 255) { encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); --=20 2.34.1