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Thu, 10 Jul 2025 17:06:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+/T1OnB8IvOBYkpp76pElaF0Nz3/XEzCi3Q0BfqeJntjn+ksixk15n+UWeqJzBUAhHjIEtQ== X-Received: by 2002:a05:600c:4444:b0:453:6ca:16b1 with SMTP id 5b1f17b1804b1-454ec2726c9mr5489065e9.26.1752192375680; Thu, 10 Jul 2025 17:06:15 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: xiaoyao.li@intel.com, zhao1.liu@intel.com Subject: [PATCH 1/4] target/i386: move max_features to class Date: Fri, 11 Jul 2025 02:06:00 +0200 Message-ID: <20250711000603.438312-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250711000603.438312-1-pbonzini@redhat.com> References: <20250711000603.438312-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752192435916116600 Content-Type: text/plain; charset="utf-8" max_features is always set to true for instances created by -cpu max or -cpu host; it's always false for other classes. Therefore it can be turned into a field in the X86CPUClass. Signed-off-by: Paolo Bonzini Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 5 +++-- target/i386/hvf/hvf-cpu.c | 3 ++- target/i386/kvm/kvm-cpu.c | 5 +++-- 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 51e10139dfd..be3ae6d546e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2196,7 +2196,6 @@ struct ArchCPU { bool expose_tcg; bool migratable; bool migrate_smi_count; - bool max_features; /* Enable all supported features automatically */ uint32_t apic_id; =20 /* Enables publishing of TSC increment and Local APIC bus frequencies = to @@ -2349,6 +2348,7 @@ struct X86CPUClass { */ const X86CPUModel *model; =20 + bool max_features; /* Enable all supported features automatically */ bool host_cpuid_required; int ordering; bool migration_safe; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0d35e95430f..624cebc3ff7 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6187,6 +6187,7 @@ static void max_x86_cpu_class_init(ObjectClass *oc, c= onst void *data) =20 xcc->ordering =3D 9; =20 + xcc->max_features =3D true; xcc->model_description =3D "Enables all features supported by the accelerator in the current = host"; =20 @@ -6201,7 +6202,6 @@ static void max_x86_cpu_initfn(Object *obj) /* We can't fill the features array here because we don't know yet if * "migratable" is true or false. */ - cpu->max_features =3D true; object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); =20 /* @@ -8282,6 +8282,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) */ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) { + X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); CPUX86State *env =3D &cpu->env; FeatureWord w; int i; @@ -8306,7 +8307,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) * plus_features & minus_features to global properties * inside x86_cpu_parse_featurestr() too. */ - if (cpu->max_features) { + if (xcc->max_features) { for (w =3D 0; w < FEATURE_WORDS; w++) { /* Override only features that weren't set explicitly * by the user. diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c index dfdda701268..2b991f2fc8e 100644 --- a/target/i386/hvf/hvf-cpu.c +++ b/target/i386/hvf/hvf-cpu.c @@ -61,13 +61,14 @@ static void hvf_cpu_xsave_init(void) static void hvf_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); + X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); =20 host_cpu_instance_init(cpu); =20 /* Special cases not set in the X86CPUDefinition structs: */ /* TODO: in-kernel irqchip for hvf */ =20 - if (cpu->max_features) { + if (xcc->max_features) { hvf_cpu_max_instance_init(cpu); } =20 diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 16bde4de01e..0fb88a239d4 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -41,6 +41,7 @@ static void kvm_set_guest_phys_bits(CPUState *cs) static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) { X86CPU *cpu =3D X86_CPU(cs); + X86CPUClass *xcc =3D X86_CPU_GET_CLASS(cpu); CPUX86State *env =3D &cpu->env; bool ret; =20 @@ -63,7 +64,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * check/update ucode_rev, phys_bits, guest_phys_bits, mwait * cpu_common_realizefn() (via xcc->parent_realize) */ - if (cpu->max_features) { + if (xcc->max_features) { if (enable_cpu_pm) { if (kvm_has_waitpkg()) { env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; 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Thu, 10 Jul 2025 17:06:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGfcgldzrWafJ/8ZemFSYEOm8yF2CzsmEhWaXdTv7mT3Q6tVs0aNjQJYJID/sKTivFdcWFZ1g== X-Received: by 2002:a05:6000:2503:b0:3a4:dc42:a0ac with SMTP id ffacd0b85a97d-3b5f18f608fmr970404f8f.49.1752192381205; Thu, 10 Jul 2025 17:06:21 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: xiaoyao.li@intel.com, zhao1.liu@intel.com Subject: [PATCH 2/4] target/i386: nvmm, whpx: add accel/CPU class that sets host vendor Date: Fri, 11 Jul 2025 02:06:01 +0200 Message-ID: <20250711000603.438312-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250711000603.438312-1-pbonzini@redhat.com> References: <20250711000603.438312-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752192485447116600 Content-Type: text/plain; charset="utf-8" NVMM and WHPX are virtualizers, and therefore they need to use (at least by default) the host vendor for the guest CPUID. Add a cpu_instance_init implementation to these accelerators. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 8 +++++++- target/i386/nvmm/nvmm-all.c | 23 +++++++++++++++++++++++ target/i386/whpx/whpx-all.c | 23 +++++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 624cebc3ff7..69bdffbfe46 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -43,6 +43,7 @@ #include "hw/boards.h" #include "hw/i386/sgx-epc.h" #endif +#include "system/qtest.h" #include "tcg/tcg-cpu.h" =20 #include "disas/capstone.h" @@ -1943,7 +1944,7 @@ uint32_t xsave_area_size(uint64_t mask, bool compacte= d) =20 static inline bool accel_uses_host_cpuid(void) { - return kvm_enabled() || hvf_enabled(); + return !tcg_enabled() && !qtest_enabled(); } =20 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index b4a4d50e860..69125230abb 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -1207,10 +1207,33 @@ static const TypeInfo nvmm_accel_type =3D { .class_init =3D nvmm_accel_class_init, }; =20 +static void nvmm_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); +} + +static void nvmm_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D nvmm_cpu_instance_init; +} + +static const TypeInfo nvmm_cpu_accel_type =3D { + .name =3D ACCEL_CPU_NAME("nvmm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D nvmm_cpu_accel_class_init, + .abstract =3D true, +}; + static void nvmm_type_init(void) { type_register_static(&nvmm_accel_type); + type_register_static(&nvmm_cpu_accel_type); } =20 type_init(nvmm_type_init); diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index faf56e19722..b380459d6fe 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2500,6 +2500,28 @@ static void whpx_set_kernel_irqchip(Object *obj, Vis= itor *v, } } =20 +static void whpx_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); +} + +static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D whpx_cpu_instance_init; +} + +static const TypeInfo whpx_cpu_accel_type =3D { + .name =3D ACCEL_CPU_NAME("whpx"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D whpx_cpu_accel_class_init, + .abstract =3D true, +}; + /* * Partition support */ @@ -2726,6 +2748,7 @@ static const TypeInfo whpx_accel_type =3D { static void whpx_type_init(void) { type_register_static(&whpx_accel_type); + type_register_static(&whpx_cpu_accel_type); } =20 bool init_whp_dispatch(void) --=20 2.50.0 From nobody Mon Dec 15 21:29:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Thu, 10 Jul 2025 17:06:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGCeBCjWW7gscQYOiEalbWaDB7ZdEriztzByvyPw7w09XAUBAbNyb3kuQ4/BOueiLDu8DRl+w== X-Received: by 2002:a05:6000:26ca:b0:3aa:caea:aa7f with SMTP id ffacd0b85a97d-3b5f2e4901amr447805f8f.56.1752192386738; Thu, 10 Jul 2025 17:06:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: xiaoyao.li@intel.com, zhao1.liu@intel.com Subject: [PATCH 3/4] target/i386: allow reordering max_x86_cpu_initfn vs accel CPU init Date: Fri, 11 Jul 2025 02:06:02 +0200 Message-ID: <20250711000603.438312-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250711000603.438312-1-pbonzini@redhat.com> References: <20250711000603.438312-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752192435946116600 Content-Type: text/plain; charset="utf-8" The PMU feature is only supported by KVM, so move it there. And since all accelerators other than TCG overwrite the vendor, set it in max_x86_cpu_initfn only if it has not been initialized by the superclass. This makes it possible to run max_x86_cpu_initfn after accelerator init. Signed-off-by: Paolo Bonzini Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu --- target/i386/cpu.c | 24 ++++++++++++------------ target/i386/kvm/kvm-cpu.c | 2 ++ 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 69bdffbfe46..46d59229200 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6204,21 +6204,21 @@ static void max_x86_cpu_class_init(ObjectClass *oc,= const void *data) static void max_x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); - - /* We can't fill the features array here because we don't know yet if - * "migratable" is true or false. - */ - object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + CPUX86State *env =3D &cpu->env; =20 /* - * these defaults are used for TCG and all other accelerators - * besides KVM and HVF, which overwrite these values + * these defaults are used for TCG, other accelerators overwrite these + * values */ - object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, - &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", - "QEMU TCG CPU version " QEMU_HW_VERSION, - &error_abort); + if (!env->cpuid_vendor1) { + object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, + &error_abort); + } + if (!env->cpuid_model[0]) { + object_property_set_str(OBJECT(cpu), "model-id", + "QEMU TCG CPU version " QEMU_HW_VERSION, + &error_abort); + } } =20 static const TypeInfo max_x86_cpu_type_info =3D { diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 0fb88a239d4..6fed353548e 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -111,6 +111,8 @@ static void kvm_cpu_max_instance_init(X86CPU *cpu) =20 host_cpu_max_instance_init(cpu); =20 + object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + if (lmce_supported()) { object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); } --=20 2.50.0 From nobody Mon Dec 15 21:29:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Thu, 10 Jul 2025 17:06:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGiq+8PT+39k8woi1szLsWTlwjyxZzgWbWPZ2b4aKH1GJ2nz38LYvfle0ZMuKv/W5NgZ+/FiQ== X-Received: by 2002:a05:600c:4ab0:b0:453:79e8:e92d with SMTP id 5b1f17b1804b1-454db88fe12mr37626145e9.5.1752192392211; Thu, 10 Jul 2025 17:06:32 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: xiaoyao.li@intel.com, zhao1.liu@intel.com Subject: [PATCH 4/4] target/i386: move accel_cpu_instance_init to .instance_init Date: Fri, 11 Jul 2025 02:06:03 +0200 Message-ID: <20250711000603.438312-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250711000603.438312-1-pbonzini@redhat.com> References: <20250711000603.438312-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1752192752894116600 Content-Type: text/plain; charset="utf-8" With the reordering of instance_post_init callbacks that is new in 10.1 accel_cpu_instance_init must execute in .instance_init as is already the case for RISC-V. Otherwise, for example, setting the vendor property is broken when using KVM or Hypervisor.framework, because KVM sets it *after* the user's value is set by DeviceState's intance_post_init callback. Reported-by: Xiaoyao Li Signed-off-by: Paolo Bonzini Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 46d59229200..5f95bb97b82 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6207,8 +6207,8 @@ static void max_x86_cpu_initfn(Object *obj) CPUX86State *env =3D &cpu->env; =20 /* - * these defaults are used for TCG, other accelerators overwrite these - * values + * these defaults are used for TCG, other accelerators have overwritten + * these values */ if (!env->cpuid_vendor1) { object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, @@ -9043,8 +9043,6 @@ static void x86_cpu_post_initfn(Object *obj) } } =20 - accel_cpu_instance_init(CPU(obj)); - #ifndef CONFIG_USER_ONLY if (current_machine && current_machine->cgs) { x86_confidential_guest_cpu_instance_init( @@ -9119,6 +9117,8 @@ static void x86_cpu_initfn(Object *obj) if (xcc->model) { x86_cpu_load_model(cpu, xcc->model); } + + accel_cpu_instance_init(CPU(obj)); } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) --=20 2.50.0