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[189.47.46.41]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de434d6b0sm30447775ad.203.2025.07.10.14.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 14:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752181864; x=1752786664; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=24pxxDuWEZzb6wGY252RDxtIpjDwPD+IPgiDjqz1YEk=; b=X1Z9YOEVJfzdFQuge4oO9eNx4hl8I7Juj7Uqr2wF1jKzo3+EOxBDoYf3Pp9ZpX3UyJ hhhP9LbKpKR92HGRqg0787l7uuFpUfObPGxrT2sy0VN+SNBwVV6QeyXOxswveNrEky1C 3SI4kLy1/wkc9b7SdAp3FVWiyuu4+lW5uye3CpXMZ36ROfU1L3xabCmvkKT9glqf72Rv Gt0QMzAsd7T7JOkQ2dlOGUldKqTM/9KI0hNtQZkf+wNIqW/TRfwoAtZ5lm6R/F+E1HYJ ksZysUlEhqW+8s9QvwhYiDEgx2YrhKodmddYOwPQ9Ji0uIZpbNCSWsy03KwfDNYKegbu UyQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752181864; x=1752786664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=24pxxDuWEZzb6wGY252RDxtIpjDwPD+IPgiDjqz1YEk=; b=IW8Oc/Q5jmhEDHyLksd8/9C121o/FQpeHVkq6RmpoFZS/Ux9uVbR2FfbLVgGP+E2SM bxZe/Y0xluQZJfVJXiCJdpooHQz34g5eFhrwC37mwCjeq8MHuAH1fA37AfKW3fsLgoHM XeOoQ04kxn0Pd072YF+v0wtYX8h5FoaS/PA59R3llax3YGkyTIt1zCujGFMJGu5YruDR qBeDmtZO1+lwUOC6yKUyXMWDOKZMt0LJG4mpBv/siuWBX0Itj83oYzhKAiwBLGDN03wb uUIKtqHpxxg33vCXksDjTvK2KqBtoh1H1pN4wxK9nyaK3lB+17Uk0JLfeqE/8hRcu/V7 fVCw== X-Gm-Message-State: AOJu0YzQEeAIMPBGGKGrtZifnIvy3SmieWShcnBZz8vCvKwyXhJy0Muf rTProUukA1tRjGmyjwrBkUOXbH1uHVGE2fZ9lPlktv8VA0fb7rT/WMtDW7wdfbm/xCc= X-Gm-Gg: ASbGnctPa7hErXx+MywBEYedPQ38kR7x84ZZHcOjq8nS8ogkys0rifyn4KNhrD9KKkl wk94DU+raBZZ5LeFpZjj6K0tDTDdYtJvMzb4lkR+BRCWRmzSZx9cMeHSDURVtZcPhhb6vIEL/Qk rn+aezc0Kovobep557gzencs2ExRRdDyX04kaHPO9e3+NdIfHd9ZJj+bBPEHqK0gYxeoPPhIknb gRwSPTt7HryyFH5MeElxyfhsZrac5stMpRHd4wiFp9ycBbwkhhd5yfuh9X3YyiY0IUIosiKMZFB MtKoaL/OOK1ZRtKPG1N2rzBGNQVeJwm2r16HeCBaPA0yTA2tlJYWtwWY5GtHrFBrTNPmwAMLBOs us18l2bO9IWBe8DXS/67C9uT41z5UghFo/2IwBXA59BQxxhQQFrx4ut6fyg== X-Google-Smtp-Source: AGHT+IHmpIsk/2hGSYFiR/Bc3drCbCerDeMpmxZJw04YjfLwK1jehup3Cu6ee9OVmiYhlEZfx/6Tlg== X-Received: by 2002:a17:903:1b63:b0:235:caa8:1a72 with SMTP id d9443c01a7336-23dede81dc8mr9636535ad.30.1752181863928; Thu, 10 Jul 2025 14:11:03 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v6 5/6] target/arm: Implement FEAT_MEC cache instructions Date: Thu, 10 Jul 2025 21:09:40 +0000 Message-Id: <20250710210941.1098088-6-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710210941.1098088-1-gustavo.romero@linaro.org> References: <20250710210941.1098088-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752181926152116600 Content-Type: text/plain; charset="utf-8" This commit implements the two cache maintenance instructions introduced by FEAT_MEC, DC CIPAE and DC CIGDPAE. Because QEMU does not model the cache topology, all cache maintenance instructions are implemented as NOPs, hence these new instructions are implemented as NOPs too. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index ecfd53cc5a..c030f0a0da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6856,6 +6856,18 @@ static void mecid_write(CPUARMState *env, const ARMC= PRegInfo *ri, raw_write(env, ri, value); } =20 +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + static const ARMCPRegInfo mec_reginfo[] =3D { { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, @@ -6895,6 +6907,15 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D mecid_access, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, }; =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9216,6 +9237,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (cpu_isar_feature(aa64_mec, cpu)) { define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } } =20 if (cpu_isar_feature(aa64_sctlr2, cpu)) { --=20 2.34.1