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Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8cf0ab417..0f64c7b163 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1717,6 +1717,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ --=20 2.34.1 From nobody Fri Dec 19 22:05:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752181908; cv=none; d=zohomail.com; s=zohoarc; b=MxMpXP2lO3Qw57f2/De6tise5R/bBskITNSXwYeuy9Eezvdkq98khvRpWaZbBU4cFXcARxw2hkCwJhBUVOCtTrumj2C4u9s2wJQYh5dXzF+pnQBhUne+9esTJWxWh6oe7HKF3X6vMd+nox3HgVi/UuTSCMCiuP0rqngBpcGP3+c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752181908; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZeG1zg84q+9XSbqQeM5w+nO7GmXG52C215che07ehKE=; b=CF74IYRC+Wd4IPFARQdq6XDjKLvVS45O/WaqokmpKsuIa58py/86WZqoGrnRyaQ8/pVzdxEPLHRrsAv/p3Mu4Ff9Ki8Admvkjr3n32tkK5bLtTRFN/fackYqmYtMS9bjzicCPx78vx2ux/oQiodatbKBNbjtVWhjnQ6E5enIjzI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752181908661313.3757177721752; Thu, 10 Jul 2025 14:11:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZyXx-0000Ym-9e; Thu, 10 Jul 2025 17:11:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZyXn-0000V8-8x for qemu-devel@nongnu.org; Thu, 10 Jul 2025 17:11:03 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uZyXl-0006cv-DX for qemu-devel@nongnu.org; Thu, 10 Jul 2025 17:11:02 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-23c703c471dso22728005ad.0 for ; Thu, 10 Jul 2025 14:10:59 -0700 (PDT) Received: from gromero0.. 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To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected and will be implemented in subsequent commits. FEAT_MEC also requires two new cache management instructions, not included in this commit, that will be implemented in a subsequent commit. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 9 +++++ target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 3 ++ 4 files changed, 87 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428..72b6fd9b27 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f64c7b163..40ca093331 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -576,6 +576,15 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index b3f0d6f17a..984406c945 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6827,6 +6827,72 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 2) { + if (arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + + if (!(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value =3D extract64(value, 0, MECID_WIDTH); + raw_write(env, ri, value); +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .access =3D PL2_R, .type =3D ARM_CP_CONST, .resetvalue =3D MECID_WID= TH - 1 }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL3_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9014,6 +9080,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 21a8d67edd..77ba2a2273 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1982,4 +1982,7 @@ void vfp_clear_float_status_exc_flags(CPUARMState *en= v); */ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask); =20 +/* Used in FEAT_MEC to set the MECIDWidthm1 field in the MECIDR_EL2 regist= er. */ +#define MECID_WIDTH 16 + #endif --=20 2.34.1 From nobody Fri Dec 19 22:05:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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These registers are extensions of the SCTLR_ELx ones. Because the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, this commit only implements the EMEC bits in CTLR2_EL2 and SCTLR2_EL3. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 15 +++++++ target/arm/helper.c | 80 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/tcg/cpu64.c | 5 ++- 6 files changed, 106 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 890dc6fee2..66043b0747 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 72b6fd9b27..a5fc2ca572 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 40ca093331..894e2a2997 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -337,6 +337,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1433,6 +1434,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8 /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1725,6 +1739,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/helper.c b/target/arm/helper.c index 984406c945..210a50a21a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6144,6 +6144,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), + "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12" }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), "CPACR", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), @@ -7816,6 +7818,80 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_el2_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult sctlr2_el1_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_SCTLR2EN= )) { + return CP_ACCESS_TRAP_EL2; + } + return sctlr2_el2_access(env, ri, isread); +} + +static void sctlr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* This register does not control any feature yet. */ +} + +static void sctlr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, + .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_el2_access, + .writefn =3D sctlr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9084,6 +9160,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mec_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 77ba2a2273..d18d0fb19a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -232,6 +232,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d0df50a2f3..30505fb293 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,7 +1247,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); 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These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Since the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, the FEAT_TCR2 only implements the AMEC bits for now. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 2 ++ target/arm/helper.c | 62 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 19 +++++++++++ target/arm/tcg/cpu64.c | 1 + 6 files changed, 90 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 66043b0747..1c597d8673 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -149,6 +149,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage= 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage= 1) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a5fc2ca572..9579d93cec 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) !=3D 0; +} + static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 894e2a2997..9f900ee4f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -366,6 +366,7 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ uint64_t tcr_el[4]; + uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ @@ -1739,6 +1740,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) diff --git a/target/arm/helper.c b/target/arm/helper.c index 210a50a21a..ecfd53cc5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6154,6 +6154,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), + "TCR2_EL1", "TCR2_EL2", "TCR2_EL12" }, { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), @@ -7892,6 +7894,62 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 +static CPAccessResult tcr2_el2_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_TCR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult tcr2_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= { + return CP_ACCESS_TRAP_EL2; + } + return tcr2_el2_access(env, ri, isread); +} + +static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* This register does not control any feature yet. */ +} + +static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo tcr2_reginfo[] =3D { + { .name =3D "TCR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, + .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, + { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D tcr2_el2_access, + .writefn =3D tcr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9164,6 +9222,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, sctlr2_reginfo); } =20 + if (cpu_isar_feature(aa64_tcr2, cpu)) { + define_arm_cp_regs(cpu, tcr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index d18d0fb19a..8cb0709abe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -201,6 +201,24 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +#define TCR2_PNCH (1ULL << 0) +#define TCR2_PIE (1ULL << 1) +#define TCR2_E0POE (1ULL << 2) +#define TCR2_POE (1ULL << 3) +#define TCR2_AIE (1ULL << 4) +#define TCR2_D128 (1ULL << 5) +#define TCR2_PTTWI (1ULL << 10) +#define TCR2_HAFT (1ULL << 11) +#define TCR2_AMEC0 (1ULL << 12) +#define TCR2_AMEC1 (1ULL << 13) +#define TCR2_DISCH0 (1ULL << 14) +#define TCR2_DISCH1 (1ULL << 15) +#define TCR2_A2 (1ULL << 16) +#define TCR2_FNG0 (1ULL << 17) +#define TCR2_FNG1 (1ULL << 18) +#define TCR2_FNGNA0 (1ULL << 20) +#define TCR2_FNGNA1 (1ULL << 21) + FIELD(VTCR, T0SZ, 0, 6) FIELD(VTCR, SL0, 6, 2) FIELD(VTCR, IRGN0, 8, 2) @@ -232,6 +250,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 30505fb293..ae2046a7f6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1248,6 +1248,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); --=20 2.34.1 From nobody Fri Dec 19 22:05:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752181924; cv=none; d=zohomail.com; s=zohoarc; b=Dert0BesGzjvbQVut8b/vzKXP81DB6mJCfjR9E7lmR/H3DbSNVrp7uqu53O6aNvsMv6xu5k0Cy5VONfNh/gJX274K2ko43zecbjesKR96cl8VjPrS/f3Qj6Zshe4Dq1omTeapacp352w2SCEaeH/yBBEjgH3ZhPx1WolnTLbZYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752181924; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[189.47.46.41]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de434d6b0sm30447775ad.203.2025.07.10.14.11.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 14:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752181864; x=1752786664; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=24pxxDuWEZzb6wGY252RDxtIpjDwPD+IPgiDjqz1YEk=; b=X1Z9YOEVJfzdFQuge4oO9eNx4hl8I7Juj7Uqr2wF1jKzo3+EOxBDoYf3Pp9ZpX3UyJ hhhP9LbKpKR92HGRqg0787l7uuFpUfObPGxrT2sy0VN+SNBwVV6QeyXOxswveNrEky1C 3SI4kLy1/wkc9b7SdAp3FVWiyuu4+lW5uye3CpXMZ36ROfU1L3xabCmvkKT9glqf72Rv Gt0QMzAsd7T7JOkQ2dlOGUldKqTM/9KI0hNtQZkf+wNIqW/TRfwoAtZ5lm6R/F+E1HYJ ksZysUlEhqW+8s9QvwhYiDEgx2YrhKodmddYOwPQ9Ji0uIZpbNCSWsy03KwfDNYKegbu UyQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752181864; x=1752786664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=24pxxDuWEZzb6wGY252RDxtIpjDwPD+IPgiDjqz1YEk=; b=IW8Oc/Q5jmhEDHyLksd8/9C121o/FQpeHVkq6RmpoFZS/Ux9uVbR2FfbLVgGP+E2SM bxZe/Y0xluQZJfVJXiCJdpooHQz34g5eFhrwC37mwCjeq8MHuAH1fA37AfKW3fsLgoHM XeOoQ04kxn0Pd072YF+v0wtYX8h5FoaS/PA59R3llax3YGkyTIt1zCujGFMJGu5YruDR qBeDmtZO1+lwUOC6yKUyXMWDOKZMt0LJG4mpBv/siuWBX0Itj83oYzhKAiwBLGDN03wb uUIKtqHpxxg33vCXksDjTvK2KqBtoh1H1pN4wxK9nyaK3lB+17Uk0JLfeqE/8hRcu/V7 fVCw== X-Gm-Message-State: AOJu0YzQEeAIMPBGGKGrtZifnIvy3SmieWShcnBZz8vCvKwyXhJy0Muf rTProUukA1tRjGmyjwrBkUOXbH1uHVGE2fZ9lPlktv8VA0fb7rT/WMtDW7wdfbm/xCc= X-Gm-Gg: ASbGnctPa7hErXx+MywBEYedPQ38kR7x84ZZHcOjq8nS8ogkys0rifyn4KNhrD9KKkl wk94DU+raBZZ5LeFpZjj6K0tDTDdYtJvMzb4lkR+BRCWRmzSZx9cMeHSDURVtZcPhhb6vIEL/Qk rn+aezc0Kovobep557gzencs2ExRRdDyX04kaHPO9e3+NdIfHd9ZJj+bBPEHqK0gYxeoPPhIknb gRwSPTt7HryyFH5MeElxyfhsZrac5stMpRHd4wiFp9ycBbwkhhd5yfuh9X3YyiY0IUIosiKMZFB MtKoaL/OOK1ZRtKPG1N2rzBGNQVeJwm2r16HeCBaPA0yTA2tlJYWtwWY5GtHrFBrTNPmwAMLBOs us18l2bO9IWBe8DXS/67C9uT41z5UghFo/2IwBXA59BQxxhQQFrx4ut6fyg== X-Google-Smtp-Source: AGHT+IHmpIsk/2hGSYFiR/Bc3drCbCerDeMpmxZJw04YjfLwK1jehup3Cu6ee9OVmiYhlEZfx/6Tlg== X-Received: by 2002:a17:903:1b63:b0:235:caa8:1a72 with SMTP id d9443c01a7336-23dede81dc8mr9636535ad.30.1752181863928; Thu, 10 Jul 2025 14:11:03 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v6 5/6] target/arm: Implement FEAT_MEC cache instructions Date: Thu, 10 Jul 2025 21:09:40 +0000 Message-Id: <20250710210941.1098088-6-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710210941.1098088-1-gustavo.romero@linaro.org> References: <20250710210941.1098088-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752181926152116600 Content-Type: text/plain; charset="utf-8" This commit implements the two cache maintenance instructions introduced by FEAT_MEC, DC CIPAE and DC CIGDPAE. Because QEMU does not model the cache topology, all cache maintenance instructions are implemented as NOPs, hence these new instructions are implemented as NOPs too. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index ecfd53cc5a..c030f0a0da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6856,6 +6856,18 @@ static void mecid_write(CPUARMState *env, const ARMC= PRegInfo *ri, raw_write(env, ri, value); } =20 +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + static const ARMCPRegInfo mec_reginfo[] =3D { { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, @@ -6895,6 +6907,15 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D mecid_access, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, }; =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9216,6 +9237,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (cpu_isar_feature(aa64_mec, cpu)) { define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } } =20 if (cpu_isar_feature(aa64_sctlr2, cpu)) { --=20 2.34.1 From nobody Fri Dec 19 22:05:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752182023; cv=none; d=zohomail.com; s=zohoarc; b=PIb3fi4UqCKdpjBa4DPNYf5ZkOuvqELfe5wsj+A3H/KYL4hWuM0KDWw1moE8rxH0Q8/UQm2DEOtkh1a0uUrwB9aC0axVO5c9sdn5EZo4ftbzewdKB+Y2YA/A+T41eObqf2gnHIjEbvJ3anEBaI9VxY1lxA64rjkycYUPfcENKxQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752182023; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XxglZr9FSbfBVmHLZ+FvVDfQKN3fWf8b03y6OHhLFac=; b=OJxcF/ylmjw5qeLOFuUvHLhzgfO4KjjqH5r1/qkmG3DtNaDwZowombInt0QhoZD1Kua8jKr7QlUajsuXUif83tfOyugQDat0t6z3IqNOM/Si2jo4i90IAF5rCcPDzEcFb8oVo+d2+J+JoJEp8IXSxgaHQPIELnbLUKxUh5HMnxs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752182023153599.5652278078462; Thu, 10 Jul 2025 14:13:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZyXy-0000Z7-6X; Thu, 10 Jul 2025 17:11:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZyXs-0000XL-Vq for qemu-devel@nongnu.org; Thu, 10 Jul 2025 17:11:10 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uZyXr-0006eR-Co for qemu-devel@nongnu.org; Thu, 10 Jul 2025 17:11:08 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-23aeac7d77aso14047725ad.3 for ; Thu, 10 Jul 2025 14:11:07 -0700 (PDT) Received: from gromero0.. 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[189.47.46.41]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de434d6b0sm30447775ad.203.2025.07.10.14.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 14:11:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752181866; x=1752786666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XxglZr9FSbfBVmHLZ+FvVDfQKN3fWf8b03y6OHhLFac=; b=S2ubFhecNrlcE0wHvzSd++yXvrycuf426RKI3nyvqXRxAJO+rp10BunaJO3R6CbvLJ 5iRLSMhsHbhAUhJ5ErlhM2AL7OwNa0eoxwgTdO0c3lW0ypnK0ubyAQirEeK1H79rpGbd iXcQDAxy0LYW87ouBC5Fy7GHhO1ygSHHjWqk9Mc3C2l2nOpSN7yTgjHYZCpuoBNmTfEr ZyhTyqVCs2a8C643FZKoSAn1IBFkxpHXAqw0q7s2mZ3lNbK201jOOVV8wxPhW/OkVLuz eR3NkZhvqhfcF4uf5e+bUPVC6UKWqzoFBpXBn0mMRQHkmiAFh7E4KinellZyMhFC2MWM AbbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752181866; x=1752786666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XxglZr9FSbfBVmHLZ+FvVDfQKN3fWf8b03y6OHhLFac=; b=LSA1FATAu08MbSiubhLpdom9PjFLQoDexQhsVPjbyFtNeeJvBLyt2FJ8iNdjwP5PlR 3JlAnB1c/a/axCHoRNK6yR0wd/BFIWl3XqpuI29WS8/wQrdOQeL6xPcSmfsXxny9lska SpE8CNzxNJ2k437jdZ3nsJM3Sl4RbXVJQPWD/yAwuBkb9M6uqUJnW4qrNFe7cR9q7YQ9 LSNbywN0p9ZLqqp/rc8E55t962mQYJf+lvNKouIOeEjfDvK+renIFooEws899DIF3AI9 qoJFP9EI2Ba4WXWKheKRBzyniCC/T4C2uYhmUE4oDERCbUucTu/lDXQNbXAASRuXmXaU v4qA== X-Gm-Message-State: AOJu0YwVgL9mvgiBsFYyBNnkoXRHrsqMgcGTqJtkZvT2saFUa5hjc3nO UTGA3c7Fjcc3dsw23q8TCQWjP5fRrcDH38E5TLUD2W+qGSvq0xraTTQaYR5Vqu4CpYE= X-Gm-Gg: ASbGncv8wfh8go9uC8IGVPpZweg3xGHefI5I+cPIiMrZlGB0Gx9M7DUXJ/Ifjps3H09 Tn0b8O2tpLd/DOBAELF6TWGt2SSFFI7FSPzYjzFYqfLx8XpWjFSxzZ3Yz6vrxugbwNub55wdh6L 7sCFZV/4LCHUOFYVcKiIYCaa+OP46+UCnf3ub1NGvmbn8XN0tCL6Y9Ul750vIuKM46e/s4djTX7 5XRCoGKmbagj9fOxZ8v+FK2K3FV4X0C/HBcrvjYYYf764zRJ4k4AwR6RVoOaypg2DT4bb3Ya+lG AvifutYAV1ByyTbCn41U7IOL9DbHjS5mTlxu8869ChKzoHw0ayCN7VWZ4FKAQAnLuimoNiYTXhH I0f6/KYNRPzxtjaI4QgQ4CAReAVCA84lEqY2b79GfTkrxYiF1+1ymmjMm0g== X-Google-Smtp-Source: AGHT+IGRi/54l7dYMIvw7MZjU0TCT2MYW3MaMAMb7gvme9jACt4mMt+PGVFnwDgSGyEgz79DhyRmOg== X-Received: by 2002:a17:903:2f85:b0:235:f45f:ed53 with SMTP id d9443c01a7336-23dede8914fmr9118495ad.33.1752181865996; Thu, 10 Jul 2025 14:11:05 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v6 6/6] target/arm: Advertise FEAT_MEC in cpu max Date: Thu, 10 Jul 2025 21:09:41 +0000 Message-Id: <20250710210941.1098088-7-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710210941.1098088-1-gustavo.romero@linaro.org> References: <20250710210941.1098088-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752182024927116600 Content-Type: text/plain; charset="utf-8" Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a first step to fully support FEAT_MEC. The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption is supported, but software stacks that rely on FEAT_MEC to run should work properly. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 3 +++ target/arm/tcg/cpu64.c | 1 + 2 files changed, 4 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 1c597d8673..d207a9f266 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -89,6 +89,9 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) + + * This is a register-only implementation without encryption. - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ae2046a7f6..1b9b6475b6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1250,6 +1250,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D GET_IDREG(isar, ID_AA64MMFR3); t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 --=20 2.34.1