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[189.47.46.41]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9f5c7f7sm2919119b3a.142.2025.07.10.09.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:41:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752165703; x=1752770503; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EtG2f9WC1Atw8TQNXmdprkNhtZEEPjSXEDq2fJcwOt8=; b=GwPLV3Q/rZ9Cbu4lb7Yf8vjhid6+I85E60uT1f8q56ih4skErpCn3N9pIs6IaJHt9v HvzUIyZkYvVf+Lwn8hr7oyLQmnmyDimPQY1XyP4XMlteVMls5G9/QDlU6B8H1Ta+Bcsj XJmOf1PBAYpBDmyTvH/LF0O2OU652C3m7kDzIRwGmYhuhYIV4a1aSjxMrSQG1AI91LHI qSw7qxRo30cIpqGiSwHRmkfVe44njHxk+plfscCvJfBd0xqrMqiKVd91chkfaoanz9ln glWDS+afrBk3C+i1RyxsuIMu05u59NwMW7yUoxIN7G/p1Ckuv4XPhP7wzNfp6NVqbY87 KZDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752165703; x=1752770503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EtG2f9WC1Atw8TQNXmdprkNhtZEEPjSXEDq2fJcwOt8=; b=V+ES+i6U6wGUkJ6z75ScUGC3ZQUXLhJUqa4/fnrOE+wHTsh3sWTTcd7CHudDbZuJX9 Ph2Z/aHrom90u+yImdh8cRfVKPWiGXS7Z9JJol9pgKOG7sn4RM4i1WpnzqVuIUr/lKsI oUwyhhMadqkXSOWGkS0NHeTSBbkyvCth+Qt8IJE8C/dqaC9BgT1bCHHjndGFqQB08+8z h53GM9L9nli8N9zQzQLCmUvnicZtQzFNJ7Hdtse4aN6i4CynasynHOtmMucSHBHRdiLz J8mRHh8YVbBrxisInCNSpZqbZIs2V8ErnqnD2/XqJVyNBlqoSI4KVwS2X62JTkEzvNX+ Qxvw== X-Gm-Message-State: AOJu0Yy1jEJBEA3y0Nhhr3sod2x/LuYjA4fN4fc917o2Ctj+7PQus4oP wVbJ+Fe4H1wo80WOUvuv+3/bqzyujK/U0TgyairC+pCfkXVG9nD+K12P07U5hXCfnVGApWRgH6n hgEL1r7E= X-Gm-Gg: ASbGncuJG94v8IyvyGUoe19ZHzNjNSt2qTztt7DlKuXJJi0eiyFwKxkOCiAlruURQvo ncCSViUg9SovaQrP5sfgk1yzF9ZXPPpC+Utldgcv6JOkg0Z62Vju+5Vs5BnsQRxQQCIVKRm3sPa ui+25qLnR37xw+D2+MrhAg2nEhLRGBo7CWsOVeTNoGinA0p0gAYuS6GZ2UMyytWk2hNfkKH4F9q JTDTRUiD24d4uHXcFy04TyvA00bCydTTE/H4TUvFyk9ilH9denit5Arv/m66MaWTiEJvhrkjNqh KbpU/3ns3xN8Wh1tdbO8oGCBGgycvvt2TPgQMbf9zfUd9p4rkcGTuL9BUPyfstPrAy8TPLSAGLG ov/xfJ2lblYPF5NdnA4WADA== X-Google-Smtp-Source: AGHT+IHn1M2Zub3MC32lkJYROXXoTEHubfXaq7lyDHdIYsD9Wee9Wfhu6jFBx47GkXNAiDl+skUzcA== X-Received: by 2002:a05:6a20:430c:b0:215:e02f:1eb8 with SMTP id adf61e73a8af0-22fc38bcf9cmr6743105637.14.1752165703233; Thu, 10 Jul 2025 09:41:43 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v5 5/6] target/arm: Implement FEAT_MEC cache instructions Date: Thu, 10 Jul 2025 16:38:58 +0000 Message-Id: <20250710163858.1094780-6-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710163858.1094780-1-gustavo.romero@linaro.org> References: <20250710163858.1094780-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752167121098116600 Content-Type: text/plain; charset="utf-8" This commit implements the two cache maintenance instructions introduced by FEAT_MEC, DC CIPAE and DC CIGDPAE. Because QEMU does not model the cache topology, all cache maintenance instructions are implemented as NOPs, hence these new instructions are implemented as NOPs too. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f678aceeb..5aab9294bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6856,6 +6856,18 @@ static void mecid_write(CPUARMState *env, const ARMC= PRegInfo *ri, raw_write(env, ri, value); } =20 +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + switch (arm_security_space(env)) { + case ARMSS_Root: /* EL3 */ + case ARMSS_Realm: /* Realm EL2 */ + return CP_ACCESS_OK; + default: + return CP_ACCESS_UNDEFINED; + } +} + static const ARMCPRegInfo mec_reginfo[] =3D { { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, @@ -6895,6 +6907,15 @@ static const ARMCPRegInfo mec_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D mecid_access, .writefn =3D mecid_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, +}; + +static const ARMCPRegInfo mec_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, }; =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9212,6 +9233,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 if (cpu_isar_feature(aa64_mec, cpu)) { define_arm_cp_regs(cpu, mec_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mec_mte_reginfo); + } } =20 if (cpu_isar_feature(aa64_sctlr2, cpu)) { --=20 2.34.1