From nobody Thu Dec 18 22:52:34 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752166774; cv=none; d=zohomail.com; s=zohoarc; b=iipGn7cOxyWt1NHFoOUZU25Z7fVifpOP/6n6el8Gpz6i4/PamLWbrsS0peva/bLDaKMlY76W3fPvhMGvVSeolEBlZKMsP8f1WgoiPnc+zbEYtJfeUWp+e1oRBHz/pQT21hfyku8m2T7vQTOkEntNnbVHUTLtpcCRWocouLsSi5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752166774; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FS5xA6GOc2Mt9sYqT6zR9mXdzFYKOmV3kMN80l8IgKM=; b=RwIDh2uyQZ43cj+uFqTyi7Dl2A8lafQ0C4Htsf0aRjrPsAzhHzkImkwp4kjmzRx1OFWQGw1ZiaSRxxK7d1+Jnw4ltdU+BLes+YXZqzkGubKOiGYQqPoUm+H9wUWlMJoVspC8DwELHY++vTOx/VICQCfTOLGF8O7Dovma0R66m1o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752166774272314.9667646078616; Thu, 10 Jul 2025 09:59:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZub4-0007XF-Ge; Thu, 10 Jul 2025 12:58:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZuL9-0003vK-4O for qemu-devel@nongnu.org; Thu, 10 Jul 2025 12:41:44 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uZuL6-00019M-T3 for qemu-devel@nongnu.org; Thu, 10 Jul 2025 12:41:42 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-74b56b1d301so800079b3a.1 for ; Thu, 10 Jul 2025 09:41:40 -0700 (PDT) Received: from gromero0.. (189-47-46-41.dsl.telesp.net.br. [189.47.46.41]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9f5c7f7sm2919119b3a.142.2025.07.10.09.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:41:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752165699; x=1752770499; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FS5xA6GOc2Mt9sYqT6zR9mXdzFYKOmV3kMN80l8IgKM=; b=s8kEZrMQyMua+nbs2Rh8xK2xPHgeO3EnD1/SF+FVoEMp+eGoOiA5BPhphJbJ58cFi6 fhftWCE1kYZaRaN5j+3czWBvIf+YAKiP4/zaREkyHIcHc1yPDhiA7n0qJ7RVFkrmV7M7 51TKedG34Mtgm+7MZV78FVCkQwZcxmOQpABR8W55Z8wtVqPz00G6dXxNeY5Yx+hbyani 91pb5BOVzpXj2bFR+Yop8DMw0jS3yiubcK8KlWUa7OFtGj4KRmvlMQCYYIP4+2sOOv1f 6FeW/L7ri/HRdFkqgSwd1kljsTc/wZI642kruu6smpM4LWTMle8y9wCRaGO0lzXHNxt3 Ykkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752165699; x=1752770499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FS5xA6GOc2Mt9sYqT6zR9mXdzFYKOmV3kMN80l8IgKM=; b=XRSOju7vknsU2TdnWxMhzP+j9idpJrKxkYPGRXAM9QXDNCkvHmMv1HY8ZS+k60HwDI IQ2S4zfMvY3+wqdmVMnMctCP8k2k8H4OvvYhnVZ2UBoQ1lYr+IhXlNmgRiVhU1TpOHVv fYcpipi2PxJTikKhyINvHPFMPR5WAO+y9wtQ/dXGzX51EFMuuNFsr29FB9ctqvS0Uyli 18AbteQ6HHj0iUWbpI8GLY/DLFKUxTPWP2BuHc89qDI6YsnGQX2fcY1PzJJD4XHSk/iF K7WA3WOR1oXTV3DJQx8Ry3rSt51GATEnj4Zoyu1lS++sMkKrWJXptibDC/vYJHx0hvoT 5B9A== X-Gm-Message-State: AOJu0YzrwuRyUF2VGwyfeXWJdBJGfufi2N1mQ033OIEDNVoDNI/hK5qH MoS+kz5VJbalbeOiirUPbY7cpGU2b3DGTO/ZzAOwNo5kqw6cg0OxAqTN1GzYR9mGg0o= X-Gm-Gg: ASbGnctuOe9drjtoulaGgtUNqt1pfoNeVMXb3Dduodr78/g6ernOjt3NQzLIgxo1KLZ KXuMXnOy8iOpOnR3z0pJF3tA19zRwBS4AjFnqEPj7fef2UiKqvvsq9ybffjDi5i0Dhw8grKKlk1 iYCjQfyB09C+UKz1zgL1e+LO457i2cwDQAfXGLmyZp0yG5mdzkGay6J034qxAyZ99/P63SuCw2F GH6ya0u/IPfhOQGtGhjJk0FMECc8R+OQPKlprF10RLej+iH0YCSUb5QMQu8wtSid3fDVyATyOA1 vhoHpnUy1Pc7YYLLl+hub8xIjbG0ndqOiT/GVY46GrmgX6XxROLUSkNpVIamLOWgQyxp7WLfWJw VQB1HspLMaB/h3xCSeVhQYeJ/frxQLozA X-Google-Smtp-Source: AGHT+IG9hd28Qk2FKfz9fuFpLyvK5eIum7E22ZmTwwdApiQ7I4pUjoAw5b6XsTe3B/tT76j1gZlo2w== X-Received: by 2002:aa7:88c6:0:b0:732:2923:b70f with SMTP id d2e1a72fcca58-74eb8f7c139mr4584567b3a.11.1752165699076; Thu, 10 Jul 2025 09:41:39 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v5 3/6] target/arm: Add FEAT_SCTLR2 Date: Thu, 10 Jul 2025 16:38:56 +0000 Message-Id: <20250710163858.1094780-4-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710163858.1094780-1-gustavo.romero@linaro.org> References: <20250710163858.1094780-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=gustavo.romero@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752166775520116600 Content-Type: text/plain; charset="utf-8" Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Because the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, this commit only implements the EMEC bits in CTLR2_EL2 and SCTLR2_EL3. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 15 +++++++ target/arm/helper.c | 78 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/tcg/cpu64.c | 5 ++- 6 files changed, 104 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 890dc6fee2..66043b0747 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 72b6fd9b27..a5fc2ca572 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 40ca093331..894e2a2997 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -337,6 +337,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1433,6 +1434,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8 /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1725,6 +1739,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/helper.c b/target/arm/helper.c index 984406c945..963d3e064b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6144,6 +6144,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), + "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12" }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), "CPACR", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), @@ -7816,6 +7818,78 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_el2_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult sctlr2_el1_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_SCTLR2EN= )) { + return CP_ACCESS_TRAP_EL2; + } + return sctlr2_el2_access(env, ri, isread); +} + +static void sctlr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* This register does not control any feature yet. */ +} + +static void sctlr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, + .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_el2_access, + .writefn =3D sctlr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9084,6 +9158,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mec_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 77ba2a2273..d18d0fb19a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -232,6 +232,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d0df50a2f3..30505fb293 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,7 +1247,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 - FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ --=20 2.34.1