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Thu, 10 Jul 2025 14:43:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20250714130420epoutp0276b9ccff4508ebe64f11d9512e602fec~SH_Hp9yOi3013930139epoutp02T DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1752498260; bh=pqdmardhYLbgukB+gPoJmX2cMN4AhVUGeaD4ZeYNo+0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rwwKhN0AlgXXfeHhwfx1BhpT0L4jSHdNxIxaRpOMI6WKP7w7nu1tiDI5rH67m+2NP 8SSoUCD6h+dQQl2XFq6kZgasPKkbbCVcrQeG1wRqivS7QpCmKR4Afu9VkMs9HhR8Ag Ye9eJO5OB3nprzpYmTb2IweQkka3WiAqve/hzNG8= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, Jonathan.Cameron@huawei.com, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, cpgs@samsung.com, Arpit Kumar Subject: [PATCH v2 2/2] hw/cxl: Add Physical Port Control (Opcode 5102h) Date: Thu, 10 Jul 2025 20:13:38 +0530 Message-Id: <20250710144338.2839512-3-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710144338.2839512-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250710144358epcas5p1bf06af9ee56880a24421a2f7a7d6c113 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250710144358epcas5p1bf06af9ee56880a24421a2f7a7d6c113 References: <20250710144338.2839512-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.25; envelope-from=arpit1.kumar@samsung.com; helo=mailout2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1752504155773116600 -added assert-deassert PERST implementation for physical ports (both USP and DSP's). -assert PERST involves bg operation for holding 100ms. -reset PPB implementation for physical ports. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 135 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 10 +++ 2 files changed, 145 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index c4e83fb2aa..3aa8bd14b9 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -118,6 +118,7 @@ enum { PHYSICAL_SWITCH =3D 0x51, #define IDENTIFY_SWITCH_DEVICE 0x0 #define GET_PHYSICAL_PORT_STATE 0x1 + #define PHYSICAL_PORT_CONTROL 0X2 TUNNEL =3D 0x53, #define MANAGEMENT_COMMAND 0x0 MHD =3D 0x55, @@ -605,6 +606,121 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 +static void *bg_assertcb(void *opaque) +{ + struct pperst *perst =3D opaque; + + /* holding reset phase for 100ms */ + while (perst->asrt_time--) { + usleep(1000); + } + perst->issued_assert_perst =3D true; + return NULL; +} + +static CXLRetCode deassert_perst(Object *obj, uint8_t pn, CXLUpstreamPort = *pp) +{ + if (!pp->pports.perst[pn].issued_assert_perst) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock); + resettable_release_reset(obj, RESET_TYPE_COLD); + pp->pports.perst[pn].issued_assert_perst =3D false; + pp->pports.pport_info[pn].link_state_flags &=3D + ~LINK_STATE_FLAG_PERST_ASSERTED; + pp->pports.perst[pn].asrt_time =3D ASSERT_WAIT_TIME_MS; + + return CXL_MBOX_SUCCESS; +} + +static CXLRetCode assert_perst(Object *obj, uint8_t pn, CXLUpstreamPort *p= p) +{ + if (pp->pports.perst[pn].issued_assert_perst || + pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) { + return CXL_MBOX_INTERNAL_ERROR; + } + + QEMU_LOCK_GUARD(&pp->pports.perst[pn].lock); + pp->pports.pport_info[pn].link_state_flags |=3D + LINK_STATE_FLAG_PERST_ASSERTED; + resettable_assert_reset(obj, RESET_TYPE_COLD); + qemu_thread_create(&pp->pports.perst[pn].asrt_thread, "assert_thread", + bg_assertcb, &pp->pports.perst[pn], QEMU_THREAD_DETACHED); + + return CXL_MBOX_SUCCESS; +} + +static struct PCIDevice *cxl_find_port_dev(uint8_t pn, CXLCCI *cci) +{ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + + if (pp->pports.pport_info[pn].current_port_config_state =3D=3D + CXL_PORT_CONFIG_STATE_USP) { + PCIDevice *usp_dev =3D pci_bridge_get_device(bus); + return usp_dev; + } + + if (pp->pports.pport_info[pn].current_port_config_state =3D=3D + CXL_PORT_CONFIG_STATE_DSP) { + PCIDevice *dsp_dev =3D pcie_find_port_by_pn(bus, pn); + return dsp_dev; + } + return NULL; +} + +/* CXL r3.2 Section 7.6.7.1.3: Get Physical Port Control (Opcode 5102h) */ +static CXLRetCode cmd_physical_port_control(const struct cxl_cmd *cmd, + uint8_t *payload_in, + size_t len_in, + uint8_t *payload_out, + size_t *len_out, + CXLCCI *cci) +{ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + PCIDevice *dev; + uint8_t ret =3D CXL_MBOX_SUCCESS; + + struct cxl_fmapi_get_physical_port_control_req_pl { + uint8_t ppb_id; + uint8_t ports_op; + } QEMU_PACKED *in =3D (void *)payload_in; + + if (len_in < sizeof(*in)) { + return CXL_MBOX_INVALID_PAYLOAD_LENGTH; + } + + uint8_t pn =3D in->ppb_id; + if (pp->pports.pport_info[pn].port_id !=3D pn) { + return CXL_MBOX_INTERNAL_ERROR; + } + + dev =3D cxl_find_port_dev(pn, cci); + if (!dev) { + return CXL_MBOX_INTERNAL_ERROR; + } + + switch (in->ports_op) { + case 0: + ret =3D assert_perst(OBJECT(&dev->qdev), pn, pp); + break; + case 1: + ret =3D deassert_perst(OBJECT(&dev->qdev), pn, pp); + break; + case 2: + if (pp->pports.perst[pn].issued_assert_perst || + pp->pports.perst[pn].asrt_time < ASSERT_WAIT_TIME_MS) { + return CXL_MBOX_INTERNAL_ERROR; + } + device_cold_reset(&dev->qdev); + break; + default: + return CXL_MBOX_INVALID_INPUT; + } + return ret; +} + /* CXL r3.1 Section 8.2.9.1.2: Background Operation Status (Opcode 0002h) = */ static CXLRetCode cmd_infostat_bg_op_sts(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -3579,7 +3695,11 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max) =20 void cxl_destroy_cci(CXLCCI *cci) { + CXLUpstreamPort *pp =3D CXL_USP(cci->d); qemu_mutex_destroy(&cci->bg.lock); + for (int i =3D 0; i < CXL_MAX_PHY_PORTS; i++) { + qemu_mutex_destroy(&pp->pports.perst[i].lock); + } cci->initialized =3D false; } =20 @@ -3798,6 +3918,8 @@ static const struct cxl_cmd cxl_cmd_set_usp_mctp[256]= [256] =3D { cmd_identify_switch_device, 0, 0 }, [PHYSICAL_SWITCH][GET_PHYSICAL_PORT_STATE] =3D { "SWITCH_PHYSICAL_PORT= _STATS", cmd_get_physical_port_state, ~0, 0 }, + [PHYSICAL_SWITCH][PHYSICAL_PORT_CONTROL] =3D { "SWITCH_PHYSICAL_PORT_C= ONTROL", + cmd_physical_port_control, 2, 0 }, [TUNNEL][MANAGEMENT_COMMAND] =3D { "TUNNEL_MANAGEMENT_COMMAND", cmd_tunnel_management_cmd, ~0, 0 }, }; @@ -3810,4 +3932,17 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceS= tate *d, DeviceState *intf, cci->intf =3D intf; cxl_init_cci(cci, payload_max); cxl_set_phy_port_info(cci); + /* physical port control */ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + for (int i =3D 0; i < CXL_MAX_PHY_PORTS; i++) { + qemu_mutex_init(&pp->pports.perst[i].lock); + pp->pports.perst[i].issued_assert_perst =3D false; + /* + * Assert PERST involves physical port to be in + * hold reset phase for minimum 100ms. No other + * physcial port control requests are entertained + * until Deassert PERST command. + */ + pp->pports.perst[i].asrt_time =3D ASSERT_WAIT_TIME_MS; + } } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 1fa6cf7536..bb47e671eb 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -128,6 +128,7 @@ (1 << 16)) =20 #define CXL_MAX_PHY_PORTS 256 +#define ASSERT_WAIT_TIME_MS 100 /* Assert - Deassert PERST */ =20 #define LINK_STATE_FLAG_LANE_REVERSED BIT(0) #define LINK_STATE_FLAG_PERST_ASSERTED BIT(1) @@ -203,10 +204,19 @@ struct cxl_phy_port_info { uint8_t supported_ld_count; } QEMU_PACKED; =20 +/* Assert - Deassert PERST */ +struct pperst { + bool issued_assert_perst; + QemuMutex lock; + uint64_t asrt_time; + QemuThread asrt_thread; /* thread for 100ms delay */ +}; + struct phy_port { uint8_t num_ports; uint8_t active_port_bitmask[0x20]; struct cxl_phy_port_info pport_info[CXL_MAX_PHY_PORTS]; + struct pperst perst[CXL_MAX_PHY_PORTS]; }; =20 /* CXL r3.1 Table 8-34: Command Return Codes */ --=20 2.34.1