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Thu, 10 Jul 2025 14:43:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20250714130414epoutp0180fc5e1e1c3e13e606994797e450e470~SH_CPOxKi2247922479epoutp01W DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1752498254; bh=wexRdYSX/POQW9r6xMlSyrNroYododbW5ywT6p75eSM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kx2k9/QYRxH1akQiK5bspsHQFnC3vdakMwTeLldNGMVZyawjYoagTEQAZUAnl7nFo 0mPTxKRNKpIPjQn/JtxqBLASLDbxlpa2FhQI03P/0aNusLyeV02RkVdXFj8om5uzyF VZpu/afiCa5o0+54niAjMT3t8+VlhbFb121U62FQ= From: Arpit Kumar To: qemu-devel@nongnu.org Cc: gost.dev@samsung.com, linux-cxl@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, Jonathan.Cameron@huawei.com, vishak.g@samsung.com, krish.reddy@samsung.com, a.manzanares@samsung.com, alok.rathore@samsung.com, cpgs@samsung.com, Arpit Kumar Subject: [PATCH v2 1/2] hw/cxl: Refactored Identify Switch Device & Get Physical Port State Date: Thu, 10 Jul 2025 20:13:37 +0530 Message-Id: <20250710144338.2839512-2-arpit1.kumar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710144338.2839512-1-arpit1.kumar@samsung.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250710144354epcas5p46a083b743de04f5849e3449a4d9dfe87 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250710144354epcas5p46a083b743de04f5849e3449a4d9dfe87 References: <20250710144338.2839512-1-arpit1.kumar@samsung.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.254.224.24; envelope-from=arpit1.kumar@samsung.com; helo=mailout1.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @samsung.com) X-ZM-MESSAGEID: 1752504192356116600 -Storing physical ports info during enumeration. -Refactored changes using physical ports info for Identify Switch Device (Opcode 5100h) & Get Physical Port State (Opcode 5101h) physical switch FM-API command set. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c | 229 ++++++++++++---------- include/hw/cxl/cxl_device.h | 82 ++++++++ include/hw/pci-bridge/cxl_upstream_port.h | 4 + 3 files changed, 207 insertions(+), 108 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index a02d130926..c4e83fb2aa 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -500,16 +500,6 @@ static CXLRetCode cmd_set_response_msg_limit(const str= uct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } =20 -static void cxl_set_dsp_active_bm(PCIBus *b, PCIDevice *d, - void *private) -{ - uint8_t *bm =3D private; - if (object_dynamic_cast(OBJECT(d), TYPE_CXL_DSP)) { - uint8_t port =3D PCIE_PORT(d)->port; - bm[port / 8] |=3D 1 << (port % 8); - } -} - /* CXL r3.1 Section 7.6.7.1.1: Identify Switch Device (Opcode 5100h) */ static CXLRetCode cmd_identify_switch_device(const struct cxl_cmd *cmd, uint8_t *payload_in, @@ -518,9 +508,8 @@ static CXLRetCode cmd_identify_switch_device(const stru= ct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - PCIEPort *usp =3D PCIE_PORT(cci->d); - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - int num_phys_ports =3D pcie_count_ds_ports(bus); + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + uint8_t num_phys_ports =3D pp->pports.num_ports; =20 struct cxl_fmapi_ident_switch_dev_resp_pl { uint8_t ingress_port_id; @@ -537,11 +526,11 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, =20 out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl *)payload_out; *out =3D (struct cxl_fmapi_ident_switch_dev_resp_pl) { - .num_physical_ports =3D num_phys_ports + 1, /* 1 USP */ + .num_physical_ports =3D num_phys_ports, .num_vcss =3D 1, /* Not yet support multiple VCS - potentially tri= cky */ .active_vcs_bitmask[0] =3D 0x1, - .total_vppbs =3D num_phys_ports + 1, - .bound_vppbs =3D num_phys_ports + 1, + .total_vppbs =3D num_phys_ports, + .bound_vppbs =3D num_phys_ports, .num_hdm_decoders_per_usp =3D 4, }; =20 @@ -553,16 +542,14 @@ static CXLRetCode cmd_identify_switch_device(const st= ruct cxl_cmd *cmd, out->ingress_port_id =3D 0; } =20 - pci_for_each_device_under_bus(bus, cxl_set_dsp_active_bm, - out->active_port_bitmask); - out->active_port_bitmask[usp->port / 8] |=3D (1 << usp->port % 8); - + memcpy(out->active_port_bitmask, pp->pports.active_port_bitmask, + sizeof(pp->pports.active_port_bitmask)); *len_out =3D sizeof(*out); =20 return CXL_MBOX_SUCCESS; } =20 -/* CXL r3.1 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ +/* CXL r3.2 Section 7.6.7.1.2: Get Physical Port State (Opcode 5101h) */ static CXLRetCode cmd_get_physical_port_state(const struct cxl_cmd *cmd, uint8_t *payload_in, size_t len_in, @@ -570,44 +557,22 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, size_t *len_out, CXLCCI *cci) { - /* CXL r3.1 Table 7-17: Get Physical Port State Request Payload */ + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + size_t pl_size; + int i; + + /* CXL r3.2 Table 7-17: Get Physical Port State Request Payload */ struct cxl_fmapi_get_phys_port_state_req_pl { uint8_t num_ports; uint8_t ports[]; } QEMU_PACKED *in; =20 - /* - * CXL r3.1 Table 7-19: Get Physical Port State Port Information Block - * Format - */ - struct cxl_fmapi_port_state_info_block { - uint8_t port_id; - uint8_t config_state; - uint8_t connected_device_cxl_version; - uint8_t rsv1; - uint8_t connected_device_type; - uint8_t port_cxl_version_bitmask; - uint8_t max_link_width; - uint8_t negotiated_link_width; - uint8_t supported_link_speeds_vector; - uint8_t max_link_speed; - uint8_t current_link_speed; - uint8_t ltssm_state; - uint8_t first_lane_num; - uint16_t link_state; - uint8_t supported_ld_count; - } QEMU_PACKED; - - /* CXL r3.1 Table 7-18: Get Physical Port State Response Payload */ + /* CXL r3.2 Table 7-18: Get Physical Port State Response Payload */ struct cxl_fmapi_get_phys_port_state_resp_pl { uint8_t num_ports; uint8_t rsv1[3]; - struct cxl_fmapi_port_state_info_block ports[]; + struct cxl_phy_port_info ports[]; } QEMU_PACKED *out; - PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; - PCIEPort *usp =3D PCIE_PORT(cci->d); - size_t pl_size; - int i; =20 in =3D (struct cxl_fmapi_get_phys_port_state_req_pl *)payload_in; out =3D (struct cxl_fmapi_get_phys_port_state_resp_pl *)payload_out; @@ -620,69 +585,20 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, return CXL_MBOX_INVALID_INPUT; } =20 - /* For success there should be a match for each requested */ - out->num_ports =3D in->num_ports; + if (in->num_ports > pp->pports.num_ports) { + return CXL_MBOX_INVALID_INPUT; + } =20 + out->num_ports =3D in->num_ports; for (i =3D 0; i < in->num_ports; i++) { - struct cxl_fmapi_port_state_info_block *port; - /* First try to match on downstream port */ - PCIDevice *port_dev; - uint16_t lnkcap, lnkcap2, lnksta; - - port =3D &out->ports[i]; - - port_dev =3D pcie_find_port_by_pn(bus, in->ports[i]); - if (port_dev) { /* DSP */ - PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) - ->devices[0]; - port->config_state =3D 3; - if (ds_dev) { - if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { - port->connected_device_type =3D 5; /* Assume MLD for n= ow */ - } else { - port->connected_device_type =3D 1; - } - } else { - port->connected_device_type =3D 0; - } - port->supported_ld_count =3D 3; - } else if (usp->port =3D=3D in->ports[i]) { /* USP */ - port_dev =3D PCI_DEVICE(usp); - port->config_state =3D 4; - port->connected_device_type =3D 0; - } else { + int pn =3D in->ports[i]; + if (pp->pports.pport_info[pn].port_id !=3D pn) { return CXL_MBOX_INVALID_INPUT; + } else { + memcpy(&out->ports[i], &(pp->pports.pport_info[pn]), + sizeof(struct cxl_phy_port_info)); } - - port->port_id =3D in->ports[i]; - /* Information on status of this port in lnksta, lnkcap */ - if (!port_dev->exp.exp_cap) { - return CXL_MBOX_INTERNAL_ERROR; - } - lnksta =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= STA, - sizeof(lnksta)); - lnkcap =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LNK= CAP, - sizeof(lnkcap)); - lnkcap2 =3D port_dev->config_read(port_dev, - port_dev->exp.exp_cap + PCI_EXP_LN= KCAP2, - sizeof(lnkcap2)); - - port->max_link_width =3D (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - port->negotiated_link_width =3D (lnksta & PCI_EXP_LNKSTA_NLW) >> 4; - /* No definition for SLS field in linux/pci_regs.h */ - port->supported_link_speeds_vector =3D (lnkcap2 & 0xFE) >> 1; - port->max_link_speed =3D lnkcap & PCI_EXP_LNKCAP_SLS; - port->current_link_speed =3D lnksta & PCI_EXP_LNKSTA_CLS; - /* TODO: Track down if we can get the rest of the info */ - port->ltssm_state =3D 0x7; - port->first_lane_num =3D 0; - port->link_state =3D 0; - port->port_cxl_version_bitmask =3D 0x2; - port->connected_device_cxl_version =3D 0x2; } - pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; *len_out =3D pl_size; =20 @@ -3686,6 +3602,101 @@ void cxl_add_cci_commands(CXLCCI *cci, const struct= cxl_cmd (*cxl_cmd_set)[256], cxl_rebuild_cel(cci); } =20 +static CXLRetCode cxl_set_port_type(CXLUpstreamPort *ports, int pnum, + CXLCCI *cci) +{ + uint16_t lnkcap, lnkcap2, lnksta; + PCIBus *bus; + PCIDevice *port_dev; + PCIEPort *usp =3D PCIE_PORT(cci->d); + + if (usp->port =3D=3D pnum) { + port_dev =3D PCI_DEVICE(usp); + ports->pports.pport_info[pnum].current_port_config_state =3D + CXL_PORT_CONFIG_STATE_USP; + ports->pports.pport_info[pnum].connected_device_type =3D NO_DEVICE= _DETECTED; + } else { + bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + port_dev =3D pcie_find_port_by_pn(bus, pnum); + if (port_dev) { /* DSP */ + PCIDevice *ds_dev =3D pci_bridge_get_sec_bus(PCI_BRIDGE(port_d= ev)) + ->devices[0]; + ports->pports.pport_info[pnum].current_port_config_state =3D + CXL_PORT_CONFIG_STATE_DSP; + if (ds_dev) { + if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { + /* To-do: controllable */ + ports->pports.pport_info[pnum].connected_device_type = =3D + CXL_TYPE_3_SLD; + } else { + ports->pports.pport_info[pnum].connected_device_type = =3D PCIE_DEVICE; + } + } else { + ports->pports.pport_info[pnum].connected_device_type =3D N= O_DEVICE_DETECTED; + } + ports->pports.pport_info[pnum].supported_ld_count =3D 3; + } else { + return CXL_MBOX_INVALID_INPUT; + } + } + + if (!port_dev->exp.exp_cap) { + return CXL_MBOX_INTERNAL_ERROR; + } + lnksta =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKSTA, + sizeof(lnksta)); + lnkcap =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP, + sizeof(lnkcap)); + lnkcap2 =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKCAP= 2, + sizeof(lnkcap2)); + + ports->pports.pport_info[pnum].max_link_width =3D (lnkcap & PCI_EXP_LN= KCAP_MLW) >> 4; + ports->pports.pport_info[pnum].negotiated_link_width =3D + (lnksta & PCI_EXP_LNKSTA_NLW) >> 4; + ports->pports.pport_info[pnum].supported_link_speeds_vector =3D (lnkca= p2 & 0xFE) >> 1; + ports->pports.pport_info[pnum].max_link_speed =3D lnkcap & PCI_EXP_LNK= CAP_SLS; + ports->pports.pport_info[pnum].current_link_speed =3D lnksta & PCI_EXP= _LNKSTA_CLS; + + ports->pports.pport_info[pnum].port_id =3D pnum; + ports->pports.active_port_bitmask[pnum / 8] |=3D (1 << pnum % 8); + ports->pports.pport_info[pnum].ltssm_state =3D LTSSM_L2; + ports->pports.pport_info[pnum].first_negotiated_lane_num =3D 0; + ports->pports.pport_info[pnum].link_state_flags =3D 0; + ports->pports.pport_info[pnum].supported_cxl_modes =3D CXL_256B_FLIT_C= APABLE; + ports->pports.pport_info[pnum].connected_device_mode =3D STANDARD_256B= _FLIT_MODE; + + return CXL_MBOX_SUCCESS; +} + +static void cxl_set_dsp_port(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + CXLCCI *cci =3D (CXLCCI *)opaque; + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + + if (object_dynamic_cast(OBJECT(dev), TYPE_CXL_DSP)) { + uint8_t phy_port_num =3D PCIE_PORT(dev)->port; + cxl_set_port_type(pp, phy_port_num, cci); + } +} + +static CXLRetCode cxl_set_phy_port_info(CXLCCI *cci) +{ + PCIEPort *usp =3D PCIE_PORT(cci->d); + PCIBus *bus =3D &PCI_BRIDGE(cci->d)->sec_bus; + CXLUpstreamPort *pp =3D CXL_USP(cci->d); + int num_phys_ports =3D pcie_count_ds_ports(bus) + 1; + pp->pports.num_ports =3D num_phys_ports; + uint8_t phy_port_num =3D usp->port; + + cxl_set_port_type(pp, phy_port_num, cci); /* USP */ + pci_for_each_device_under_bus(bus, cxl_set_dsp_port, cci); /* DSP */ + + return CXL_MBOX_SUCCESS; +} + void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, DeviceState *d, size_t payload_max) { @@ -3693,6 +3704,7 @@ void cxl_initialize_mailbox_swcci(CXLCCI *cci, Device= State *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); } =20 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload= _max) @@ -3797,4 +3809,5 @@ void cxl_initialize_usp_mctpcci(CXLCCI *cci, DeviceSt= ate *d, DeviceState *intf, cci->d =3D d; cci->intf =3D intf; cxl_init_cci(cci, payload_max); + cxl_set_phy_port_info(cci); } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index ca515cab13..1fa6cf7536 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -127,6 +127,88 @@ CXL_NUM_CHMU_INSTANCES * (1 << 16), \ (1 << 16)) =20 +#define CXL_MAX_PHY_PORTS 256 + +#define LINK_STATE_FLAG_LANE_REVERSED BIT(0) +#define LINK_STATE_FLAG_PERST_ASSERTED BIT(1) +#define LINK_STATE_FLAG_PRSNT BIT(2) +#define LINK_STATE_FLAG_POWER_OFF BIT(3) + +/* physical port control info - CXL r3.2 table 7-19 */ +#define CXL_PORT_CONFIG_STATE_DISABLED 0x0 +#define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 +#define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2 +#define CXL_PORT_CONFIG_STATE_DSP 0x3 +#define CXL_PORT_CONFIG_STATE_USP 0x4 +#define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5 +#define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF + +typedef enum { + NOT_CXL_OR_DISCONNECTED =3D 0x00, + RCD_MODE =3D 0x01, + CXL_68B_FLIT_AND_VH_MODE =3D 0x02, + STANDARD_256B_FLIT_MODE =3D 0x03, + CXL_LATENCY_OPTIMIZED_256B_FLIT_MODE =3D 0x04, + PBR_MODE =3D 0x05 +} connected_device_mode; + +typedef enum { + NO_DEVICE_DETECTED =3D 0, + PCIE_DEVICE =3D 1, + CXL_TYPE_1_DEVICE =3D 2, + CXL_TYPE_2_DEVICE_OR_HBR_SWITCH =3D 3, + CXL_TYPE_3_SLD =3D 4, + CXL_TYPE_3_MLD =3D 5, + PBR_COMPONENT =3D 6 +} connected_device_type; + +typedef enum { + CXL_RCD_MODE =3D 0x00, + CXL_68B_FLIT_AND_VH_CAPABLE =3D 0x01, + CXL_256B_FLIT_CAPABLE =3D 0x02, + CXL_LATENCY_OPTIMIZED_256B_FLIT =3D 0x03, + CXL_PBR_CAPABLE =3D 0x04 +} supported_cxl_modes; + +typedef enum { + LTSSM_DETECT =3D 0x00, + LTSSM_POLLING =3D 0x01, + LTSSM_CONFIGURATION =3D 0x02, + LTSSM_RECOVERY =3D 0x03, + LTSSM_L0 =3D 0x04, + LTSSM_L0S =3D 0x05, + LTSSM_L1 =3D 0x06, + LTSSM_L2 =3D 0x07, + LTSSM_DISABLED =3D 0x08, + LTSSM_LOOPBACK =3D 0x09, + LTSSM_HOT_RESET =3D 0x0A +} LTSSM_State; + +/* CXL r3.2 Table 7-19: Port Info */ +struct cxl_phy_port_info { + uint8_t port_id; + uint8_t current_port_config_state; + uint8_t connected_device_mode; + uint8_t rsv1; + uint8_t connected_device_type; + uint8_t supported_cxl_modes; + uint8_t max_link_width; + uint8_t negotiated_link_width; + uint8_t supported_link_speeds_vector; + uint8_t max_link_speed; + uint8_t current_link_speed; + uint8_t ltssm_state; + uint8_t first_negotiated_lane_num; + uint16_t link_state_flags; + uint8_t supported_ld_count; +} QEMU_PACKED; + +struct phy_port { + uint8_t num_ports; + uint8_t active_port_bitmask[0x20]; + struct cxl_phy_port_info pport_info[CXL_MAX_PHY_PORTS]; +}; + /* CXL r3.1 Table 8-34: Command Return Codes */ typedef enum { CXL_MBOX_SUCCESS =3D 0x0, diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bri= dge/cxl_upstream_port.h index db1dfb6afd..bcd3002cf8 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -4,6 +4,7 @@ #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" #include "hw/cxl/cxl.h" +#include "include/hw/cxl/cxl_device.h" =20 typedef struct CXLUpstreamPort { /*< private >*/ @@ -23,6 +24,9 @@ typedef struct CXLUpstreamPort { =20 DOECap doe_cdat; uint64_t sn; + + /*< physical ports information >*/ + struct phy_port pports; } CXLUpstreamPort; =20 #endif /* CXL_SUP_H */ --=20 2.34.1