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([189.110.24.38]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c84599f07sm153380175ad.218.2025.07.09.11.05.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 11:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752084350; x=1752689150; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vSHu2C6AHkdi6I2MI+MN+9VTwDs09gk+qY11owIPdS8=; b=GyvGoAZ/ANAFePzdECm7laBFQbFvsGoo95Je9Xu054E7YHLlKU0yOSggLgLq4PK3oY zPGRZ7argdtYrifbGmA53LluwO9cKklk54MGuf/qBFrhhh7V4BREOm/RWWMZffNdzPak gJ3scFiC8JInlkxymTA6nE9AkVUueDhSMywBZOxshTkJAYdee+wMPg0TMEz+vosO/KWr o2hyB0ALKG3x5iHzfRngl5eZKvbT7XZjYnSgsAGfPFz42F29SLTlcu+kwuk2FkZzSSaG 1DVWpfYRE2RCa/xBd4+zVCWNE7cPLf18sF6Hww5CEu9hXNAfULEeVhz5gYM7cgg+O2lt sxcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752084350; x=1752689150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vSHu2C6AHkdi6I2MI+MN+9VTwDs09gk+qY11owIPdS8=; b=NtphHdAFOSBEM+2c9YPPEOlfpdHYwS7hfZ+tWnn9MJo5/9Oj7guReL+PMJNvblngb6 uQs+zUyMDUvUSAVd4GbzWisSMGeLis7uANaaJCXQjJd7LC1FaOJav7ulwJBr/i3LdybH YhuRIDbPE3+5UNIFvUyds8DT9YrHDwhizWOOnajBW/M96eNaa20SRYv+dnQh77MfnWVe qA3A/mn8U6jhGvxB1SQbG68WbzJkE7jVWkvfuJ0bEy6qlLUWiOvAsqUNkhhcVZtoh+P6 raSmZ1HkcFv3CAM7lB7hYId8xBhm6r9mCWCMAxZCVvbKqLhGxmwKKmns1QW2ONfDe3Zt mZLA== X-Gm-Message-State: AOJu0Yz0YSv4FyCbeTil0ljeTqSWUxBeBNYqdUzNQHziXL6cSVLTjyJg YZoxjx/2zsCV0fUSRQVSrIJi6XHYoTqw+8eGTuUQR2h6e+RVUhx7rgvbRnS0UK303YU= X-Gm-Gg: ASbGnctNXIaP5N0fksSWTnHNn7rvxmqcgpV8mzOBudYViYWHjsU98AIePvoA4n05Upq aI+L8mmz/hDv7LWEa2pX/1W5vS32ARRY3rdnQKULwIq0aaPU20W/h0WTNqglgBV9fKhopj1rNQh JKd9+jHBqq9YHl9NyoxLL2a5VA7afcP4eLrW1y/Bo2zIVd8me3WiANhZFXVTRq8ff2/rmwWFvRS ke4eOr7ipAmHqlCiRYBseHetCbIWMGD3eQhkti3gehiT1O9CrMNilAT43TaorXFN0Xw/5HHQ5/g pC5JEfvaEbHF09TgREFd7pPTIE7+UZnrlnhiFB9Dkqtm9jWoECdytNFDKRSUbfa5++A= X-Google-Smtp-Source: AGHT+IHlaKJfJDEhDeguKXFw3p6Nu7oCLURk+bMtTCV7YeCCek8aHndypC4k1qqUj64kyXUeg9BgKA== X-Received: by 2002:a17:90b:1c0a:b0:31c:203f:cacd with SMTP id 98e67ed59e1d1-31c2fe001f2mr5359211a91.22.1752084349958; Wed, 09 Jul 2025 11:05:49 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v4 1/6] target/arm: Add the MECEn SCR_EL3 bit Date: Wed, 9 Jul 2025 18:03:21 +0000 Message-Id: <20250709180326.1079826-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709180326.1079826-1-gustavo.romero@linaro.org> References: <20250709180326.1079826-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=gustavo.romero@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752084457407116600 Content-Type: text/plain; charset="utf-8" The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c8cf0ab417..0f64c7b163 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1717,6 +1717,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ --=20 2.34.1 From nobody Sat Nov 15 10:54:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752084424; cv=none; d=zohomail.com; s=zohoarc; b=a/5Emai5ia1JrDOG/Do3jV00uc4Sn5QVphe1LlmEiVl39EOkWL3Vf5MEVLk1BxYudh/jgoxlqDJMSmkQ+ARaegyA1HRlaVYGcsH+Gnn2vJtMhv8MpEunyvNMW3IJutwu0Oy+kXIbdsJpvw4NVjf7EzFw19/BUEb5EqMym88kavE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752084424; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AmhliCegNfZGHfr7J+p0jeoV/6BX3pT1C+80y0xkf40=; b=MVorzV2ku6HwPPlwVSszj4pzBQ3iLDo9cloXiNtaiJqWCx4bBOG1cYrTVaS7MS0yz3Wv9ROD+rGyXA+hm230u3crwzzze2d9ECe8beT0IM2hFYq/k2wczYRj2ecffMplIZ7cQg3gj906nt05fOjrdEnOjqaYbeKiqca96erf53o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752084424580909.4399892897462; Wed, 9 Jul 2025 11:07:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZZBk-0001OK-PJ; Wed, 09 Jul 2025 14:06:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZZB7-00014J-G1 for qemu-devel@nongnu.org; Wed, 09 Jul 2025 14:05:58 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uZZB3-00048w-Ly for qemu-devel@nongnu.org; Wed, 09 Jul 2025 14:05:55 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-311d5fdf1f0so256337a91.1 for ; Wed, 09 Jul 2025 11:05:53 -0700 (PDT) Received: from gromero0.. ([189.110.24.38]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c84599f07sm153380175ad.218.2025.07.09.11.05.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 11:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752084352; x=1752689152; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AmhliCegNfZGHfr7J+p0jeoV/6BX3pT1C+80y0xkf40=; b=mxiVph+hddOuVTNrWlyFS6TsUvExzjKTCGR7ayj3Mh8oK8kZ6QXiT2R0MtgN2WyxOy JBuym9Udq5kDA7n6NE9kuQcnr65enHwFGiop+JBN+/P2IzS0WZTvekrmYU/ItwxnO2xK YB8pAGx4SAdr/BBUaHWWkGiRW7w/41IEwpB3SiPRe4OQ1ZIm1y2+9yy6h1kMxXc1EE4S XYQ0PvMQ0blorXr6e8bYFA3FuOT9pkk/PGopXV4lbA+daJZ8Xx+MYLgPsCmvJj0AAqgU ko7UBTOG/dJyiKuT+wkA4tZG7dUDrUlE6hmFSTOkKr5sPdLKSyJpVTLMSKChrcLI22g7 VEbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752084352; x=1752689152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AmhliCegNfZGHfr7J+p0jeoV/6BX3pT1C+80y0xkf40=; b=a+BgT5OuseojEygoBs63OYpY/VL2LhoRSSvnXZPPbe/i5mbbYb2fkd1B6dlbpTNe/Z 7zSbtToTgShWu88X63CBSldqNZnHLhPdnOO0mr1N5PWM+of6tR2h+y8/+DEJf9Aku29E dl03biLNouDFlyfB2sG9ir4Sn/zyoDoCol+exUnrYHpSHUuJcPOgx9x4tYamhXnfNu2v P9oBmYSyKC+8cd3XelBxdjsAKEGgzgYCeV9GFUFJvbyyi41PAKrIAEB+ajr4RXxVIeeg H9tDxt65WGDkF2VEdu2XferI3jIMct16UVSQ81pTkmw+EhsQXN86ivng2blivKbjEqbV b+IQ== X-Gm-Message-State: AOJu0Yy4sVl5h304gdtqaVqSdCAHVQR0jZyyy8PkTlTs2Mx9SDdOzdii e5AJnN+3hzAx4Q6PdT73YSEpis6vAVvP3UcuFjUJWBIx1k4yfye98irsUj3TqRjrWcQ= X-Gm-Gg: ASbGncteVsuYDBYk01YtNOu0LQu3XFgW4/bgiy4t4UcwYim6FB1fHes/ACJAXknsrEL HfvIV3ZcykzXZni12UvIWcJv4FXxiaUCbR2fo8gMft+C1R71UTRx/AmCGku8rqLlGv00+TfxBtl o1Eypbusj26ETnMV/1SmTO8te4PCwh8pmxamaXTiMfW9hrnn2LJfmPPSOXidfvs/hWBXEO/URJ1 0VgJoJaDRMxOrPYYK3Yt/jpv+Q4/GqFS0WW8Omqk7/SGa8YyOHNu3e4tuvQsZrfP3qCrIZ2PePk Rl6/5bUEnBQR9Ogcppu5w0/qeaPbcXK1NuEDTNwgtbe10hwunTFqTzyalrjt394eRFI= X-Google-Smtp-Source: AGHT+IF7n01vAizxIJsxMkOuXsK/RAkq6fyKho4QvjqgAJ/s1145LjgDO/lRt5uRDi655Vw2ZiNILw== X-Received: by 2002:a17:90a:d44f:b0:311:abba:53c9 with SMTP id 98e67ed59e1d1-31c3c25555dmr1442755a91.7.1752084351968; Wed, 09 Jul 2025 11:05:51 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v4 2/6] target/arm: Add FEAT_MEC registers Date: Wed, 9 Jul 2025 18:03:22 +0000 Message-Id: <20250709180326.1079826-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709180326.1079826-1-gustavo.romero@linaro.org> References: <20250709180326.1079826-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=gustavo.romero@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752084427154116600 Content-Type: text/plain; charset="utf-8" Add all FEAT_MEC registers. To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected. FEAT_MEC also requires two new cache management instructions, not included in this commit, that will be implemented in subsequent commits. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 11 ++++++ target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428..552d8757b7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -594,6 +594,11 @@ static inline bool isar_feature_aa64_hbc(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; +} + static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f64c7b163..a93eebe077 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -576,6 +576,15 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -2424,6 +2433,8 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 +#define MECID_WIDTH 16 + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index b3f0d6f17a..984406c945 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6827,6 +6827,72 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 2) { + if (arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + + if (!(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value =3D extract64(value, 0, MECID_WIDTH); + raw_write(env, ri, value); +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .access =3D PL2_R, .type =3D ARM_CP_CONST, .resetvalue =3D MECID_WID= TH - 1 }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL3_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9014,6 +9080,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.34.1 From nobody Sat Nov 15 10:54:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752084468; cv=none; d=zohomail.com; s=zohoarc; b=Lv8ZhRGCqjGnGk4EdqCzE6cw2d3RqQADv5aoPCVPl7ye5yEl8MAHor+T7WGhtX3LypmAFzcseAPX3RQaL3I3kFzHjUZ1+WglNUC9cM5VdPgM/owTB6S0/l2wdkoHscTtB3W4MlXu/n+4MQWjmhfLv/YbUc2Vbo86qH/gHUih4Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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These registers are extensions of the SCTLR_ELx ones. Because the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, this commit only implements the EMEC bits in CTLR2_EL2 and SCTLR2_EL3. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 15 +++++++ target/arm/helper.c | 78 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/tcg/cpu64.c | 1 + 6 files changed, 101 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 890dc6fee2..66043b0747 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 552d8757b7..44d6b655a9 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -416,6 +416,11 @@ static inline bool isar_feature_aa64_rdm(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) !=3D 0; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; +} + static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR0, SHA3) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a93eebe077..32d30b7bb9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -337,6 +337,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1433,6 +1434,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8 /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1725,6 +1739,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/helper.c b/target/arm/helper.c index 984406c945..5707eea822 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6144,6 +6144,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), + "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12" }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), "CPACR", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), @@ -7816,6 +7818,78 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_el2_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +}; + +static CPAccessResult sctlr2_el1_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_SCTLR2EN= )) { + return CP_ACCESS_TRAP_EL2; + } + return sctlr2_el2_access(env, ri, isread); +}; + +static void sctlr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* This register does not control any feature yet. */ +}; + +static void sctlr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +}; + +static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +}; + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, + .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_el2_access, + .writefn =3D sctlr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9084,6 +9158,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mec_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 21a8d67edd..398e0b4a7d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -232,6 +232,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) =20 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d0df50a2f3..bdd2fe7f5b 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,6 +1247,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); --=20 2.34.1 From nobody Sat Nov 15 10:54:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752084473; cv=none; d=zohomail.com; s=zohoarc; b=S1KwOZnUb0p9SFgewBQaM+/Y4p6Yoh8HsMYUJK/Ut8VULR1Mr6SeIW4gYwby2/tsi1/938QaKReJlACk1d/+awMZhP+fvvP89zu6cygCQSctMp0jmIBVjKLpe1tCy/krolMufg1DLEEZ1WFAkKpM2uYknJGAH4/zc/OZayRjAdo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752084473; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Since the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, the FEAT_TCR2 only implements the AMEC bits for now. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 2 ++ target/arm/helper.c | 60 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 19 +++++++++++ target/arm/tcg/cpu64.c | 1 + 6 files changed, 88 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 66043b0747..1c597d8673 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -149,6 +149,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage= 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage= 1) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 44d6b655a9..3878aed589 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -486,6 +486,11 @@ static inline bool isar_feature_aa64_xs(const ARMISARe= gisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR1, XS) !=3D 0; } =20 +static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) !=3D 0; +} + /* * These are the values from APA/API/APA3. * In general these must be compared '>=3D', per the normal Arm ARM diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32d30b7bb9..5c13f89b29 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -366,6 +366,7 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ uint64_t tcr_el[4]; + uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ @@ -1739,6 +1740,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5707eea822..34e12bde90 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6154,6 +6154,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), + "TCR2_EL1", "TCR2_EL2", "TCR2_EL12" }, { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), @@ -7890,6 +7892,60 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 +static CPAccessResult tcr2_el2_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) < 3 && !(env->cp15.scr_el3 & SCR_TCR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +}; + +static CPAccessResult tcr2_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= { + return CP_ACCESS_TRAP_EL2; + } + return tcr2_el2_access(env, ri, isread); +} + +static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* This register does not control any feature yet. */ +} + +static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; + } + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo tcr2_reginfo[] =3D { + { .name =3D "TCR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, + .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, + { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D tcr2_el2_access, + .writefn =3D tcr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9162,6 +9218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, sctlr2_reginfo); } =20 + if (cpu_isar_feature(aa64_tcr2, cpu)) { + define_arm_cp_regs(cpu, tcr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 398e0b4a7d..4b3dde82c6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -201,6 +201,24 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +#define TCR2_PNCH (1ULL << 0) +#define TCR2_PIE (1ULL << 1) +#define TCR2_E0POE (1ULL << 2) +#define TCR2_POE (1ULL << 3) +#define TCR2_AIE (1ULL << 4) +#define TCR2_D128 (1ULL << 5) +#define TCR2_PTTWI (1ULL << 10) +#define TCR2_HAFT (1ULL << 11) +#define TCR2_AMEC0 (1ULL << 12) +#define TCR2_AMEC1 (1ULL << 13) +#define TCR2_DISCH0 (1ULL << 14) +#define TCR2_DISCH1 (1ULL << 15) +#define TCR2_A2 (1ULL << 16) +#define TCR2_FNG0 (1ULL << 17) +#define TCR2_FNG1 (1ULL << 18) +#define TCR2_FNGNA0 (1ULL << 20) +#define TCR2_FNGNA1 (1ULL << 21) + FIELD(VTCR, T0SZ, 0, 6) FIELD(VTCR, SL0, 6, 2) FIELD(VTCR, IRGN0, 8, 2) @@ -232,6 +250,7 @@ FIELD(VTCR, SL2, 33, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index bdd2fe7f5b..173528175a 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,6 +1247,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 --=20 2.34.1 From nobody Sat Nov 15 10:54:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752084469; cv=none; d=zohomail.com; s=zohoarc; b=AtBDNAic3aKHHLh8r0H56jjLQyfc59d3r6K17QTXy4YBuMZMEguCIoMHrif3ZsUccxCZaGXPfBnupPAWTDf8YY3aXlNgKZNblG+7uZ7GWdyEdhKz95peuWyj0W55ipuD0xZbn/05CV0ttGIDMi2BXZtCm13J4f9LPp1Lqkx7d5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752084469; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Because QEMU does not model the cache topology, all cache maintenance instructions are implemented as NOPs, hence these new instructions are implemented as NOPs too. Signed-off-by: Gustavo Romero --- target/arm/helper.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 34e12bde90..36cf2b6415 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4996,6 +4996,34 @@ static void ic_ivau_write(CPUARMState *env, const AR= MCPRegInfo *ri, } #endif =20 +static CPAccessResult cipae_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + + if (!cpu_isar_feature(aa64_mec, env_archcpu(env))) { + return CP_ACCESS_UNDEFINED; + } + if (el < 3 && arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; +} + +static CPAccessResult cigdpae_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + CPAccessResult ret =3D cipae_access(env, ri, isread); + + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (!cpu_isar_feature(aa64_mte, env_archcpu(env))) { + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* * Minimal set of EL0-visible registers. This will need to be expanded @@ -5094,6 +5122,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .fgt =3D FGT_DCCISW, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, + { .name =3D "DC_CIPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D cipae_access, .type =3D ARM_CP_NOP = }, + { .name =3D "DC_CIGDPAE", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 14, .opc2 =3D 7, + .access =3D PL2_W, .accessfn =3D cigdpae_access, .type =3D ARM_CP_NO= P }, #ifndef CONFIG_USER_ONLY /* 64 bit address translation operations */ { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, --=20 2.34.1 From nobody Sat Nov 15 10:54:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1752084470; cv=none; d=zohomail.com; s=zohoarc; b=N2s/grQqhe2aL2qP6VSm33jRonAr9DJFGON06CiceHJNEkgerH3NFg0rP7UiQ2rXXvDUevu3lmcAETcNVF70Fasb84F4Pniuo5TLD2tW0da5FQsWY7cQkEIXNeQxmXuFA9uOfvNcqMzLloiZHS/PUYSRzzFW8+10UOjPcKvZzws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752084470; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WSgpCCNCeg+W2zo7Uq4pSJ5onka4R108XVyFa7HdUAM=; b=Q3BIc8nSPSlVQo3w799dF47XqUCZ1YpJAgzFtqE82Ts/FMSaSGcGmSd/KpjFob08tpEo0STqOTnVqQT4xvz+v8qgajPkOGPz3asDBOLCDYerI1SY0L5vCeGGin2yT+3mD439WSWHUvhA93ZzCKZWO560QYx8MslI8eilbbA8e7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175208447086759.435980875629184; Wed, 9 Jul 2025 11:07:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZZBr-0001TM-2L; Wed, 09 Jul 2025 14:06:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZZBE-00018x-Ta for qemu-devel@nongnu.org; Wed, 09 Jul 2025 14:06:05 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uZZBB-0004Ao-O1 for qemu-devel@nongnu.org; Wed, 09 Jul 2025 14:06:04 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-2349f096605so2116335ad.3 for ; Wed, 09 Jul 2025 11:06:01 -0700 (PDT) Received: from gromero0.. ([189.110.24.38]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23c84599f07sm153380175ad.218.2025.07.09.11.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 11:05:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752084360; x=1752689160; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WSgpCCNCeg+W2zo7Uq4pSJ5onka4R108XVyFa7HdUAM=; b=Cow+RNaFLp42VoSGz4PpHLlOC/ruChSmq1PgBLtWSS1Pb/vXqrXichWvikcdCzxezn NRFs17NIBWZOpKxR18nKdE4CUAWpM+2s8hRVKmS0Vb4xlKo8SBMrq6PAEiE/JaRRZpuE Rl68Zin0i1kZpfWwCiduoMk3jO5lX2D4iY+xO98e8/aW3ZP1Jy42iThizlNvVOaCqYzB rbj6BwoVKaMlfcCyYeI5enpUOkAE93r8RR1RGVBvK2OPpku1t9JixM8ew0SHNVvM6IPP 8nBv4oLkb5tyxUY7MuTgo9J1AsV/4tTr05lNf95N3VVnaKgiyvCXZMeIf19q29YSYkAm SBkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752084360; x=1752689160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WSgpCCNCeg+W2zo7Uq4pSJ5onka4R108XVyFa7HdUAM=; b=wsrdaYoRXQYHVsZTHCJQzhChil5nlhBED0o/7P37AQ7X82AujgcWln+2t+V0/HN/QF PceGKnXPCrYBJMae+H0YJRW4utTiz/A7hbDu+i4HEckutYxu74hH75xHbQwDVm8/b65S UcVrmdV7KYg4up2Sgfyzu6t6ZMVd+OI1f5Xhs/w6mn5VLZvqbLxFOUBFldy9rusRQGpk o0NiDUglOMOrio+7LV9XhSajdd0U9AOt0kXt2QSVsYQqrL09y9zI04ztCmrENwgRBQT5 2PlZY1gcZwVdnGkVwS4SvdL+0L0YSsxQQLDkYvbUPfuzcqKvpqxoGKZTChKmEO837SWb t+4g== X-Gm-Message-State: AOJu0YwU0viI6PtsHetb9s+AjWKzWJu9H3RqlzCp/JcLfxNXERooZCOB 2Jd+tc/zkM1FC0nQLc09+GZGl/S47C2fUm2JuHT7GbDUC0AzD2dd5ehEPCBKT7/DhV1yUFQW9pa V20BBgDk= X-Gm-Gg: ASbGncuxXCHvbDvj+aP3ZaRC4YDMAy1r4oMXpwpjuskPgr5VMxGobmjhJSHApPDcdBC 2oC6F7AcMiC1zKbq1A9/fNXOGgMVl5PODFa/GVZJ8rAE3dBUbSHP/xTVL8Uc8eEdLptiEI1gLVN VcNV7XcPFOLFYreQ8knU5+xzMWlf9o7x3ztQOGYazEsB5mMeFAlEv7310SQEr5G3Xie9gNhGWGG LWcQoG6Ik/0twhEnLOZ2xRZoolqBP+voiYl+h1kynfFeQWkFq+rMQAxENJWuu0o/6UOXiLAdR5N 5fddt00Q/hh4szF1ZZmW43pNTVqwzV92cYugJeakBnNtZ5CwcLbxb9X0pTtvXi0ssj8= X-Google-Smtp-Source: AGHT+IEAWiI3PsRLNGL8y55qUafpAsfqinwEcLFBlGMKoONIcrUmC+KHPLthkQ97+n/GULfhgpAkwA== X-Received: by 2002:a17:902:ef49:b0:23a:bc47:381f with SMTP id d9443c01a7336-23ddb36832dmr51466815ad.36.1752084360073; Wed, 09 Jul 2025 11:06:00 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [PATCH v4 6/6] target/arm: Advertise FEAT_MEC in cpu max Date: Wed, 9 Jul 2025 18:03:26 +0000 Message-Id: <20250709180326.1079826-7-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709180326.1079826-1-gustavo.romero@linaro.org> References: <20250709180326.1079826-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=gustavo.romero@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752084471396116600 Content-Type: text/plain; charset="utf-8" Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a first step to fully support FEAT_MEC. The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption is supported, but most software stacks that rely on FEAT_MEC to run should work properly. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 3 +++ target/arm/tcg/cpu64.c | 1 + 2 files changed, 4 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 1c597d8673..d207a9f266 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -89,6 +89,9 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) + + * This is a register-only implementation without encryption. - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 173528175a..2c63940878 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1249,6 +1249,7 @@ void aarch64_max_tcg_initfn(Object *obj) =20 FIELD_DP64_IDREG(isar, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + FIELD_DP64_IDREG(isar, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); --=20 2.34.1