From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022015515147.8563857304855; Tue, 8 Jul 2025 17:46:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIww-0003qa-Ni; Tue, 08 Jul 2025 20:46:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwf-0003j6-VX for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:58 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Ls-Dx for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Ax3eK7u21oGOgkAQ--.40989S3; Wed, 09 Jul 2025 08:45:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S3; Wed, 09 Jul 2025 08:45:47 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 1/6] target/loongarch: Move some function definition to kvm directory Date: Wed, 9 Jul 2025 08:45:41 +0800 Message-Id: <20250709004546.3005275-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022017742116600 Content-Type: text/plain; charset="utf-8" Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 9 --------- target/loongarch/kvm/kvm_loongarch.h | 4 ++-- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index b15ada2078..31215b7785 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -46,6 +46,7 @@ #include "hw/block/flash.h" #include "hw/virtio/virtio-iommu.h" #include "qemu/error-report.h" +#include "kvm/kvm_loongarch.h" =20 static void virt_get_veiointc(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 9538e8d61d..bbe6db33f1 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -496,13 +496,4 @@ static inline void set_pc(CPULoongArchState *env, uint= 64_t value) =20 void loongarch_cpu_post_init(Object *obj); =20 -#ifdef CONFIG_KVM -void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); -#else -static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu) -{ -} -#endif -void kvm_loongarch_init_irq_routing(void); - #endif /* LOONGARCH_CPU_H */ diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kv= m_loongarch.h index 1051a341ec..51475675d6 100644 --- a/target/loongarch/kvm/kvm_loongarch.h +++ b/target/loongarch/kvm/kvm_loongarch.h @@ -5,11 +5,11 @@ * Copyright (c) 2023 Loongson Technology Corporation Limited */ =20 -#include "cpu.h" - #ifndef QEMU_KVM_LOONGARCH_H #define QEMU_KVM_LOONGARCH_H =20 +void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu); +void kvm_loongarch_init_irq_routing(void); int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level); void kvm_arch_reset_vcpu(CPUState *cs); =20 --=20 2.39.3 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022030206704.9416229459578; Tue, 8 Jul 2025 17:47:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwt-0003pI-TB; Tue, 08 Jul 2025 20:46:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwe-0003ia-Rf for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:56 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Lw-DK for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:56 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxrOK7u21oGegkAQ--.38090S3; Wed, 09 Jul 2025 08:45:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S4; Wed, 09 Jul 2025 08:45:47 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 2/6] target/loongarch: Define function loongarch_cpu_post_init as static Date: Wed, 9 Jul 2025 08:45:42 +0800 Message-Id: <20250709004546.3005275-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022031828116600 Content-Type: text/plain; charset="utf-8" Function loongarch_cpu_post_init() is implemented and used in the same file target/loongarch/cpu.c, it can be defined as static function. This patch moves implementation about function loongarch_cpu_post_init() before it is referenced. And it is only code movement, no function change. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 180 ++++++++++++++++++++--------------------- target/loongarch/cpu.h | 2 - 2 files changed, 90 insertions(+), 92 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c054..b96429ffb1 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -422,6 +422,96 @@ static void loongarch_la464_init_csr(Object *obj) #endif } =20 +static bool loongarch_get_lsx(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->lsx !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_lsx(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if (cpu->lsx =3D=3D ON_OFF_AUTO_OFF) { + cpu->lasx =3D ON_OFF_AUTO_OFF; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "Failed to disable LSX since LASX is enabled"= ); + return; + } + } + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; + } + + /* LSX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LSX) =3D=3D 0) { + error_setg(errp, "Failed to enable LSX in TCG mode"); + return; + } + } else { + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, 0); + val =3D cpu->env.cpucfg[2]; + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); +} + +static bool loongarch_get_lasx(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->lasx !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_lasx(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->lasx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + if ((cpu->lsx =3D=3D ON_OFF_AUTO_OFF) && (cpu->lasx =3D=3D ON_OFF_AUTO= _ON)) { + error_setg(errp, "Failed to enable LASX since lSX is disabled"); + return; + } + + if (kvm_enabled()) { + /* kvm feature detection in function kvm_arch_init_vcpu */ + return; + } + + /* LASX feature detection in TCG mode */ + val =3D cpu->env.cpucfg[2]; + if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { + if (FIELD_EX32(val, CPUCFG2, LASX) =3D=3D 0) { + error_setg(errp, "Failed to enable LASX in TCG mode"); + return; + } + } + + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); +} + +static void loongarch_cpu_post_init(Object *obj) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + cpu->lbt =3D ON_OFF_AUTO_OFF; + cpu->pmu =3D ON_OFF_AUTO_OFF; + cpu->lsx =3D ON_OFF_AUTO_AUTO; + cpu->lasx =3D ON_OFF_AUTO_AUTO; + object_property_add_bool(obj, "lsx", loongarch_get_lsx, + loongarch_set_lsx); + object_property_add_bool(obj, "lasx", loongarch_get_lasx, + loongarch_set_lasx); + /* lbt is enabled only in kvm mode, not supported in tcg mode */ + if (kvm_enabled()) { + kvm_loongarch_cpu_post_init(cpu); + } +} + static void loongarch_la464_initfn(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); @@ -683,96 +773,6 @@ static void loongarch_cpu_unrealizefn(DeviceState *dev) lacc->parent_unrealize(dev); } =20 -static bool loongarch_get_lsx(Object *obj, Error **errp) -{ - return LOONGARCH_CPU(obj)->lsx !=3D ON_OFF_AUTO_OFF; -} - -static void loongarch_set_lsx(Object *obj, bool value, Error **errp) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - uint32_t val; - - cpu->lsx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; - if (cpu->lsx =3D=3D ON_OFF_AUTO_OFF) { - cpu->lasx =3D ON_OFF_AUTO_OFF; - if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { - error_setg(errp, "Failed to disable LSX since LASX is enabled"= ); - return; - } - } - - if (kvm_enabled()) { - /* kvm feature detection in function kvm_arch_init_vcpu */ - return; - } - - /* LSX feature detection in TCG mode */ - val =3D cpu->env.cpucfg[2]; - if (cpu->lsx =3D=3D ON_OFF_AUTO_ON) { - if (FIELD_EX32(val, CPUCFG2, LSX) =3D=3D 0) { - error_setg(errp, "Failed to enable LSX in TCG mode"); - return; - } - } else { - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, 0); - val =3D cpu->env.cpucfg[2]; - } - - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LSX, value); -} - -static bool loongarch_get_lasx(Object *obj, Error **errp) -{ - return LOONGARCH_CPU(obj)->lasx !=3D ON_OFF_AUTO_OFF; -} - -static void loongarch_set_lasx(Object *obj, bool value, Error **errp) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - uint32_t val; - - cpu->lasx =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; - if ((cpu->lsx =3D=3D ON_OFF_AUTO_OFF) && (cpu->lasx =3D=3D ON_OFF_AUTO= _ON)) { - error_setg(errp, "Failed to enable LASX since lSX is disabled"); - return; - } - - if (kvm_enabled()) { - /* kvm feature detection in function kvm_arch_init_vcpu */ - return; - } - - /* LASX feature detection in TCG mode */ - val =3D cpu->env.cpucfg[2]; - if (cpu->lasx =3D=3D ON_OFF_AUTO_ON) { - if (FIELD_EX32(val, CPUCFG2, LASX) =3D=3D 0) { - error_setg(errp, "Failed to enable LASX in TCG mode"); - return; - } - } - - cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); -} - -void loongarch_cpu_post_init(Object *obj) -{ - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - - cpu->lbt =3D ON_OFF_AUTO_OFF; - cpu->pmu =3D ON_OFF_AUTO_OFF; - cpu->lsx =3D ON_OFF_AUTO_AUTO; - cpu->lasx =3D ON_OFF_AUTO_AUTO; - object_property_add_bool(obj, "lsx", loongarch_get_lsx, - loongarch_set_lsx); - object_property_add_bool(obj, "lasx", loongarch_get_lasx, - loongarch_set_lasx); - /* lbt is enabled only in kvm mode, not supported in tcg mode */ - if (kvm_enabled()) { - kvm_loongarch_cpu_post_init(cpu); - } -} - static void loongarch_cpu_init(Object *obj) { #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index bbe6db33f1..7731f6acdc 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -494,6 +494,4 @@ static inline void set_pc(CPULoongArchState *env, uint6= 4_t value) =20 #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU =20 -void loongarch_cpu_post_init(Object *obj); - #endif /* LOONGARCH_CPU_H */ --=20 2.39.3 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022004705113.05953343881845; Tue, 8 Jul 2025 17:46:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwt-0003pL-Ti; Tue, 08 Jul 2025 20:46:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwg-0003jB-5H for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:58 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Lr-Vz for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxfeG8u21oHegkAQ--.38369S3; Wed, 09 Jul 2025 08:45:48 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S5; Wed, 09 Jul 2025 08:45:47 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 3/6] target/loongarch: Set page size in TLB misc with STLB Date: Wed, 9 Jul 2025 08:45:43 +0800 Message-Id: <20250709004546.3005275-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022008219116600 Content-Type: text/plain; charset="utf-8" With VTLB different TLB entry may have different page size, and page size is set in PS field of TLB misc. However with STLB, all the TLB entries have the same page size, page size comes from register CSR_STLBPS, PS field of TLB misc is not used. Here PS field of TLB misc is used with all TLB entries, even with STLB, it is convenient with TLB maintainance operation. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 41 ++++++++----------------------- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index dc48b0f4d2..871a8f3e76 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -110,11 +110,8 @@ static void invalidate_tlb_entry(CPULoongArchState *en= v, int index) if (!tlb_e) { return; } - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); pagesize =3D MAKE_64BIT_MASK(tlb_ps, 1); mask =3D MAKE_64BIT_MASK(0, tlb_ps + 1); =20 @@ -179,11 +176,8 @@ static void fill_tlb_entry(CPULoongArchState *env, int= index) return; } =20 - /* Only MTLB has the ps fields */ - if (index >=3D LOONGARCH_STLB) { - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); - } - + /* Store page size in field PS */ + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); @@ -289,12 +283,7 @@ void helper_tlbrd(CPULoongArchState *env) =20 index =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX); tlb =3D &env->tlb[index]; - - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 if (!tlb_e) { @@ -489,11 +478,8 @@ void helper_invtlb_page_asid(CPULoongArchState *env, t= arget_ulong info, if (!tlb_e) { continue; } - if (i >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1); compare_shift =3D tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -522,11 +508,8 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *e= nv, if (!tlb_e) { continue; } - if (i >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); vpn =3D (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1); compare_shift =3D tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT; @@ -680,11 +663,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *= env, hwaddr *physical, uint64_t tlb_entry, tlb_ppn; uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; =20 - if (index >=3D LOONGARCH_STLB) { - tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); - } else { - tlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); - } + tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ =20 tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; --=20 2.39.3 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022070887406.7763635177215; Tue, 8 Jul 2025 17:47:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwx-0003qm-2s; Tue, 08 Jul 2025 20:46:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwe-0003iU-IK for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:56 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Lv-D7 for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:56 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxSWq8u21oH+gkAQ--.43846S3; Wed, 09 Jul 2025 08:45:48 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S6; Wed, 09 Jul 2025 08:45:48 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 4/6] target/loongarch: Add header file cpu-mmu.h Date: Wed, 9 Jul 2025 08:45:44 +0800 Message-Id: <20250709004546.3005275-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022072782116600 Content-Type: text/plain; charset="utf-8" New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 30 ++++++++++++++++++++++++++++++ target/loongarch/cpu.c | 1 + target/loongarch/cpu_helper.c | 1 + target/loongarch/internals.h | 20 -------------------- target/loongarch/tcg/csr_helper.c | 1 + target/loongarch/tcg/tlb_helper.c | 1 + 6 files changed, 34 insertions(+), 20 deletions(-) create mode 100644 target/loongarch/cpu-mmu.h diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h new file mode 100644 index 0000000000..4c5cbd7425 --- /dev/null +++ b/target/loongarch/cpu-mmu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * LoongArch CPU parameters for QEMU. + * + * Copyright (c) 2025 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_CPU_MMU_H +#define LOONGARCH_CPU_MMU_H + +enum { + TLBRET_MATCH =3D 0, + TLBRET_BADADDR =3D 1, + TLBRET_NOMATCH =3D 2, + TLBRET_INVALID =3D 3, + TLBRET_DIRTY =3D 4, + TLBRET_RI =3D 5, + TLBRET_XI =3D 6, + TLBRET_PE =3D 7, +}; + +bool check_ps(CPULoongArchState *ent, uint8_t ps); +int get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, int is_de= bug); +void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, + uint64_t *dir_width, target_ulong level); +hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +#endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b96429ffb1..990985708e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -17,6 +17,7 @@ #include "hw/qdev-properties.h" #include "exec/translation-block.h" #include "cpu.h" +#include "cpu-mmu.h" #include "internals.h" #include "fpu/softfloat-helpers.h" #include "csr.h" diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index e172b11ce1..2e8d3d7cfb 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -13,6 +13,7 @@ #include "exec/target_page.h" #include "internals.h" #include "cpu-csr.h" +#include "cpu-mmu.h" #include "tcg/tcg_loongarch.h" =20 void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index a7384b0d31..e50d109767 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -32,19 +32,6 @@ void restore_fp_status(CPULoongArchState *env); #endif =20 #ifndef CONFIG_USER_ONLY -enum { - TLBRET_MATCH =3D 0, - TLBRET_BADADDR =3D 1, - TLBRET_NOMATCH =3D 2, - TLBRET_INVALID =3D 3, - TLBRET_DIRTY =3D 4, - TLBRET_RI =3D 5, - TLBRET_XI =3D 6, - TLBRET_PE =3D 7, -}; - -bool check_ps(CPULoongArchState *ent, uint8_t ps); - extern const VMStateDescription vmstate_loongarch_cpu; =20 void loongarch_cpu_set_irq(void *opaque, int irq, int level); @@ -54,13 +41,6 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongA= rchCPU *cpu); uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu); void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu, uint64_t value); -int get_physical_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, int is_de= bug); -void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, - uint64_t *dir_width, target_ulong level); -hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - #endif /* !CONFIG_USER_ONLY */ =20 uint64_t read_fcc(CPULoongArchState *env); diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 2942d7feb8..49000b2418 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -16,6 +16,7 @@ #include "accel/tcg/cpu-ldst.h" #include "hw/irq.h" #include "cpu-csr.h" +#include "cpu-mmu.h" =20 target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val) { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 871a8f3e76..a2855209e2 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -10,6 +10,7 @@ #include "qemu/guest-random.h" =20 #include "cpu.h" +#include "cpu-mmu.h" #include "internals.h" #include "exec/helper-proto.h" #include "exec/cputlb.h" --=20 2.39.3 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022004129568.353195934406; Tue, 8 Jul 2025 17:46:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwv-0003qE-NT; Tue, 08 Jul 2025 20:46:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwg-0003jA-2a for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:58 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Lt-Dv for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxzOK8u21oIegkAQ--.12919S3; Wed, 09 Jul 2025 08:45:48 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S7; Wed, 09 Jul 2025 08:45:48 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 5/6] target/loongarch: Add common function loongarch_check_pte() Date: Wed, 9 Jul 2025 08:45:45 +0800 Message-Id: <20250709004546.3005275-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022008361116600 Content-Type: text/plain; charset="utf-8" Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 9 +++++ target/loongarch/cpu_helper.c | 63 +++++++++++++++++++++++++++++++ target/loongarch/tcg/tlb_helper.c | 61 ++++-------------------------- 3 files changed, 80 insertions(+), 53 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c5cbd7425..6ca77b8501 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -19,7 +19,15 @@ enum { TLBRET_PE =3D 7, }; =20 +typedef struct pte_context { + target_ulong vaddr; + uint64_t pte; + int page_shift; +} pte_context; + bool check_ps(CPULoongArchState *ent, uint8_t ps); +int loongarch_check_pte(CPULoongArchState *env, hwaddr *physical, int *pro= t, + pte_context *context, int access_type, int mmu_idx); int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx, int is_de= bug); @@ -27,4 +35,5 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t = *dir_base, uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 + #endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 2e8d3d7cfb..ed72ca1640 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -44,6 +44,69 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t= *dir_base, } } =20 +int loongarch_check_pte(CPULoongArchState *env, hwaddr *physical, int *pro= t, + pte_context *context, int access_type, int mmu_idx) + +{ + uint64_t plv =3D mmu_idx; + uint64_t tlb_entry, tlb_ppn; + uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + + tlb_entry =3D context->pte; + tlb_ps =3D context->page_shift; + + tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); + tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); + if (is_la64(env)) { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); + tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); + tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); + tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); + } else { + tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); + tlb_nx =3D 0; + tlb_nr =3D 0; + tlb_rplv =3D 0; + } + + /* Check access rights */ + if (!tlb_v) { + return TLBRET_INVALID; + } + + if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { + return TLBRET_XI; + } + + if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { + return TLBRET_RI; + } + + if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || + ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { + return TLBRET_PE; + } + + if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { + return TLBRET_DIRTY; + } + + /* Remove sw bit between bit12 -- bit PS*/ + tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); + *physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | + (context->vaddr & MAKE_64BIT_MASK(0, tlb_ps)); + *prot =3D PAGE_READ; + if (tlb_d) { + *prot |=3D PAGE_WRITE; + } + if (!tlb_nx) { + *prot |=3D PAGE_EXEC; + } + + return TLBRET_MATCH; +} + static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, int *prot, target_ulong address) { diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index a2855209e2..ccd2e52258 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -660,64 +660,19 @@ static int loongarch_map_tlb_entry(CPULoongArchState = *env, hwaddr *physical, int access_type, int index, int mmu_idx) { LoongArchTLB *tlb =3D &env->tlb[index]; - uint64_t plv =3D mmu_idx; - uint64_t tlb_entry, tlb_ppn; - uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv; + uint64_t tlb_entry; + uint8_t tlb_ps, n; + pte_context context; =20 tlb_ps =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS); n =3D (address >> tlb_ps) & 0x1;/* Odd or even */ =20 tlb_entry =3D n ? tlb->tlb_entry1 : tlb->tlb_entry0; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); - tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); - if (is_la64(env)) { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); - tlb_nx =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NX); - tlb_nr =3D FIELD_EX64(tlb_entry, TLBENTRY_64, NR); - tlb_rplv =3D FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); - } else { - tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); - tlb_nx =3D 0; - tlb_nr =3D 0; - tlb_rplv =3D 0; - } - - /* Remove sw bit between bit12 -- bit PS*/ - tlb_ppn =3D tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1)); - - /* Check access rights */ - if (!tlb_v) { - return TLBRET_INVALID; - } - - if (access_type =3D=3D MMU_INST_FETCH && tlb_nx) { - return TLBRET_XI; - } - - if (access_type =3D=3D MMU_DATA_LOAD && tlb_nr) { - return TLBRET_RI; - } - - if (((tlb_rplv =3D=3D 0) && (plv > tlb_plv)) || - ((tlb_rplv =3D=3D 1) && (plv !=3D tlb_plv))) { - return TLBRET_PE; - } - - if ((access_type =3D=3D MMU_DATA_STORE) && !tlb_d) { - return TLBRET_DIRTY; - } - - *physical =3D (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | - (address & MAKE_64BIT_MASK(0, tlb_ps)); - *prot =3D PAGE_READ; - if (tlb_d) { - *prot |=3D PAGE_WRITE; - } - if (!tlb_nx) { - *prot |=3D PAGE_EXEC; - } - return TLBRET_MATCH; + context.vaddr =3D address; + context.page_shift =3D tlb_ps; + context.pte =3D tlb_entry; + return loongarch_check_pte(env, physical, prot, &context, access_type, + mmu_idx); } =20 int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical, --=20 2.39.3 From nobody Sat Nov 15 12:43:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752022053584905.0251898016082; Tue, 8 Jul 2025 17:47:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIx2-0003rR-7r; Tue, 08 Jul 2025 20:46:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZIwg-0003j7-0m for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:58 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZIwb-0004Lu-Su for qemu-devel@nongnu.org; Tue, 08 Jul 2025 20:45:57 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxCeG9u21oI+gkAQ--.37841S3; Wed, 09 Jul 2025 08:45:49 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+S6u21o0TEPAA--.22142S8; Wed, 09 Jul 2025 08:45:48 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 6/6] target/loongarch: Use loongarch_check_pte() with page table walking Date: Wed, 9 Jul 2025 08:45:46 +0800 Message-Id: <20250709004546.3005275-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709004546.3005275-1-maobibo@loongson.cn> References: <20250709004546.3005275-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+S6u21o0TEPAA--.22142S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1752022053961116600 Content-Type: text/plain; charset="utf-8" Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used at page table walking. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index ed72ca1640..e185273950 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -108,13 +108,15 @@ int loongarch_check_pte(CPULoongArchState *env, hwadd= r *physical, int *prot, } =20 static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, - int *prot, target_ulong address) + int *prot, target_ulong address, + int access_type, int mmu_idx) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; uint64_t dir_base, dir_width; uint64_t base; int level; + pte_context context; =20 if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; @@ -157,29 +159,11 @@ static int loongarch_page_table_walker(CPULoongArchSt= ate *env, hwaddr *physical, base =3D ldq_phys(cs->as, phys); } =20 - /* TODO: check plv and other bits? */ - - /* base is pte, in normal pte format */ - if (!FIELD_EX64(base, TLBENTRY, V)) { - return TLBRET_NOMATCH; - } - - if (!FIELD_EX64(base, TLBENTRY, D)) { - *prot =3D PAGE_READ; - } else { - *prot =3D PAGE_READ | PAGE_WRITE; - } - - /* get TARGET_PAGE_SIZE aligned physical address */ - base +=3D (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1); - /* mask RPLV, NX, NR bits */ - base =3D FIELD_DP64(base, TLBENTRY_64, RPLV, 0); - base =3D FIELD_DP64(base, TLBENTRY_64, NX, 0); - base =3D FIELD_DP64(base, TLBENTRY_64, NR, 0); - /* mask other attribute bits */ - *physical =3D base & TARGET_PAGE_MASK; - - return 0; + context.vaddr =3D address; + context.page_shift =3D dir_base; + context.pte =3D base; + return loongarch_check_pte(env, physical, prot, &context, access_type, + mmu_idx); } =20 static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, @@ -203,7 +187,8 @@ static int loongarch_map_address(CPULoongArchState *env= , hwaddr *physical, * legal mapping, even if the mapping is not yet in TLB. return 0 = if * there is a valid map, else none zero. */ - return loongarch_page_table_walker(env, physical, prot, address); + return loongarch_page_table_walker(env, physical, prot, address, + access_type, mmu_idx); } =20 return TLBRET_NOMATCH; --=20 2.39.3