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([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702d638846asm56289096d6.22.2025.07.08.12.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jul 2025 12:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1752002356; x=1752607156; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AmhliCegNfZGHfr7J+p0jeoV/6BX3pT1C+80y0xkf40=; b=qJpaMapCABOibg96xQyPBepmRzEv9Wh1ApEcdV3xJdh6mi9lkWoQB0cmqY0lfogOQP 8OeaqJCu6FJPGn8wcS2t7tTXsnIJC5luF3ckur+k0oj/I4E+Kut4aHbbuGTuhjnbfqq9 NnovCXRoUmydcuepST7U3KsmBt69mRVRFE0mT1Hu6hxIREHE9mD/XU78d0HROGm2XcgN rRU35K1fdlw01WSDmmadDBVhxagAN3m9FnTaUJ7rFOXYleFf9pt6gKWzqyQtYOURdoeE 1fgkn/evWOgx7XxPlAWpilUeAopd6qparHcrFpaN+YzlF9Bu2QYM6XQlgc1dfOauC+yG AbSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752002356; x=1752607156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AmhliCegNfZGHfr7J+p0jeoV/6BX3pT1C+80y0xkf40=; b=VLpS/iNQhOnLPEr53F1I9BuRLoyi2rbF28v/rePo8M56/0SwAWoqmUpsdbhedW2nxQ IqG3NHGXHvPuh4wi8e8OQXe84ySLOc0w2RtY90kGwFtm9iVWiaqFcZr9rwMPHqOfiHiz RfI6ztixcTELEQsoLQdAGpKFzSXWOr5YhIle9VCJcZ7SZMFJz0QuffXBIhPRWFGgc2zV ta4eCQeDwFsrTuEcyeCuvfeM9S5qJ02PKvOMeMIXvvsYSLVQNofM/PQPIMd5P1VLsCIb 7tsWeqXN2Yianr1/SLDGzMZKbBagL/asQnagR8sWDrf6aDJd0wogEUz6FduqQp7G0eSy LDGA== X-Gm-Message-State: AOJu0Yy/m+LA35WF6SZJK1cHCgOOGG4j+9F+GUjdoY5nlTcUKN/p8T7d nv24y1IXdSJAR+QFckW6XQbJjpHs4BrGg76rMICh2275ToQdyS5RL8veNmzW2yyHCRCD7i13IET 4ziCZ0Yw= X-Gm-Gg: ASbGncsT5DNyYsfvp8VpQbwET89YRgE91aFit14+TS2kMpXlYNPDF0MIhzt6+fzDQpf OlwXTlgXQx3dFS+z+2xfSkaJf/t8P8+ObF/ictOYZFRn/hmFi/0+PLehq8Vi7h0Z/ceuSllKBgp GvhLO8HW/5IfRTOgBssC7dkep8ZKQeQ9ooox2rrsJOptiTixcivX3yiVlDyCYbt2RBstrBd/SVD NyE4S7Obo0eoqXvpbHc3WXFk2WwShQqa5lzbyXhEIL8yacWCZ/jqUx2p3rgqFv1oNPnMYXoDOXK mBFKyITBW0TaepSvFyqtcY0XANdU9obtqh+7qH0ySNGjZKIqELPFsFz0bt7A6bjF33I= X-Google-Smtp-Source: AGHT+IE+65XyCIHt0mMmNZ9x/WwtrgdOw2UmcMAB1mrk69YadyhIoyQ74Jz4sZDUtqmP6YZOIZNBbg== X-Received: by 2002:a05:6214:ca9:b0:6fd:d91:ba28 with SMTP id 6a1803df08f44-702c8cd99bdmr252089966d6.41.1752002356234; Tue, 08 Jul 2025 12:19:16 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, richard.henderson@linaro.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [RFC PATCH-for-10.1 v3 2/5] target/arm: Add FEAT_MEC registers Date: Tue, 8 Jul 2025 19:17:01 +0000 Message-Id: <20250708191704.1068604-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250708191704.1068604-1-gustavo.romero@linaro.org> References: <20250708191704.1068604-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1752008059952116600 Content-Type: text/plain; charset="utf-8" Add all FEAT_MEC registers. To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected. FEAT_MEC also requires two new cache management instructions, not included in this commit, that will be implemented in subsequent commits. Signed-off-by: Gustavo Romero --- target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 11 ++++++ target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428..552d8757b7 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -594,6 +594,11 @@ static inline bool isar_feature_aa64_hbc(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR2, BC) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; +} + static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR2, MOPS); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f64c7b163..a93eebe077 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -576,6 +576,15 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -2424,6 +2433,8 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 +#define MECID_WIDTH 16 + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index b3f0d6f17a..984406c945 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6827,6 +6827,72 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 2) { + if (arm_security_space(env) !=3D ARMSS_Realm) { + return CP_ACCESS_UNDEFINED; + } + + if (!(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value =3D extract64(value, 0, MECID_WIDTH); + raw_write(env, ri, value); +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .access =3D PL2_R, .type =3D ARM_CP_CONST, .resetvalue =3D MECID_WID= TH - 1 }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL3_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9014,6 +9080,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.34.1