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a="57973910" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973910" X-CSE-ConnectionGUID: vODf6lIERFep+cdj9Cjllw== X-CSE-MsgGUID: 0c6MqHjBQFyehb393xa7Cw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647930" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 02/20] hw/pci: Introduce pci_device_get_viommu_cap() Date: Tue, 8 Jul 2025 07:05:43 -0400 Message-ID: <20250708110601.633308-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008353696116600 Content-Type: text/plain; charset="utf-8" pci_device_get_viommu_cap() call pci_device_get_iommu_bus_devfn() to get iommu_bus->iommu_ops and call get_viommu_cap() callback to get a bitmap with each bit represents a vIOMMU exposed capability. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- MAINTAINERS | 1 + hw/pci/pci.c | 11 +++++++++++ include/hw/iommu.h | 16 ++++++++++++++++ include/hw/pci/pci.h | 23 +++++++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 include/hw/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index 1842c3dd83..d9fc977b81 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2302,6 +2302,7 @@ F: include/system/iommufd.h F: backends/host_iommu_device.c F: include/system/host_iommu_device.h F: include/qemu/chardev_open.h +F: include/hw/iommu.h F: util/chardev_open.c F: docs/devel/vfio-iommufd.rst =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c70b5ceeba..df1fb615a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2992,6 +2992,17 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +uint64_t pci_device_get_viommu_cap(PCIDevice *dev) +{ + PCIBus *iommu_bus; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); + if (iommu_bus && iommu_bus->iommu_ops->get_viommu_cap) { + return iommu_bus->iommu_ops->get_viommu_cap(iommu_bus->iommu_opaqu= e); + } + return 0; +} + int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is_read, bool is_write) diff --git a/include/hw/iommu.h b/include/hw/iommu.h new file mode 100644 index 0000000000..e80aaf4431 --- /dev/null +++ b/include/hw/iommu.h @@ -0,0 +1,16 @@ +/* + * General vIOMMU capabilities, flags, etc + * + * Copyright (C) 2025 Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_IOMMU_H +#define HW_IOMMU_H + +enum { + VIOMMU_CAP_STAGE1 =3D BIT_ULL(0), /* stage1 page table supported */ +}; + +#endif /* HW_IOMMU_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index df3cc7b875..a11ab14bdc 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -453,6 +453,19 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number of the PCI device. */ void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); + /** + * @get_viommu_cap: get vIOMMU capabilities + * + * Optional callback, if not implemented, then vIOMMU doesn't + * support exposing capabilities to other subsystem, e.g., VFIO. + * vIOMMU can choose which capabilities to expose. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * Returns: 64bit bitmap with each bit represents a capability emulated + * by VIOMMU_CAP_* in include/hw/iommu.h + */ + uint64_t (*get_viommu_cap)(void *opaque); /** * @get_iotlb_info: get properties required to initialize a device IOT= LB. * @@ -633,6 +646,16 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_device_get_viommu_cap: get vIOMMU capabilities. + * + * Returns a 64bit bitmap with each bit represents a vIOMMU exposed + * capability, 0 if vIOMMU doesn't support esposing capabilities. + * + * @dev: PCI device pointer. + */ +uint64_t pci_device_get_viommu_cap(PCIDevice *dev); + /** * pci_iommu_get_iotlb_info: get properties required to initialize a * device IOTLB. --=20 2.47.1