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a="57974037" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974037" X-CSE-ConnectionGUID: +yhSRuX4Q9SrJk7IOUrWRA== X-CSE-MsgGUID: SQLPJVImSXyUJ14O97GJ0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647983" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v3 12/20] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Date: Tue, 8 Jul 2025 07:05:53 -0400 Message-ID: <20250708110601.633308-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752007797199116600 Content-Type: text/plain; charset="utf-8" FORCE_RESET is different from GLOBAL_INV which updates pasid cache if underlying pasid entry is still valid, it drops all the pasid caches. FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, only used internally in system level reset. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 9 +++++++++ hw/i386/trace-events | 1 + 3 files changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cf2c959b60..cf263498db 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,6 +87,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); + static void vtd_panic_require_caching_mode(void) { error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " @@ -391,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_lock(s); vtd_reset_iotlb_locked(s); vtd_reset_context_cache_locked(s); + vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); } =20 @@ -3171,6 +3174,8 @@ static gboolean vtd_flush_pasid_locked(gpointer key, = gpointer value, /* fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_FORCE_RESET: + goto remove; default: error_setg(&error_fatal, "invalid pc_info->type for flush"); } @@ -3211,6 +3216,23 @@ remove: return true; } =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_reset(); + + pc_info.type =3D VTD_PASID_CACHE_FORCE_RESET; + + /* + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remo= ve + * which will free all vtd_as instances except those created for PCI + * sub-system. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, + vtd_flush_pasid_locked, &pc_info); +} + static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, dma_addr_t pt_base, int start, @@ -3344,6 +3366,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_FORCE_RESET: + /* For force reset, no need to go further replay */ + return; default: error_setg(&error_fatal, "invalid pc_info->type for replay"); } diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 621e1f6947..887f93bac9 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -568,6 +568,15 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, VTD_PASID_CACHE_PASIDSI =3D VTD_INV_DESC_PASIDC_G_PASID_SI, VTD_PASID_CACHE_GLOBAL_INV =3D VTD_INV_DESC_PASIDC_G_GLOBAL, + + /* + * Internally used PASID cache invalidation type starts here, + * 0x10 is large enough as invalidation type in pc_inv_desc + * is 2bits in size. + */ + + /* Reset all PASID cache entries, used in system level reset */ + VTD_PASID_CACHE_FORCE_RESET =3D 0x10, } VTDPCInvType; =20 typedef struct VTDPASIDCacheInfo { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ae5bbfcdc0..c8a936eb46 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 --=20 2.47.1