From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009935; cv=none; d=zohomail.com; s=zohoarc; b=Jp6GKIK2cJJJGDzLyQLGulYjhqyhJOxBjQnTgnURdKuiph87NOUV1TlXDkX8fj/VDSYfdJhDzfX8yjB9Bz5neU+dlvcD694bctJ313+avuyteQ38gtQc8obMyIKHASDyIsKZwO8Y/1F+yPGuyqWEw2DVNTfjjmrgLtfqguaa0YM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009935; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5jWsMIdzImhkq9wAF8wUzwoy+DvTNC3FaXR583xDLrk=; b=W8liA5VoDsbae7ktEc9QTzYH2SB9EmYnDed3TGWlyBf6J2fhTyZXVMStPrPUpgPh8RNxyP5H8Qi0NsOc9jZIx3IATVh0A5fe4sZh+QOvrA3tmA14CFcUMbXcHaAO/M69ZyKXD85D/LVAGdRGpqfZ0vuRC5aam9dn166qwL/OxUM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009935579301.1212046018228; Tue, 8 Jul 2025 14:25:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFC4-000793-Sl; Tue, 08 Jul 2025 16:45:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqi-0006zM-Rm for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:32 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqb-00082f-2l for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:27 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:17 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002362; x=1783538362; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eksDTVl35dhaVnF4chtZcohGFCQS9M8yqR97AuGfJFY=; b=fcF+FKE4zjQav4Pt85HLmUmCswdJhwD7K6UUUMJziWRi8yWY2IEpI/5/ RMhRoPd6nmc+N7SOxqJWXB8pvJBFKABQZP7vBuYTC2L80Y8ZcKTbkHxVS 66r145OxtjM3O3pQD4c1fOMgbjY7RkzTFItKuRnuhJfPa/n6DcrKxRduz 8RuTr5w64NZM5R/Corw+Ao9YCzgEfdVDt9GRi9sMjwgHQZKOHDuOQyAnY gidG0gHbi/N+pzYF8XTLjoJWM0inj6+jl9cwvSWNdE22vprbz1aYqjUv+ je5fo12iupiDwbX6Q8FDxZrJsWe/Rbi/NGeK+xSEOxouhu1hf9X+YCcGm Q==; X-CSE-ConnectionGUID: xLH7cQaoT0WXpsLDzoiS4Q== X-CSE-MsgGUID: ecJVo2MBQlG7B9yXL8T/qg== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973899" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973899" X-CSE-ConnectionGUID: ThmKtk4xQ/uoXwAYkGT2uw== X-CSE-MsgGUID: LGOGSi8gSGazuLWh4qu6PQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647920" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 01/20] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Date: Tue, 8 Jul 2025 07:05:42 -0400 Message-ID: <20250708110601.633308-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009937576116600 In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 69d72ad35c..f0b1f90eff 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) @@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret =3D vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008352; cv=none; d=zohomail.com; s=zohoarc; b=n0lWGtbTxX0cQduQnCsITk/RnYrAF2fFmSvhH+KgHHvlHvXMaE/4IVAwInJ56/DT1pJGh27pOdsQ2ivvQuITNt0fEYU9og6ImW6tYP1Kw/fIwJCPYgCmdf1qQ7/HZKxxKxK69FCZTK1A17OXWosIfLOK96A7MdI26OPBvMM2Q7s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008352; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NcCyDGJaKt5xKc335hTGm7eSsMTtM59bmBXi4hkRmjk=; b=W8ZYIEKZsNLqnS0hSDR4IFqGSH2VTETy8/6nVjHWPs9tzP6Yvg9v3IxU59LDpAhAfaHFwE5KZwkP7/Gc/xyErEzktsxwp4ckpD4kGWdFSUVqJMAgZUVQBUtYQL++p1NqxXoXswXAVtQF/e6vsbA1/JSdm0HN9rTBGFuTvU9zlkw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752008352711258.57596649095024; Tue, 8 Jul 2025 13:59:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFC-00023S-La; Tue, 08 Jul 2025 16:48:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrW-0008Hg-PB for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:23 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrQ-00086x-KZ for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:17 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:21 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002413; x=1783538413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2RiIr4+eavDZWdSlMVoyWZlpg5A1dJBD7bC9x9Ek84g=; b=mUdYXdEH74m9pr4As/QK19QztLVqNjqLSEAQ32MMAN6d45xEBqZ8r3U6 b3fScNsIkLDaN49WOG91cuIAHh+x+4p4pVx8HDZ61/2wnOug+gCgyP4P6 XCQlhDz4N6OT7z0jhwQeKIJkV8lCMA8kVko1PH3CgZYejOJSFc3+sBd4r wgPm1maKHlmP6ZZ6ktiUQ6jXOIBdcrfUFsEBhZj76yZBvgJNdZMIGwOJg 5dCsS/iA8qC911lgJPMVXr2qD15oBnzKSyBEsjjYGwx7uupUw5ZsXa9sb 8PGYDoJkGe7GnZfAIf7bdpWQOrspd2tCMrqYtrqtGam8tHFxBfA10R64w A==; X-CSE-ConnectionGUID: s3qhotHNRyGUwudavqt10g== X-CSE-MsgGUID: WGBnYywYSFOUJFYQIUJPHA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973910" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973910" X-CSE-ConnectionGUID: vODf6lIERFep+cdj9Cjllw== X-CSE-MsgGUID: 0c6MqHjBQFyehb393xa7Cw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647930" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 02/20] hw/pci: Introduce pci_device_get_viommu_cap() Date: Tue, 8 Jul 2025 07:05:43 -0400 Message-ID: <20250708110601.633308-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008353696116600 Content-Type: text/plain; charset="utf-8" pci_device_get_viommu_cap() call pci_device_get_iommu_bus_devfn() to get iommu_bus->iommu_ops and call get_viommu_cap() callback to get a bitmap with each bit represents a vIOMMU exposed capability. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- MAINTAINERS | 1 + hw/pci/pci.c | 11 +++++++++++ include/hw/iommu.h | 16 ++++++++++++++++ include/hw/pci/pci.h | 23 +++++++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 include/hw/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index 1842c3dd83..d9fc977b81 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2302,6 +2302,7 @@ F: include/system/iommufd.h F: backends/host_iommu_device.c F: include/system/host_iommu_device.h F: include/qemu/chardev_open.h +F: include/hw/iommu.h F: util/chardev_open.c F: docs/devel/vfio-iommufd.rst =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c70b5ceeba..df1fb615a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2992,6 +2992,17 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +uint64_t pci_device_get_viommu_cap(PCIDevice *dev) +{ + PCIBus *iommu_bus; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); + if (iommu_bus && iommu_bus->iommu_ops->get_viommu_cap) { + return iommu_bus->iommu_ops->get_viommu_cap(iommu_bus->iommu_opaqu= e); + } + return 0; +} + int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is_read, bool is_write) diff --git a/include/hw/iommu.h b/include/hw/iommu.h new file mode 100644 index 0000000000..e80aaf4431 --- /dev/null +++ b/include/hw/iommu.h @@ -0,0 +1,16 @@ +/* + * General vIOMMU capabilities, flags, etc + * + * Copyright (C) 2025 Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_IOMMU_H +#define HW_IOMMU_H + +enum { + VIOMMU_CAP_STAGE1 =3D BIT_ULL(0), /* stage1 page table supported */ +}; + +#endif /* HW_IOMMU_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index df3cc7b875..a11ab14bdc 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -453,6 +453,19 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number of the PCI device. */ void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); + /** + * @get_viommu_cap: get vIOMMU capabilities + * + * Optional callback, if not implemented, then vIOMMU doesn't + * support exposing capabilities to other subsystem, e.g., VFIO. + * vIOMMU can choose which capabilities to expose. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * Returns: 64bit bitmap with each bit represents a capability emulated + * by VIOMMU_CAP_* in include/hw/iommu.h + */ + uint64_t (*get_viommu_cap)(void *opaque); /** * @get_iotlb_info: get properties required to initialize a device IOT= LB. * @@ -633,6 +646,16 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_device_get_viommu_cap: get vIOMMU capabilities. + * + * Returns a 64bit bitmap with each bit represents a vIOMMU exposed + * capability, 0 if vIOMMU doesn't support esposing capabilities. + * + * @dev: PCI device pointer. + */ +uint64_t pci_device_get_viommu_cap(PCIDevice *dev); + /** * pci_iommu_get_iotlb_info: get properties required to initialize a * device IOTLB. --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009219; cv=none; d=zohomail.com; s=zohoarc; b=BGptVXqiVA5vY/vyRJI1NwdF2kDNoh+ZnXGWpdDgWsvszfbbuRI8UabgZw6ARE0ABkKyuuOcIlrEG6RakeW8wlYBnldijJjAm0SlUKOcAx5cyYkdiWTIUH/afI9bykVujzXBN2jpBtuf3oarsaosN1TtNmLta3RwHbKZIxcwxGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009219; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xBbogE+VUV0CazcV2NAbdGSnnwHYLK9B22LzeAJLgXU=; b=dBHwRHnFtOIc5YBVn2Kq3Y/w1T/WZ29L+5fmC5154Q9D05AITnvNmBPU49NMap2b7bHb8L9grQNZQ+5barvtSkEaTcKp0MR+5EByclk/JuIsGArDxXBbIDX/acZA3pWzsCdp18brWR2DFz9YfU/CnsjlMu7m5dP5wVqsxxlFu24= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17520092196130.39722602399012885; Tue, 8 Jul 2025 14:13:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFET-0006JS-Jh; Tue, 08 Jul 2025 16:48:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqq-000784-I7 for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:38 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqm-00082f-Eq for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:36 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:25 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002373; x=1783538373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CTUex6E1/CDtLReZCOrMYpJ0NzdK+F9clgJengK6Qgk=; b=Fm7T2kexeNfKqkK+mKfN9im9o4clfDc4dbTdb2ZHgOtRvpEug7tEenQl 5ceZ5rq04PcBi4/AkL38VX+Wxk4z1kkEzwatXZN0stSlkIRhyQUYv6z8T EIYpYT7Qp3ujmyrZ7AHe3aeLFJVk8lT1cUZVtR4Xquf/sMLIFyftxJUPL wEGyeJVzqcPNNt1IyEgAa5A0t2ovreTGMjWcXZfQMoQlVd6obpLXpzbyE /IE8//mHq9WHLt1Ia+jdbBLINiBXynggDC1R/cMS0JmFbkm1lsUO2uVKM L1adx0eVM6OJa+zsNE3OiZkeNCgjzHGS+3JmVFmKieK4Kn4KnGPsg+3dd w==; X-CSE-ConnectionGUID: Tf11lw3oRDSVIKCSa0m3kw== X-CSE-MsgGUID: fZNYLswCQZGi/8GgZBDxoQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973923" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973923" X-CSE-ConnectionGUID: g+Wyd9/dQCKh65lzavcOXw== X-CSE-MsgGUID: cV1TMnLMRa2p6gwB6o+EvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647935" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 03/20] intel_iommu: Implement get_viommu_cap() callback Date: Tue, 8 Jul 2025 07:05:44 -0400 Message-ID: <20250708110601.633308-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009220789116600 Content-Type: text/plain; charset="utf-8" Implement get_viommu_cap() callback and expose stage-1 capability for now. VFIO uses it to create nested parent domain which is further used to create nested domain in vIOMMU. All these will be implemented in following patches. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f0b1f90eff..702973da5c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,6 +24,7 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/sysbus.h" +#include "hw/iommu.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -4412,6 +4413,16 @@ static void vtd_dev_unset_iommu_device(PCIBus *bus, = void *opaque, int devfn) vtd_iommu_unlock(s); } =20 +static uint64_t vtd_get_viommu_cap(void *opaque) +{ + IntelIOMMUState *s =3D opaque; + uint64_t caps; + + caps =3D s->flts ? VIOMMU_CAP_STAGE1 : 0; + + return caps; +} + /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -4734,6 +4745,7 @@ static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, .set_iommu_device =3D vtd_dev_set_iommu_device, .unset_iommu_device =3D vtd_dev_unset_iommu_device, + .get_viommu_cap =3D vtd_get_viommu_cap, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008353; cv=none; d=zohomail.com; s=zohoarc; b=JWLYElrOxXFbG8Yx+YHy8aKHxYSDqFmKj50+nzgqStCe/30gAE2Zaoi9MYu7A/IZcSdYsB61VRxQuI4i1anstLHA6BMB5TJUTWNgyFd1uksvNXc3NRk4YQeqf3Ju7zWr17WhqeJjtf71eNn8GWV+m2DYdXuGy22BH0QYqnD4kAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008353; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r835l3IGSPwyii5C40MLEkwnH61I0ExJ9MomphUkm7w=; b=iyAM2V+xjUvua3EanwShoRL06CAa6QzlPj/tbmDglT3izdltW/fGXNOGKg4MyrdRdPuXYkQAtj0D2rcVQVZzhP7N3oyM1qA8ZmoM4SzCvskhDuQsyIyaNF5wiD2S6XM0gxN3y92y7hgipYVLQmIXVgzh7qq2MMVwxf/NGLer5ds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752008353843595.4656842104448; Tue, 8 Jul 2025 13:59:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFCq-0000k7-KX; Tue, 08 Jul 2025 16:46:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqy-0007E4-Qc for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:47 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDqq-0008BN-DM for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:19:42 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:29 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002377; x=1783538377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pVh6PrV0RlHt3w2Val9nzK4L2WgoD2bK1GkhXjQD/0Y=; b=I56MNao8MvERhBLR1orqVIfujUsUU66JHwR7VFBZCPfxPtizjha55Anb nXWJR14vt8rKWSNNli2LXKphwbHSDrR00qTy5TkEgCqcpJULQ6zC45dZX WNWM6PHgdgVBnJnHN6UJXlIXZTP/4S5e6f7MIfxHVaDwMlX7H5t3QW1xc 5Q/7p3/oD2RHq3M/mRYyVT3JFS6RcBrx8WeZRSMNTle9/ebHH6ibkYpp5 Ckq4tx+Wkxnx40NJKKLhnCp9+S7zWvQHEAielZyECcBipQhcjumO9fjBO 6fVX5fomTBnQRkIGhwsGmA9soz+jBL7cxV1eHQRWi9AaN0G4ukm6r9gqD g==; X-CSE-ConnectionGUID: afxYSL9lRdyZGDsxKauINA== X-CSE-MsgGUID: oA9iOcCjS++YMhiyRZo1Mw== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973933" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973933" X-CSE-ConnectionGUID: wm12UT8XQju+WLaUeln8TA== X-CSE-MsgGUID: ChncqA8qQf2Ibb7QOy6dTg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647939" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 04/20] vfio/iommufd: Force creating nested parent domain Date: Tue, 8 Jul 2025 07:05:45 -0400 Message-ID: <20250708110601.633308-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008355395116600 Content-Type: text/plain; charset="utf-8" Call pci_device_get_viommu_cap() to get if vIOMMU supports VIOMMU_CAP_STAGE= 1, if yes, create nested parent domain which could be reused by vIOMMU to crea= te nested domain. It is safe because hw_caps & VIOMMU_CAP_STAGE1 cannot be set yet because s->flts is forbidden until we support passthrough device with x-flts=3Don. Suggested-by: Nicolin Chen Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/vfio/iommufd.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 48c590b6a9..c172c177fc 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -20,6 +20,7 @@ #include "trace.h" #include "qapi/error.h" #include "system/iommufd.h" +#include "hw/iommu.h" #include "hw/qdev-core.h" #include "hw/vfio/vfio-cpr.h" #include "system/reset.h" @@ -379,6 +380,19 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } =20 + /* + * If vIOMMU supports stage-1 translation, force to create nested pare= nt + * domain which could be reused by vIOMMU to create nested domain. + */ + if (vbasedev->type =3D=3D VFIO_DEVICE_TYPE_PCI) { + VFIOPCIDevice *vdev =3D container_of(vbasedev, VFIOPCIDevice, vbas= edev); + + hw_caps =3D pci_device_get_viommu_cap(&vdev->pdev); + if (hw_caps & VIOMMU_CAP_STAGE1) { + flags |=3D IOMMU_HWPT_ALLOC_NEST_PARENT; + } + } + if (cpr_is_incoming()) { hwpt_id =3D vbasedev->cpr.hwpt_id; goto skip_alloc; --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752007821; cv=none; d=zohomail.com; s=zohoarc; b=dBjKpgCE3VWZ9sceSJEp4DFNiSr/GvCZ8mVLTsEKdAAP6DQd4Vkdbddxa88l/Pc8XGk9iw4LomsJpxZGrj6R2hRFCZVTtOyD2g2Gsod21AfndEd84sh2+AhgH6wpqH4V54PAZCAjMWlAxt1hQVnAy+g/Ce40Qieg/IearRq9N3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752007821; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uxpD0/KCa/f2BBMZYdA11DNQljNAFQua8Poa58vafZM=; b=L9zI+LFrJb4Wq+zUj60Gb7frlZOtFCa7Un03HWT8Jbyr+rdpLKGetLNRglUFdOhxlJmKx3FJKIwk/HFvYrhEm6xt6nvzmX/a9FFVhrr3ZKPiTmC0vJsASc+Zw6yUipVbYQBViEBILLwWdI9BLvWd2ScmBm4GVMMeKJIxQzIsr7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752007821526350.4784104944041; Tue, 8 Jul 2025 13:50:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFF9-0001gp-BN; Tue, 08 Jul 2025 16:48:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrQ-000889-EE for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:16 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrI-00082f-Or for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:09 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:33 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002405; x=1783538405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KsOnCsI5jC90DeVaUlcU5vLyuj8uWYtnJUXix5a5El0=; b=GgTuu5wIKeo/QciHxHhZsDLjd2N/r8azj+83WWEq2LdrVvjl2ioudmJ7 HVU+hpVyFyzX6JBR7tAPkXjYVzO27eHxrv33iPZDpQ4YKHAC1F9O/yY2e hAwXpz5/pGnGCig8cL/iUhmgShoKAFj0eN6x3M29DsE3fx2Oj43ba5x4x /Q6gg4uCcuxnfvpcJb/Fs5iAb99PmbItmE5gM+heuAWXiq2yYlNMmPj2W FOrieVQfTtUwMr5MF+pyjkj2V7vX2oq/3cuCw/ilSt+yJ3DpuoN6TQL4c bWTCKGrm8qEGQoWdKSdSDxaljlks8BXzG3rLKse7pyXtN1mgSjF3+C2Rl A==; X-CSE-ConnectionGUID: t6fLUWEoQ9KJJW/dBCX+TQ== X-CSE-MsgGUID: nE2SzAB+T5SoqZiBiJM1kQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973945" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973945" X-CSE-ConnectionGUID: 6WJx2Jt/Szyfu7BoEiw2EQ== X-CSE-MsgGUID: TtnH6KeAR8mwIngJoR3ypA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647946" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 05/20] hw/pci: Export pci_device_get_iommu_bus_devfn() and return bool Date: Tue, 8 Jul 2025 07:05:46 -0400 Message-ID: <20250708110601.633308-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752007823352116600 Content-Type: text/plain; charset="utf-8" Returns true if PCI device is aliased or false otherwise. This will be used in following patch to determine if a PCI device is under a PCI bridge. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/pci/pci.c | 12 ++++++++---- include/hw/pci/pci.h | 2 ++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index df1fb615a8..87f7c942b3 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2857,20 +2857,21 @@ static void pci_device_class_base_init(ObjectClass = *klass, const void *data) * For call sites which don't need aliased BDF, passing NULL to * aliased_[bus|devfn] is allowed. * + * Returns true if PCI device is aliased or false otherwise. + * * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device. * * @aliased_bus: return aliased #PCIBus of the PCI device, optional. * * @aliased_devfn: return aliased devfn of the PCI device, optional. */ -static void pci_device_get_iommu_bus_devfn(PCIDevice *dev, - PCIBus **piommu_bus, - PCIBus **aliased_bus, - int *aliased_devfn) +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn) { PCIBus *bus =3D pci_get_bus(dev); PCIBus *iommu_bus =3D bus; int devfn =3D dev->devfn; + bool aliased =3D false; =20 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { PCIBus *parent_bus =3D pci_get_bus(iommu_bus->parent_dev); @@ -2907,6 +2908,7 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, devfn =3D parent->devfn; bus =3D parent_bus; } + aliased =3D true; } =20 iommu_bus =3D parent_bus; @@ -2928,6 +2930,8 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, if (aliased_devfn) { *aliased_devfn =3D devfn; } + + return aliased; } =20 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index a11ab14bdc..8795808155 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -641,6 +641,8 @@ typedef struct PCIIOMMUOps { bool is_write); } PCIIOMMUOps; =20 +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn); AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009740; cv=none; d=zohomail.com; s=zohoarc; b=RzQfUuqaggLS2ha8eaRfjzMlQksSGfo5bK+Rih7e/RBrqrW/Ud2bmuNruBK/4P6f0K7Fd6+GD5WVbrVn33f4or1Tsa5Nsf6y5IgmDw/5TP/NwQE0fLN+cSO2jsRxd9p6EspuDEsqclTTLJgQAzz1eHJvJzBsbg09SphvzWWlr4U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009740; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=v9ZDFY6dgJlpm0Vsve51IEJsQ28U5xgJqPtEUbUg5ws=; b=ntCLQZB2un480/1hra2lh0vQEA+ur9aKWjH8N2J5y9CRcUVd0mEU++Xkz3zSXDboD5rrAEsUjR3BlOcoyU0yYP6vww0QzhP/7fDuTQu0Y8r6ViWx6O75XRasNLbYKjH+zjB+nPLMWPnoO048dfcrQaZJoHglZAqm/HDMMxbEAjA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009740351339.5350528831983; Tue, 8 Jul 2025 14:22:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFE-0002D3-5T; Tue, 08 Jul 2025 16:48:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrb-0008SS-Az for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:24 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrQ-0008BN-BI for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:18 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:37 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002413; x=1783538413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JvvhniYOGljHl/kopdCojhByjmKO1fjRQmn9E59WiUY=; b=gZnIDcaYJg9GtvOUSsrIfmNzkLQ1hzkxdYMxoLXwUszyuonRWJHzjhM8 0usHviO4mIY3VUHGhTmN3mm7p322Qa4jLEWLGTQ2ztdxx+sx6kCrS/69h 6V9fWhiz7aUqYRH7BHQjwh6sTARegwQjHNA74d8k+o3RDVMW3lBWpymXi 2lptFxlFqyYbgxcw0OGqo668As5RU4r4eDdoxDFpn2kqS3vK9Uw/FxfBG VgBrpURJkIBVjPyes0blKcoR+f3oVesN3CLh9Rjvn41E5JFNNrvh/r04S PRVUMt+/kLkwKmrNxob9UEwsaRj3/cfh4sOJI6L+AG6siyCJp7Q+mnhhU g==; X-CSE-ConnectionGUID: EY0Sa3PwRHOpfgOt6JVfKA== X-CSE-MsgGUID: JdjI7dE/Tpi/AnD5dM/uoQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973960" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973960" X-CSE-ConnectionGUID: egwCBXf5QbOpKzbG/n3EaQ== X-CSE-MsgGUID: cOZ9T2MbRcap460ODKMmBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647949" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 06/20] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Date: Tue, 8 Jul 2025 07:05:47 -0400 Message-ID: <20250708110601.633308-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009741675116600 Content-Type: text/plain; charset="utf-8" Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 15 +++++++++++++-- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 702973da5c..e90fd2f28f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gcons= tpointer v2) =20 static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod =3D v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } =20 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4360,6 +4363,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, @@ -4376,7 +4380,14 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, return false; } =20 + vtd_hiod =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus =3D bus; + vtd_hiod->devfn =3D (uint8_t)devfn; + vtd_hiod->iommu_state =3D s; + vtd_hiod->hiod =3D hiod; + if (!vtd_check_hiod(s, hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } @@ -4386,7 +4397,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, new_key->devfn =3D devfn; =20 object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); =20 vtd_iommu_unlock(s); =20 diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index e8b211e8b0..7aba259ef8 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" =20 /* * Intel IOMMU register specification @@ -607,4 +608,10 @@ typedef struct VTDRootEntry VTDRootEntry; /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 =20 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..50f9b27a45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -295,7 +295,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008059; cv=none; d=zohomail.com; s=zohoarc; b=ZyMcLXtZkRGEuqfaRNlF8wC9wadpeLz5wz2tlY+Hy8gwJuT9eeWHXK32f1VYYCzpGqvj9zc5/DZGHkq/JXpH9TBLkJttIgJxKcZ3bLPS4W29rzYJ6K9rPv2RpIy6SKQ549eIUBERDBottmxYp0FplNQQNWKd1ua8wYOWM7oyv9Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008059; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2rTWRKQGWnW15nbVfOOyVRGepyak/G6BwcwIHWnkg5w=; b=RhLZ6p4CrwwUXsELZES10Taxg3S83Tcs2yl6P3ojbQZbEiU4sZKcH/OHs2WYXlIhYULkZhWdAZHMmMpx0ouCsrJjOwwd00NXD+kz3Bg++S/I4d3g7jU7YUVHlEjYKnzc7MeUoh8bYIlmJ9hBHz0mqJ8AJEkrf16WtY+f2LD7oAo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752008059552963.1241011360876; Tue, 8 Jul 2025 13:54:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFO-0003BB-3E; Tue, 08 Jul 2025 16:49:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrm-0000Ao-76 for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:36 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrd-00082f-0I for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:29 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:42 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002425; x=1783538425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SvDiTBbSsH02gNnCb68XP674kRfw4vNbN+I98mfwt5g=; b=jeAmLCh4SgH7UmlhniEWWxw9tiWV+EiV+8ABoqSUvPDkj+Df5fhP2/1h b4HtJXf2YpDbDGLmCAqpUNN9NFqUrn2dozVxF+5LNU16ilZmcNEgLCgha qr6uPO1TY5btetg95aaABm+3gpA19wjKCE8Hfk6iL//CDA3M3QDJQG6b1 JyLyX8uv+UJ1Lf5bLEqo2tCoqJGuNfx0f5iGKNzvH1K1VKxsl9wKxr21C 504Jsjy+5u6Hi3gSvEx61F4Fb4aVvPTZmqC5DXA5YRJQRD0+2438gO6jF zYeQtWb2PuTT73IXq+Dw56ywwAgggMkvqM5C8uIseVjhzRG3/CMmTxORO g==; X-CSE-ConnectionGUID: XDxR6owAQqKBYNrWs+AHiQ== X-CSE-MsgGUID: avuihnD+TxSHRGeqW7SUTQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973976" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973976" X-CSE-ConnectionGUID: Ik+5IbvGRNmGzmQV74N+nA== X-CSE-MsgGUID: SZWEUb1kRxKMkSyaRMtHhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647953" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 07/20] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Tue, 8 Jul 2025 07:05:48 -0400 Message-ID: <20250708110601.633308-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008059861116600 Content-Type: text/plain; charset="utf-8" When vIOMMU is configured x-flts=3Don in scalable mode, stage-1 page table is passed to host to construct nested page table. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest stage-1 page table could be used by host. For instance, vIOMMU supports stage-1 1GB huge page mapping, but host does not, then this IOMMUFD backed device should fail. Even of the checks pass, for now we willingly reject the association because all the bits are not there yet. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 30 +++++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e90fd2f28f..c57ca02cdd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -40,6 +40,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" +#include "system/iommufd.h" =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -4355,7 +4356,34 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, return true; } =20 - error_setg(errp, "host device is uncompatible with stage-1 translation= "); +#ifdef CONFIG_IOMMUFD + struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; + struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + + /* Remaining checks are all stage-1 translation specific */ + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + if (caps->type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", + caps->type); + return false; + } + + if (!(vtd->ecap_reg & VTD_ECAP_NEST)) { + error_setg(errp, "Host IOMMU doesn't support nested translation"); + return false; + } + + if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) { + error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); + return false; + } +#endif + + error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); return false; } =20 diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 7aba259ef8..18bc22fc72 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -192,6 +192,7 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) +#define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009922; cv=none; d=zohomail.com; s=zohoarc; b=Uat5k+2/mOLVdocg7VXNRFzjBrxqZAyuj4a/iazUqJaI8GJZLA0ijNKcGIzA0AuNfU6dh6kBs2VLS8BcfiTlqWYHHwe/wwnA45CFzZLda22pAwoP8ZxtRuTUw0pDDtBDliNm5yZ5C7uohxmvMLv9AJwPL6Xs2tICto/5nHAt2b8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009922; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MjLv+FoxpDkA3GyArRSK9pYsOf2hb65x6I5uweYSVJs=; b=EIypkHiKug1FylrjfQ+MZYlhGUvUXUQgA7701JZBWNUNivA9UlSCEKbzbUJoyYxFJcrCIChnyqK5w30KZh1F/xPFMmM8t91fHtbeelEjIynzUtNnXe59hWjEwZd2wbXHcZaKj/6wGXowqD+WcNp6qFHeilCEgETasdaz3cE4WV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009922476167.74849928096444; Tue, 8 Jul 2025 14:25:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFL-0002xJ-BU; Tue, 08 Jul 2025 16:48:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrl-0000Ag-1Y for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:36 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrc-00086x-Vc for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:29 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:46 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002425; x=1783538425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zw4qGRcQAiVduttowO32/gJYLffv7HLd2//CQPYhNmQ=; b=aQiJ/uB59obkVkwHgJjsmYwhsQYD9xFYZzcMsEjZsmmjOOciTQiJVRYF GXdABF5BaTe975pYM/jj1eRjWj+0zlXXo98h70zTdx3NmDgJljgaLVR9P Xf++fmD9UeRT2evTa2djNemCkC+tsS/MhoaYZvDIOTX7bnoIze/a8xsbP fk1V3vUSPVL/2HYSuBIjIvr4mG7q62pL/yzRZXULI87qWj4nN6vbcHvZv IaxNtdI5Mk4aIxz82hobGy2Hat26D4/aY6sj8dMMPiLLVfJ+K82KVr2eu YD13rce/xmfOpauJyNsZ9QczF/zxV4UTIDj9DA6WkxqcE+DIgoi+ORo/z A==; X-CSE-ConnectionGUID: ObZAJ5NSRVyAnUrXMvmyxg== X-CSE-MsgGUID: 6P3kxEJCRRKvamwlWUI3hA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57973992" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57973992" X-CSE-ConnectionGUID: H92wImjtQ+yfPYoYPmsOdQ== X-CSE-MsgGUID: AQMFwj8aT8WkYypwQfx5kw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647960" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 08/20] intel_iommu: Fail passthrough device under PCI bridge if x-flts=on Date: Tue, 8 Jul 2025 07:05:49 -0400 Message-ID: <20250708110601.633308-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009923365116600 Content-Type: text/plain; charset="utf-8" Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge, because they require different addre= ss space when x-flts=3Don. In theory, we do support if devices under same PCI bridge are all passthrou= gh devices. But emulated device can be hotplugged under same bridge. For simpl= ify, just forbid passthrough device under PCI bridge no matter if there is, or w= ill be emulated devices under same bridge. This is acceptable because PCIE brid= ge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c57ca02cdd..15f4393d6f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4330,9 +4330,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -4359,6 +4360,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, #ifdef CONFIG_IOMMUFD struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + PCIBus *bus =3D vtd_hiod->bus; + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), vtd_hiod->d= evfn); =20 /* Remaining checks are all stage-1 translation specific */ if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { @@ -4381,6 +4384,12 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); return false; } + + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device under PCI bridge is unsupported " + "when x-flts=3Don"); + return false; + } #endif =20 error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); @@ -4414,7 +4423,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752010011; cv=none; d=zohomail.com; s=zohoarc; b=CXi757gxrFzE9W/qjrfo0IsT6kZl3IiAkiSXez0KBQiND66kQKwSliDQ+5RvIuK5VbTkLkgoPxeMEe+14VA3mplX3I8mDB2erUSCGKWZ3iDgbEmdQ8ehDj7mzK8tMl25I1KWptMNPYoGV55C1BDcvLwv+kwNlYsBnKN/y875754= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752010011; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7+Ik6sPW7T1XpG5HALWQQjK1OhORcMCvfD4yRwSRGkg=; b=nQndD2Enh1r5vkbjTpj5Yp/vgn9UOQCaKXAjTO/blkTaqCtssQKZeOcQK2Hj51zvPn3WsowaqBOTDnDuGtRGwoIFIizo1pKvqMn5x1N95JqPN+iQ0rHOvlP5CBrau1N7MRGIFIR6X6Q8Sx0Vp1++07aHCdHpy7gnmbm+8QciLKQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752010011984527.1918249346445; Tue, 8 Jul 2025 14:26:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFH-0002W9-Le; Tue, 08 Jul 2025 16:48:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrh-00007s-Bl for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:36 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrb-0008BN-UV for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:26 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:51 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:46 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002424; x=1783538424; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YN0+Qrax2R2/lK61bIWyywAa1Rg9ofrCC/jNHMSnzkg=; b=Ld9EhXVjiUwOk9OX0/ZOf5hcUTOKWBxbliTUG3PaAz2e4ipMIgrg0Z6j C7f4JsD6ZhWJbUS4gpdEcIBUyueA3EmHQXwJ0OYZiHtJCfg2yXNqaS+aq 4R25uklmvp0ISO6YbgPLNttpVciuqv8u2aY6SZ+Hhz+leV33w63mMjWy4 qwDbftn2ikj1Mu84ZCwEnf2q2A62HEuftwYqQMbvpCLLvjUOdfzYtJGul KjUg9/IuTrbV0GnJT6UC88twqC4Nnl7JesN09s+AxoM8g6eS7B6Yvh6Wy Xjj394Fc0k/G/tQCvkOsHntitNohPWrTq1AA++L45AFld5lOnY3mRDiHL A==; X-CSE-ConnectionGUID: xxniA8btTiuthwLjHyrYEQ== X-CSE-MsgGUID: N7gOda2vTBmflCT5th6xdw== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974005" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974005" X-CSE-ConnectionGUID: hK44WR2KTFGJU6LuIKQCsw== X-CSE-MsgGUID: WArYOA3xQPuYb+sLVJpQjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647964" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 09/20] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Date: Tue, 8 Jul 2025 07:05:50 -0400 Message-ID: <20250708110601.633308-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752010012641116600 Content-Type: text/plain; charset="utf-8" PCI device supports two request types, Requests-without-PASID and Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's pasid to index pasid table. So we need to translate between PCI's pasid and IOMMU's pasid specially for Requests-without-PASID, e.g., PCI_NO_PASID(-1) <-> rid_pasid. For Requests-with-PASID, PCI's pasid and IOMMU's pasid are same value. vtd_as_from_iommu_pasid_locked() translates from BDF+iommu_pasid to vtd_as which contains PCI's pasid vtd_as->pasid. vtd_as_to_iommu_pasid_locked() translates from BDF+vtd_as->pasid to iommu_p= asid. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 15f4393d6f..38e7f7b7be 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1602,6 +1602,64 @@ static int vtd_dev_to_context_entry(IntelIOMMUState = *s, uint8_t bus_num, return 0; } =20 +static int vtd_as_to_iommu_pasid_locked(VTDAddressSpace *vtd_as, + uint32_t *pasid) +{ + VTDContextCacheEntry *cc_entry =3D &vtd_as->context_cache_entry; + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint8_t bus_num =3D pci_bus_num(vtd_as->bus); + uint8_t devfn =3D vtd_as->devfn; + VTDContextEntry ce; + int ret; + + if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { + ce =3D cc_entry->context_entry; + } else { + ret =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); + if (ret) { + return ret; + } + } + + /* Translate to iommu pasid if PCI_NO_PASID */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + *pasid =3D VTD_CE_GET_RID2PASID(&ce); + } else { + *pasid =3D vtd_as->pasid; + } + + return 0; +} + +static gboolean vtd_find_as_by_sid_and_iommu_pasid(gpointer key, gpointer = value, + gpointer user_data) +{ + VTDAddressSpace *vtd_as =3D (VTDAddressSpace *)value; + struct vtd_as_raw_key *target =3D (struct vtd_as_raw_key *)user_data; + uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn= ); + uint32_t pasid; + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return false; + } + + return (pasid =3D=3D target->pasid) && (sid =3D=3D target->sid); +} + +/* Translate iommu pasid to vtd_as */ +static inline +VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, uint32_t pas= id) +{ + struct vtd_as_raw_key key =3D { + .sid =3D sid, + .pasid =3D pasid + }; + + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_iommu_pasid, &key); +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009871; cv=none; d=zohomail.com; s=zohoarc; b=G/vvy5/QurCQoY8sb+A6pjQmMbQ8W4GbYQQx1JXaar8XRgjrxVoTMkG4LB9qHJclSMxt3S+uRh0RQn1uRYiaGXswUWxQpmKMj1IpmDXJXgAnknuLGjOcida5ClZMwzVpcaaZ7ZFZP2jJ3Et3PEvvO52v7PFAaxYz8sABqxwwsZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009871; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H5JRh7WDZzy/5sQqwkhprUmfGxY53ETwRLSnmpyrILg=; b=MxNxETLjoaCtENB5OgLwhiPJjVrejLG2IDN0DQsfI+GeqZhHi6FdUszBtGJk9D5wNUBnpD5gCNrBlRpvasFRXaoCiR1xQ8HVEq/DUC52/+370Tm1cXXTq7ty8LGA1loWjchGANSNWN20Q7hkiWqHkYxxkrZp1Owr6oPFVMevWgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009871649264.68050130164477; Tue, 8 Jul 2025 14:24:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFm-0004Rf-HV; Tue, 08 Jul 2025 16:49:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs9-0000c3-Tj for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:08 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs4-0008BN-NZ for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:56 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:55 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002453; x=1783538453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yx3q7fEaiyQjL76h7X90Owo+JKa7Jft2+4mZy+vciR8=; b=lO1z3QfHFu/YXfKIRSfXX8nlBmEr08oeLQeucNrFObYTlxj3cd1FuERL XXV2irFb7XKDYwQqz1eXUaI+4xy2f+or+nGjkdMWOmCocMcat4AqrS7vx 4R40cGn4B10nEH6nbCuZI1jUHpd0iPQYKn3WjqolTp4Y0ZU7sly54ZcND H0hoPkibBDS42j4vA1PYnmUjoXdVqBgH5NleMCSq9m1VJqCFxIlQK4FjG XamZXM7PrYUc+oCSIYidv3ZSwQCPpa/GdJdb7WlLo8ajTE60tck/vYPCS wPz0A95h3YUjDEZZtX2rp+ivMx5CBxsXscDTpABbBUn30a2MuzFBQrZrw g==; X-CSE-ConnectionGUID: 5xOQo2H4Rta8iYlxhDccow== X-CSE-MsgGUID: +Irfg+OQTpuaIgBKzdTbdA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974014" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974014" X-CSE-ConnectionGUID: MXHBRPVsTZaBDb32suObzw== X-CSE-MsgGUID: 2n0s/+9VQMSQYv5jw0hYzQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647969" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v3 10/20] intel_iommu: Handle PASID entry removing and updating Date: Tue, 8 Jul 2025 07:05:51 -0400 Message-ID: <20250708110601.633308-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009873062116600 Content-Type: text/plain; charset="utf-8" This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the pasid entry and track PASID usage and future PASID tagged DMA address translation support in vIOMMU. VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged and never freed. For other pasid, VTDAddressSpace instance is created/destroyed per the guest pasid entry set up/destroy. When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This patch handles a) and b), following patch will handle c). vIOMMU emulator could figure out the reason by fetching latest guest pasid = entry and compare it with cached PASID entry. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 194 +++++++++++++++++++++++++++++++-- hw/i386/intel_iommu_internal.h | 27 ++++- hw/i386/trace-events | 3 + include/hw/i386/intel_iommu.h | 6 + 4 files changed, 218 insertions(+), 12 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 38e7f7b7be..5bda439de6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1675,7 +1675,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, =20 if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); - return VTD_SM_PASID_ENTRY_DID(pe.val[1]); + return VTD_SM_PASID_ENTRY_DID(&pe); } =20 return VTD_CONTEXT_ENTRY_DID(ce->hi); @@ -3103,6 +3103,181 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState= *s, return true; } =20 +static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, + uint32_t pasid, VTDPASIDEntry = *pe) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDContextEntry ce; + int ret; + + if (!s->root_scalable) { + return -VTD_FR_RTADDR_INV_TTM; + } + + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->= devfn, + &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); +} + +static bool vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) +{ + return !memcmp(p1, p2, sizeof(*p1)); +} + +/* + * This function is used to update or clear cached pasid entry in vtd_as. + * vtd_as is released when corresponding cached pasid entry is cleared, + * except for PCI_NO_PASID which vtd_as is owen by PCI sub-system. + */ +static gboolean vtd_flush_pasid_locked(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPASIDCacheInfo *pc_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDPASIDEntry pe; + uint16_t did; + uint32_t pasid; + int ret; + + if (!pc_entry->valid) { + return false; + } + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + goto remove; + } + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + if (pc_info->pasid !=3D pasid) { + return false; + } + /* fall through */ + case VTD_PASID_CACHE_DOMSI: + if (pc_info->did !=3D did) { + return false; + } + /* fall through */ + case VTD_PASID_CACHE_GLOBAL_INV: + break; + default: + error_setg(&error_fatal, "invalid pc_info->type for flush"); + } + + /* + * pasid cache invalidation may indicate a present pasid + * entry to present pasid entry modification. To cover such + * case, vIOMMU emulator needs to fetch latest guest pasid + * entry and compares with cached pasid entry, then update + * pasid cache. + */ + ret =3D vtd_dev_get_pe_from_pasid(vtd_as, pasid, &pe); + if (ret) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry + * was modified to be either all-zero or non-present. Either + * case means existing pasid cache should be removed. + */ + goto remove; + } + + /* No need to update if cached pasid entry is latest */ + if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + pc_entry->pasid_entry =3D pe; + } + return false; + +remove: + pc_entry->valid =3D false; + + /* + * Don't remove address space of PCI_NO_PASID which is created for PCI + * sub-system. + */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + return false; + } + return true; +} + +/* Update the pasid cache in vIOMMU */ +static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) +{ + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + /* + * Regards to a pasid cache invalidation, e.g. a PSI. + * It could be either cases of below: + * a) a present pasid entry moved to non-present + * b) a present pasid entry to be a present entry + * c) a non-present pasid entry moved to present + */ + vtd_iommu_lock(s); + /* + * a,b): loop all the existing vtd_as instances for pasid cache remove + or update. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid_loc= ked, + pc_info); + vtd_iommu_unlock(s); +} + +static bool vtd_process_pasid_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t did; + uint32_t pasid; + VTDPASIDCacheInfo pc_info; + uint64_t mask[4] =3D {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_= ONE, + VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; + + if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true, + __func__, "pasid cache inv")) { + return false; + } + + did =3D VTD_INV_DESC_PASIDC_DID(inv_desc); + pasid =3D VTD_INV_DESC_PASIDC_PASID(inv_desc); + + switch (VTD_INV_DESC_PASIDC_G(inv_desc)) { + case VTD_INV_DESC_PASIDC_G_DSI: + trace_vtd_pasid_cache_dsi(did); + pc_info.type =3D VTD_PASID_CACHE_DOMSI; + pc_info.did =3D did; + break; + + case VTD_INV_DESC_PASIDC_G_PASID_SI: + /* PASID selective implies a DID selective */ + trace_vtd_pasid_cache_psi(did, pasid); + pc_info.type =3D VTD_PASID_CACHE_PASIDSI; + pc_info.did =3D did; + pc_info.pasid =3D pasid; + break; + + case VTD_INV_DESC_PASIDC_G_GLOBAL: + trace_vtd_pasid_cache_gsi(); + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + break; + + default: + error_report_once("invalid granularity field in PASID-cache invali= date " + "descriptor, hi: 0x%"PRIx64" lo: 0x%" PRIx64, + inv_desc->val[1], inv_desc->val[0]); + return false; + } + + vtd_pasid_cache_sync(s, &pc_info); + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3264,6 +3439,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_PC: + trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]= ); + if (!vtd_process_pasid_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_PIOTLB: trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); if (!vtd_process_piotlb_desc(s, &inv_desc)) { @@ -3299,16 +3481,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 - /* - * TODO: the entity of below two cases will be implemented in future s= eries. - * To make guest (which integrates scalable mode support patch set in - * iommu driver) work, just return true is enough so far. - */ - case VTD_INV_DESC_PC: - if (s->scalable_mode) { - break; - } - /* fallthrough */ default: error_report_once("%s: invalid inv desc: hi=3D%"PRIx64", lo=3D%"PR= Ix64 " (unknown type)", __func__, inv_desc.hi, diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 18bc22fc72..87059d26aa 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -315,6 +315,7 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 + VTD_FR_RTADDR_INV_TTM =3D 0x31, /* Invalid TTM in RTADDR */ /* PASID directory entry access failure */ VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, /* The Present(P) field of pasid directory entry is 0 */ @@ -492,6 +493,15 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL =20 +/* PASID-cache Invalidate Descriptor (pc_inv_dsc) fields */ +#define VTD_INV_DESC_PASIDC_G(x) extract64((x)->val[0], 4, 2) +#define VTD_INV_DESC_PASIDC_G_DSI 0 +#define VTD_INV_DESC_PASIDC_G_PASID_SI 1 +#define VTD_INV_DESC_PASIDC_G_GLOBAL 3 +#define VTD_INV_DESC_PASIDC_DID(x) extract64((x)->val[0], 16, 16) +#define VTD_INV_DESC_PASIDC_PASID(x) extract64((x)->val[0], 32, 20) +#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; @@ -552,6 +562,21 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPCInvType { + /* VTD spec defined PASID cache invalidation type */ + VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, + VTD_PASID_CACHE_PASIDSI =3D VTD_INV_DESC_PASIDC_G_PASID_SI, + VTD_PASID_CACHE_GLOBAL_INV =3D VTD_INV_DESC_PASIDC_G_GLOBAL, +} VTDPCInvType; + +typedef struct VTDPASIDCacheInfo { + VTDPCInvType type; + uint16_t did; + uint32_t pasid; + PCIBus *bus; + uint16_t devfn; +} VTDPASIDCacheInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) @@ -573,7 +598,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) =20 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ -#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) +#define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) =20 #define VTD_SM_PASID_ENTRY_FLPM 3ULL #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ac9e1a10aa..ae5bbfcdc0 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_gsi(void) "" +vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 +vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 50f9b27a45..0e3826f6f0 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -95,6 +95,11 @@ struct VTDPASIDEntry { uint64_t val[8]; }; =20 +typedef struct VTDPASIDCacheEntry { + struct VTDPASIDEntry pasid_entry; + bool valid; +} VTDPASIDCacheEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; @@ -107,6 +112,7 @@ struct VTDAddressSpace { MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; + VTDPASIDCacheEntry pasid_cache_entry; QLIST_ENTRY(VTDAddressSpace) next; /* Superset of notifier flags that this address space has */ IOMMUNotifierFlag notifier_flags; --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009069; cv=none; d=zohomail.com; s=zohoarc; b=QTazwdpshuBJHBUmD3V2MHBeobwhdZiDZqIsuklItSD0KWay0fuKJTGVi9f9rpqS+QwmXbhUggYsE5NGbmxBTas9fYWGBkyXkYXXZ+/NmD0TxPg68yObtmzyZb3ew39HZRN3thHxczUAfBx5WK9yE7930kLkwVNOcmdyk30P9nk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009069; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zr2+cxAdjclLBcr99SOs67ctJ0yngJDF3aJZXMBfdQ4=; b=jwqgrgFOH8mA+WnM2mnKrBDpY8NDhUEVgB3PIGaWwxNoendsfNETNEthDO4M2A0tKARMubdHjXxjtS7VkHl6hn3YjiqEYBqYEJPWhUbwyYZkMbehcE5MhLeHIM1aXwhFcPzubzq6AofqiGwtpoKwPgjJq4lGfOLml+UHSWKxhWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009069474366.82603768844467; Tue, 8 Jul 2025 14:11:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFb-0003jb-22; Tue, 08 Jul 2025 16:49:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrx-0000Jp-4h for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:47 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrp-00086x-3D for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:42 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:00 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:06:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002438; x=1783538438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ikvS1pvKdTqtEyPAEygZazQvrsc82tcxmp+Yv2N3FWQ=; b=ja6iJ/NZ5CmxuZ+vkKGxL7UwkWZeCBdvmhSoJ4audFl+J4DLYOyxAFO2 Ab2naoChE1CRkYHnfOIQRbOWEDcZRXdKP1RODTWxT8wkBvdYMXUnDl0ey hC1fu8K3H9doogb/NRoyqI8aj6p2svuarMBqCS7mabnvm3I49bG7Jw+Id BXOr2cDAlbpmt6gwvZFaJpcDbXwWr1ID82fw8CGce1zetQG5lxiyHKbaG bP8UeZlw+AIhh7kdvyxi8jdkacQwb2H/KdHfMZXiwF0+byEJ2/8+XLMDg NldyrUStPFcdkuyRXuI5GyKt89/INoP+RUKhxVekGmEf1aiKnDe3OMUS3 g==; X-CSE-ConnectionGUID: wxr1p1oBTjOQZet9F6t+sg== X-CSE-MsgGUID: UizyG0amT0O6LAumwfeEPA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974030" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974030" X-CSE-ConnectionGUID: lD5nkFOnR7W7SzeANx8S9Q== X-CSE-MsgGUID: Bh7GskPrSw6eKCR1X10pCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647972" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v3 11/20] intel_iommu: Handle PASID entry adding Date: Tue, 8 Jul 2025 07:05:52 -0400 Message-ID: <20250708110601.633308-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009072013116600 Content-Type: text/plain; charset="utf-8" When guest modifies a PASID entry, QEMU will capture the guest pasid select= ive pasid cache invalidation, allocate or remove a VTDAddressSpace instance per= the invalidation reasons: a) a present pasid entry moved to non-present b) a present pasid entry to be a present entry c) a non-present pasid entry moved to present This handles c) by going through each passthrough device and each pasid. Wh= en a new valid pasid entry is founded, find or create a vtd_as and cache pasid entry in it. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 170 ++++++++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 2 + 2 files changed, 169 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5bda439de6..cf2c959b60 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -826,6 +826,11 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *= s, VTDPASIDEntry *pe) } } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -1647,9 +1652,9 @@ static gboolean vtd_find_as_by_sid_and_iommu_pasid(gp= ointer key, gpointer value, } =20 /* Translate iommu pasid to vtd_as */ -static inline -VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, - uint16_t sid, uint32_t pas= id) +static VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, + uint32_t pasid) { struct vtd_as_raw_key key =3D { .sid =3D sid, @@ -3206,6 +3211,162 @@ remove: return true; } =20 +static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, + dma_addr_t pt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDEntry pe; + int pasid =3D start; + + while (pasid < end) { + if (!vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) + && vtd_pe_present(&pe)) { + int bus_n =3D pci_bus_num(info->bus), devfn =3D info->devfn; + uint16_t sid =3D PCI_BUILD_BDF(bus_n, devfn); + VTDPASIDCacheEntry *pc_entry; + VTDAddressSpace *vtd_as; + + vtd_iommu_lock(s); + /* + * When indexed by rid2pasid, vtd_as should have been created, + * e.g., by PCI subsystem. For other iommu pasid, we need to + * create vtd_as dynamically. The other iommu pasid is same as + * PCI's pasid, so it's used as input of vtd_find_add_as(). + */ + vtd_as =3D vtd_as_from_iommu_pasid_locked(s, sid, pasid); + vtd_iommu_unlock(s); + if (!vtd_as) { + vtd_as =3D vtd_find_add_as(s, info->bus, devfn, pasid); + } + + if ((info->type =3D=3D VTD_PASID_CACHE_DOMSI || + info->type =3D=3D VTD_PASID_CACHE_PASIDSI) && + (info->did !=3D VTD_SM_PASID_ENTRY_DID(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain id check. If domain id check fail, + * go to next pasid. + */ + pasid++; + continue; + } + + pc_entry =3D &vtd_as->pasid_cache_entry; + /* + * pasic cache update and clear are handled in + * vtd_flush_pasid_locked(), only care new pasid entry here. + */ + if (!pc_entry->valid) { + pc_entry->pasid_entry =3D pe; + pc_entry->valid =3D true; + } + } + pasid++; + } +} + +/* + * In VT-d scalable mode translation, PASID dir + PASID table is used. + * This function aims at looping over a range of PASIDs in the given + * two level table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(IntelIOMMUState *s, + dma_addr_t pdt_base, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D + (pasid + VTD_PASID_TBL_ENTRY_NUM) & ~(VTD_PASID_TBL_ENTRY_NUM= - 1); + pasid_next =3D pasid_next < end ? pasid_next : end; + + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(s, pt_base, pasid, pasid_next, inf= o); + } + pasid =3D pasid_next; + } +} + +static void vtd_replay_pasid_bind_for_dev(IntelIOMMUState *s, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDContextEntry ce; + + if (!vtd_dev_to_context_entry(s, pci_bus_num(info->bus), info->devfn, + &ce)) { + uint32_t max_pasid; + + max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * VTD_PASID_TBL_ENT= RY_NUM; + if (end > max_pasid) { + end =3D max_pasid; + } + vtd_sm_pasid_table_walk(s, + VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, + end, + info); + } +} + +/* + * This function replays the guest pasid bindings by walking the two level + * guest PASID table. For each valid pasid entry, it finds or creates a + * vtd_as and caches pasid entry in vtd_as. + */ +static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + /* + * Currently only Requests-without-PASID is supported, as vIOMMU doesn= 't + * support RPS(RID-PASID Support), pasid scope is fixed to [0, 1). + */ + int start =3D 0, end =3D 1; + VTDHostIOMMUDevice *vtd_hiod; + VTDPASIDCacheInfo walk_info; + GHashTableIter as_it; + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* fall through */ + case VTD_PASID_CACHE_DOMSI: + case VTD_PASID_CACHE_GLOBAL_INV: + /* loop all assigned devices */ + break; + default: + error_setg(&error_fatal, "invalid pc_info->type for replay"); + } + + /* + * In this replay, one only needs to care about the devices which are + * backed by host IOMMU. Those devices have a corresponding vtd_hiod + * in s->vtd_host_iommu_dev. For devices not backed by host IOMMU, it + * is not necessary to replay the bindings since their cache could be + * re-created in the future DMA address translation. + * + * VTD translation callback never accesses vtd_hiod and its correspond= ing + * cached pasid entry, so no iommu lock needed here. + */ + walk_info =3D *pc_info; + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + walk_info.bus =3D vtd_hiod->bus; + walk_info.devfn =3D vtd_hiod->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + } +} + /* Update the pasid cache in vIOMMU */ static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) { @@ -3228,6 +3389,9 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, = VTDPASIDCacheInfo *pc_info) g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid_loc= ked, pc_info); vtd_iommu_unlock(s); + + /* c): loop all passthrough device for new pasid entries */ + vtd_replay_guest_pasid_bindings(s, pc_info); } =20 static bool vtd_process_pasid_desc(IntelIOMMUState *s, diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 87059d26aa..621e1f6947 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -558,6 +558,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 +#define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3) #define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL @@ -588,6 +589,7 @@ typedef struct VTDPASIDCacheInfo { #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TBL_ENTRY_NUM (1ULL << 6) =20 /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752007795; cv=none; d=zohomail.com; s=zohoarc; b=ZpKClBu2kfk848mTQDGZzI56ARi5lIS5NKEMU+ri7SSgecH9Yw8KWBzP06Kat0kLhiMe6YK6d918lOXBUrb2nEBoa6AzI9XInFHwfmICew57qu5qITYnQAGlzXZLA/FeM54qip54I9IL5nmkNOCx7y2WCD8hBT2RlcttNgPLnHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752007795; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vMJzAaan14hTV1feXSRDPuOkLH6Rnjn+7v+BabYIRb0=; b=aoR9wUGoWGLErV8mjGlTMfVFiv/WZ07ERTxm2575EU7Vh0oq+X7bDLZItfIaDFOzH4+wtJgrj3Bj9nxT6lro8KzsQVsKjIIjnKTdk/kzjIpE4cFuGRlGuQvSJGprR9KvBtQq2LNAHfdqJV9UovApy2GlHYSvYadh8xH7IrTXmfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752007795833329.03198444396276; Tue, 8 Jul 2025 13:49:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFS-0003SN-4R; Tue, 08 Jul 2025 16:49:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrx-0000Jr-4Y for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:47 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDrp-00082f-3D for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:42 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:04 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002438; x=1783538438; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XWC3s87S3Ok/g4vNhclhAx5UOVWaOsLS9KdSua9BHU0=; b=Fv5hNfbOtaCg/Rw1PqwXaeTDhBuxdhfsN3K/Zir1TV6c+NBYOWLr5CHA sQDgpkAwhsqUFpdT4cjPmIcpT/6Mu+9Mr9UhUB3OVNIe+hdvkx6stiaCB m0AcIuOuAi/FdnCOgPXGYi/1cBTRKKE/1DIBjfENTVI1eC9+Ejpw7EMex S13lioZy5YhzlJ4HeFgwT5gmhKarxXO8/tInWmaU8fX0W1iGHmsjynSYz MDv4FxPC0THcsX+oSWZ0VHnDBpZMTN/IUQNPQL8BTqM/xKL4x6NzkXPyW 1Z5LOmujYQJoJfP48cuzXVD5DFQMcnf/cpY1RroreejfJ6O0sGRSfS4T0 A==; X-CSE-ConnectionGUID: SI3XZthOR/GCRSuqZlQMIA== X-CSE-MsgGUID: 4XA3raoUQbe0JavlrzIWzg== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974037" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974037" X-CSE-ConnectionGUID: +yhSRuX4Q9SrJk7IOUrWRA== X-CSE-MsgGUID: SQLPJVImSXyUJ14O97GJ0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647983" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v3 12/20] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Date: Tue, 8 Jul 2025 07:05:53 -0400 Message-ID: <20250708110601.633308-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752007797199116600 Content-Type: text/plain; charset="utf-8" FORCE_RESET is different from GLOBAL_INV which updates pasid cache if underlying pasid entry is still valid, it drops all the pasid caches. FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, only used internally in system level reset. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 9 +++++++++ hw/i386/trace-events | 1 + 3 files changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cf2c959b60..cf263498db 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,6 +87,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); + static void vtd_panic_require_caching_mode(void) { error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " @@ -391,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_lock(s); vtd_reset_iotlb_locked(s); vtd_reset_context_cache_locked(s); + vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); } =20 @@ -3171,6 +3174,8 @@ static gboolean vtd_flush_pasid_locked(gpointer key, = gpointer value, /* fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_FORCE_RESET: + goto remove; default: error_setg(&error_fatal, "invalid pc_info->type for flush"); } @@ -3211,6 +3216,23 @@ remove: return true; } =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_reset(); + + pc_info.type =3D VTD_PASID_CACHE_FORCE_RESET; + + /* + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remo= ve + * which will free all vtd_as instances except those created for PCI + * sub-system. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, + vtd_flush_pasid_locked, &pc_info); +} + static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, dma_addr_t pt_base, int start, @@ -3344,6 +3366,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_FORCE_RESET: + /* For force reset, no need to go further replay */ + return; default: error_setg(&error_fatal, "invalid pc_info->type for replay"); } diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 621e1f6947..887f93bac9 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -568,6 +568,15 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, VTD_PASID_CACHE_PASIDSI =3D VTD_INV_DESC_PASIDC_G_PASID_SI, VTD_PASID_CACHE_GLOBAL_INV =3D VTD_INV_DESC_PASIDC_G_GLOBAL, + + /* + * Internally used PASID cache invalidation type starts here, + * 0x10 is large enough as invalidation type in pc_inv_desc + * is 2bits in size. + */ + + /* Reset all PASID cache entries, used in system level reset */ + VTD_PASID_CACHE_FORCE_RESET =3D 0x10, } VTDPCInvType; =20 typedef struct VTDPASIDCacheInfo { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ae5bbfcdc0..c8a936eb46 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009877; cv=none; d=zohomail.com; s=zohoarc; b=aphxdYtiLuCxK/4ppN8TNGPr0yd3g8qEO/S5U+acOzTcZBrirkPXiUjo1Ui2WQsLpEV0zLJWNBUUXkIqV/srK/AhixS2UWzWzYmtTpYu0jXeVF+smDc5936a8xVnG1rT/L6X2MQg4L98HEzn3tUSAhpWDfafnTQA+R/iKh2pBPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009877; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=49P1kt1pT5/JgkG8fm/RgA3kgh9bPCj/wD4OZPAliSs=; b=jc7t23f0SLlG5KssEwinD37QSYTFuE/ggGEwGU96bwJHNVfQ4rOMPdj6nHJjPRuThy8far9EDWjLzfI8Lhph1+9TOLvFVDogTFjvgrCRvWEMftenWj5uro4gwZxiBHdsa/x+uRUUCculP8sdmkM87g4Ft1Bu/K9JgPS82cohk2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009877112117.47263537333902; Tue, 8 Jul 2025 14:24:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFj-00049z-NH; Tue, 08 Jul 2025 16:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs5-0000YH-O2 for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:04 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs3-00082f-En for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:53 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:08 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002452; x=1783538452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jYiYK1jkfILuoSspWWK6/mpv5mA4dlw0x1IVbMssGHI=; b=kB/UATdIqba+1x/BLmTjj/dvYIzbU03UIVkMpLYTafr2rJfmlQDAes7n RUIjTb9OF8IeL/yNs62ysPOBQcsmHywxTgqPyjYk8yg0ws9Q9b2KMSOBl oJ/89XI4vLni9LIBLouo6CiTuvsLbFIXvT2Eu9QgUScVqz7GhnloWfXxf GGvuOUNnqAp+U5RlR7WUrx+sZcRUv5hyZBVg+ae7MVCKyjE+WglVLLz6u aBvfTuRr3/O2EXS991rVwVwdQ/DrHXDJ19QD6LHY2LdsOtjJJcikt99WJ 0uZ1QV0W/2JuXGtv6GOXCmt8QuUO4hNmWO+e7N4zjKOdBo6Ufjol1cgc6 Q==; X-CSE-ConnectionGUID: PdouaHpdSN+2d40AyyLGRQ== X-CSE-MsgGUID: E///+mTyRMaheUbY0D9EqQ== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974047" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974047" X-CSE-ConnectionGUID: pvfe/nTYQaGtjJMeiqoOLQ== X-CSE-MsgGUID: C5dkz0PCSiC4adZgOh/0Ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647991" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 13/20] intel_iommu: Stick to system MR for IOMMUFD backed host device when x-fls=on Date: Tue, 8 Jul 2025 07:05:54 -0400 Message-ID: <20250708110601.633308-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009879268116600 Content-Type: text/plain; charset="utf-8" When guest in scalable mode and x-flts=3Don, we stick to system MR for IOMM= UFD backed host device. Then its default hwpt contains GPA->HPA mappings which = is used directly if PGTT=3DPT and used as nested parent if PGTT=3DFLT. Otherwi= se fallback to original processing. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cf263498db..030862fb2f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1773,6 +1773,28 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, V= TDContextEntry *ce, =20 } =20 +static VTDHostIOMMUDevice *vtd_find_hiod_iommufd(IntelIOMMUState *s, + VTDAddressSpace *as) +{ + struct vtd_as_key key =3D { + .bus =3D as->bus, + .devfn =3D as->devfn, + }; + VTDHostIOMMUDevice *vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu= _dev, + &key); + + if (vtd_hiod && vtd_hiod->hiod && + object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + return vtd_hiod; + } + return NULL; +} + +/* + * vtd_switch_address_space() calls vtd_as_pt_enabled() to determine which + * MR to switch to. Switch to system MR if return true, iommu MR otherwise. + */ static bool vtd_as_pt_enabled(VTDAddressSpace *as) { IntelIOMMUState *s; @@ -1781,6 +1803,18 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) assert(as); =20 s =3D as->iommu_state; + + /* + * When guest in scalable mode and x-flts=3Don, we stick to system MR + * for IOMMUFD backed host device. Then its default hwpt contains + * GPA->HPA mappings which is used directly if PGTT=3DPT and used as + * nested parent if PGTT=3DFLT. Otherwise fallback to original + * processing. + */ + if (s->root_scalable && s->flts && vtd_find_hiod_iommufd(s, as)) { + return true; + } + if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn, &ce)) { /* --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008165; cv=none; d=zohomail.com; s=zohoarc; b=fojoWunxCpzecE26PUHBSmqwpJPhh23smjmYMp1TrdJz7qQhtCYTxtovm3vsYU2bN1jSiBezkm0/bO6Yxp+52ok+WXxLrc+/zfOV8so1Xbxb8Kbrw8ltge927lNx78VDK2IK9JOz8IuWua6GGhGCSg/wtuFmp+JeR4IWRQbjo94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008165; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=D74OGbw6DVsH2IuhJZvnO9GhZBcxlXEjSA2k2cTkUps=; b=m0dMkdelisxT/w0UA2NFhXHQEBUFZE6V3HrBVbeHkJbhFiHYXR8IEdQiDyneVU9Jf4ijc+3bOhLh54s0UMFk1vnbpbJKxoRi2S7+3rRmf+YZ5VZaZW1zm6JUXXYWBwKh0aZBEF8ALK7xf1TnyavTjvLFjMpZfBF9o8M0b0BxMjY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175200816507611.721744812577867; Tue, 8 Jul 2025 13:56:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFO-0003D9-GS; Tue, 08 Jul 2025 16:49:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsA-0000c4-Ah for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:08 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs4-00086x-SB for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:56 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:12 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002453; x=1783538453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SJ9E8XxsukQQm9xPWcv7N2WNYua0+CpREJT6UgZ1flM=; b=jg98cl6gpu5zGsBLLB6YfyHNFkt4KAoApjo6ZlMkao7PklOXWRAqLAnx V76frv4EwGl2pvaNYzasSQ5SKTxLOymMLIwgkAEmyXJHEP2aErSoHhD+Y /iXDUCxzp+Zh+GUCK50XcXM8Vvr8uO2WuliraynfEVn4JKCDoRRQWJr0Y KbQeUkzrToyWf/SbfZc2RpNjeXMqIDAgmunQ6/1HyDCTRgxiX9lGF1Tqy 2JQOPnA7tcs/GvrFDHLbQ8PhKhxpKnq4S7ToIuq5YqI82IMwJxvsryOTg yyozPMInyhzVqeERT1Zr+ylNWk168m9guyKepGR41Qwsq2tor+JPUSnhh g==; X-CSE-ConnectionGUID: AZlF9zn6R6m7O/+KOeGMyQ== X-CSE-MsgGUID: FfKI+16/RP+hRvxrtMekzA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974058" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974058" X-CSE-ConnectionGUID: k+C/iyZmS5e8Ervoo0YZRw== X-CSE-MsgGUID: YAYHSZNfTMyGGhmRs0Fsxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192647997" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v3 14/20] intel_iommu: Bind/unbind guest page table to host Date: Tue, 8 Jul 2025 07:05:55 -0400 Message-ID: <20250708110601.633308-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008167499116600 Content-Type: text/plain; charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU mdoe and PGTT configuration. When PGTT is Pass-through(100b), the hwpt on host side is a stage-2 page table(GPA->HPA). When PGTT is First-stage Translation only(001b), vIOMMU reuse hwpt(GPA->HPA) provided by VFIO as nested parent to construct nested page table. When guest decides to use legacy mode then vIOMMU switches the MRs of the device's AS, hence the IOAS created by VFIO container would be switched to using the IOMMU_NOTIFIER_IOTLB_EVENTS since the MR is switched to IOMMU MR. So it is able to support shadowing the guest IO page table. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 221 ++++++++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 14 ++- hw/i386/trace-events | 3 + include/hw/i386/intel_iommu.h | 1 + 4 files changed, 233 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 030862fb2f..c35673eb58 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -20,6 +20,7 @@ */ =20 #include "qemu/osdep.h" +#include CONFIG_DEVICES /* CONFIG_IOMMUFD */ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" @@ -41,6 +42,9 @@ #include "migration/vmstate.h" #include "trace.h" #include "system/iommufd.h" +#ifdef CONFIG_IOMMUFD +#include +#endif =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -50,10 +54,9 @@ =20 /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) -#define VTD_PE_GET_FL_LEVEL(pe) \ - (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM)) #define VTD_PE_GET_SL_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) +#define VTD_PE_GET_FL_LEVEL(pe) (VTD_SM_PASID_ENTRY_FSPM(pe) + 4) =20 /* * PCI bus number (or SID) is not reliable since the device is usaully @@ -834,6 +837,31 @@ static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTD= ContextEntry *ce) return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); } =20 +static inline dma_addr_t vtd_pe_get_flpt_base(VTDPASIDEntry *pe) +{ + return pe->val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; +} + +/* + * Stage-1 IOVA address width: 48 bits for 4-level paging(FSPM=3D00) + * 57 bits for 5-level paging(FSPM=3D01) + */ +static inline uint32_t vtd_pe_get_fl_aw(VTDPASIDEntry *pe) +{ + return 48 + VTD_SM_PASID_ENTRY_FSPM(pe) * 9; +} + +static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_PT); +} + +/* check if pgtt is first stage translation */ +static inline bool vtd_pe_pgtt_is_flt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_FLT); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -1131,7 +1159,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { - return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; + return pe.val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; } else { return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; } @@ -1766,7 +1794,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, */ return false; } - return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); + return vtd_pe_pgtt_is_pt(&pe); } =20 return (vtd_ce_get_type(ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH); @@ -2428,6 +2456,178 @@ static void vtd_context_global_invalidate(IntelIOMM= UState *s) vtd_iommu_replay_all(s); } =20 +#ifdef CONFIG_IOMMUFD +static void vtd_init_s1_hwpt_data(struct iommu_hwpt_vtd_s1 *vtd, + VTDPASIDEntry *pe) +{ + memset(vtd, 0, sizeof(*vtd)); + + vtd->flags =3D (VTD_SM_PASID_ENTRY_SRE_BIT(pe) ? IOMMU_VTD_S1_SRE : 0= ) | + (VTD_SM_PASID_ENTRY_WPE_BIT(pe) ? IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE_BIT(pe) ? IOMMU_VTD_S1_EAFE : 0= ); + vtd->addr_width =3D vtd_pe_get_fl_aw(pe); + vtd->pgtbl_addr =3D (uint64_t)vtd_pe_get_flpt_base(pe); +} + +static int vtd_create_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDPASIDEntry *pe, uint32_t *s1_hwpt, + Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd; + + vtd_init_s1_hwpt_data(&vtd, pe); + + return !iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + idev->hwpt_id, 0, IOMMU_HWPT_DATA_V= TD_S1, + sizeof(vtd), &vtd, s1_hwpt, errp); +} + +static void vtd_destroy_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDAddressSpace *vtd_as) +{ + if (!vtd_as->s1_hwpt) { + return; + } + iommufd_backend_free_id(idev->iommufd, vtd_as->s1_hwpt); + vtd_as->s1_hwpt =3D 0; +} + +static int vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; + uint32_t hwpt_id; + int ret; + + /* + * We can get here only if flts=3Don, the supported PGTT is FLT and PT. + * Catch invalid PGTT when processing invalidation request to avoid + * attaching to wrong hwpt. + */ + if (!vtd_pe_pgtt_is_flt(pe) && !vtd_pe_pgtt_is_pt(pe)) { + error_setg(errp, "Invalid PGTT type"); + return -EINVAL; + } + + if (vtd_pe_pgtt_is_flt(pe)) { + /* Should fail if the FLPT base is 0 */ + if (!vtd_pe_get_flpt_base(pe)) { + error_setg(errp, "FLPT base is 0"); + return -EINVAL; + } + + if (vtd_create_s1_hwpt(idev, pe, &hwpt_id, errp)) { + return -EINVAL; + } + } else { + hwpt_id =3D idev->hwpt_id; + } + + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret); + if (!ret) { + vtd_destroy_s1_hwpt(idev, vtd_as); + if (vtd_pe_pgtt_is_flt(pe)) { + vtd_as->s1_hwpt =3D hwpt_id; + } + } else if (vtd_pe_pgtt_is_flt(pe)) { + iommufd_backend_free_id(idev->iommufd, hwpt_id); + } + + return ret; +} + +static int vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + uint32_t pasid =3D vtd_as->pasid; + int ret; + + if (vtd_hiod->iommu_state->dmar_enabled) { + ret =3D !host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id= , errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (!ret) { + vtd_destroy_s1_hwpt(idev, vtd_as); + } + + return ret; +} + +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, + Error **errp) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(s, vtd_as); + int ret; + + if (!vtd_hiod) { + /* No need to go further, e.g. for emulated device */ + return 0; + } + + if (vtd_as->pasid !=3D PCI_NO_PASID) { + error_setg(errp, "Non-rid_pasid %d not supported yet", vtd_as->pas= id); + return -EINVAL; + } + + switch (op) { + case VTD_PASID_UPDATE: + case VTD_PASID_BIND: + { + ret =3D vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); + break; + } + case VTD_PASID_UNBIND: + { + ret =3D vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); + break; + } + default: + error_setg(errp, "Unknown VTDPASIDOp!!!"); + break; + } + + return ret; +} +#else +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, + Error **errp) +{ + return 0; +} +#endif + +static int vtd_bind_guest_pasid_report_err(VTDAddressSpace *vtd_as, + VTDPASIDOp op) +{ + Error *local_err =3D NULL; + int ret; + + /* + * vIOMMU calls into kernel to do BIND/UNBIND, the failure reason + * can be kernel, QEMU bug or invalid guest config. None of them + * should be reported to guest in PASID cache invalidation + * processing path. But at least, we can report it to QEMU console. + * + * TODO: for invalid guest config, DMA translation fault will be + * caught by host and passed to QEMU to inject to guest in future. + */ + ret =3D vtd_bind_guest_pasid(vtd_as, op, &local_err); + if (ret) { + error_report_err(local_err); + } + + return ret; +} + /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -3234,10 +3434,20 @@ static gboolean vtd_flush_pasid_locked(gpointer key= , gpointer value, /* No need to update if cached pasid entry is latest */ if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { pc_entry->pasid_entry =3D pe; + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_UPDATE)) { + /* + * In case update binding fails, tear down existing binding to + * catch invalid pasid entry config during DMA translation. + */ + goto remove; + } } return false; =20 remove: + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_UNBIND)) { + return false; + } pc_entry->valid =3D false; =20 /* @@ -3317,6 +3527,9 @@ static void vtd_sm_pasid_table_walk_one(IntelIOMMUSta= te *s, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_BIND= )) { + pc_entry->valid =3D false; + } } } pasid++; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 887f93bac9..c87e59554d 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -563,6 +563,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPASIDOp { + VTD_PASID_BIND, + VTD_PASID_UPDATE, + VTD_PASID_UNBIND, +} VTDPASIDOp; + typedef enum VTDPCInvType { /* VTD spec defined PASID cache invalidation type */ VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, @@ -611,8 +617,12 @@ typedef struct VTDPASIDCacheInfo { #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ #define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) =20 -#define VTD_SM_PASID_ENTRY_FLPM 3ULL -#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_FSPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_SRE_BIT(x) extract64((x)->val[2], 0, 1) +/* 00: 4-level paging, 01: 5-level paging, 10-11: Reserved */ +#define VTD_SM_PASID_ENTRY_FSPM(x) extract64((x)->val[2], 2, 2) +#define VTD_SM_PASID_ENTRY_WPE_BIT(x) extract64((x)->val[2], 4, 1) +#define VTD_SM_PASID_ENTRY_EAFE_BIT(x) extract64((x)->val[2], 7, 1) =20 /* First Level Paging Structure */ /* Masks for First Level Paging Entry */ diff --git a/hw/i386/trace-events b/hw/i386/trace-events index c8a936eb46..1c31b9a873 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 0e3826f6f0..2affab36b2 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -104,6 +104,7 @@ struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; uint32_t pasid; + uint32_t s1_hwpt; AddressSpace as; IOMMUMemoryRegion iommu; MemoryRegion root; /* The root container of the device */ --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008012; cv=none; d=zohomail.com; s=zohoarc; b=N8mb22Lieyytpu0jMw4xb3lQhmlL1CHAH/FvYP+zq26wVmGD6nIgyx/wUwu2Yz9N/zvONe74e701orteGiFIuRcyuoi8DLXHgof+qA0mIt1XC/kx4WEAfNZVJw7j+TWjfTraaRzFsk1TrabTz3sSUNmEa4S9UYyoqPYImXXQwzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008012; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aKf4WR86RUDDvjW9AeX/kQbzscshrlDUwr5xzX4U67Y=; b=XjOIgvvAykpyRkCEDr5Xz34Kk4GqOkgRRsfK3u34QXTeTjkQnaDSEz705kSjRFxJekG77S84Fb/Eo4X1jCw2jpdPPth88L5S33/rFf8FY6/NVQ00KP3wHt5l0d3zqh4QN+Og4fAGJI+c+qMELPi7eP9BgjfB6LzSaH1XttVPQvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752008012611348.52798147989574; Tue, 8 Jul 2025 13:53:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFq-0004sx-FD; Tue, 08 Jul 2025 16:49:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsA-0000c5-Dv for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:08 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDs6-00082f-23 for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:20:57 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:17 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002455; x=1783538455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SR4FjrzFxmx6ILcaxKJKK6EBtEpMukiad4HTKi/4A20=; b=lAUyZ3sNzHirNiwDCijM3HdqTLOLRVh/oYf4qSGF93FG9g07lidwgQa1 QisTkH7bnL3bE76aAu4GBlsOsrpHmlSKicHd+1c/b2xNjA9FVQu3YDPSs LiXcAEWPAkDXQjPTjijq6hz+AGmTNKW0y5Cf8SuYoWPirQZ6bTMcXrhUY lc4+C4qPSjm9j5KLhPYEquxzNmTGpD/smn6vcBK7AWv7gXsdnIpImg2xp EWI/VdlnXaaM0ohSV0XgGLXewSUTR4CaTz2KEye+Nn/F8saQ4CDy55ul4 0eNMcBesF9JEuYNeLjy78k6MJ7su/FZhsaAcqQTX2I09mhOBkvnqfXCxF w==; X-CSE-ConnectionGUID: HL42Z9NxQKmNoW2AY816Eg== X-CSE-MsgGUID: 7EuhZFEHR8So2In5+arG4Q== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974066" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974066" X-CSE-ConnectionGUID: 6jG3VQW6TauI9HFEoFHmrQ== X-CSE-MsgGUID: BlN3Q734QA2SQbQvj1I6EA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648006" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan Subject: [PATCH v3 15/20] intel_iommu: Replay pasid bindings after context cache invalidation Date: Tue, 8 Jul 2025 07:05:56 -0400 Message-ID: <20250708110601.633308-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008013573116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This replays guest pasid bindings after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 42 ++++++++++++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/trace-events | 1 + 3 files changed, 45 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c35673eb58..887830a855 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -91,6 +91,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -2437,6 +2441,8 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info; + trace_vtd_inv_desc_cc_global(); /* Protects context cache */ vtd_iommu_lock(s); @@ -2454,6 +2460,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 #ifdef CONFIG_IOMMUFD @@ -2686,6 +2695,15 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec, context flush should also be followed with PASID + * cache and iotlb flush. In order to work with a guest which + * doesn't follow spec and missed PASID cache flush, we have + * vtd_pasid_cache_devsi() to invalidate PASID caches of the + * passthrough device. Host iommu driver would flush piotlb + * when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_as->bus, devfn); } } } @@ -3410,6 +3428,11 @@ static gboolean vtd_flush_pasid_locked(gpointer key,= gpointer value, break; case VTD_PASID_CACHE_FORCE_RESET: goto remove; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->bus !=3D vtd_as->bus || pc_info->devfn !=3D vtd_as->d= evfn) { + return false; + } + break; default: error_setg(&error_fatal, "invalid pc_info->type for flush"); } @@ -3616,6 +3639,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; + case VTD_PASID_CACHE_DEVSI: + walk_info.bus =3D pc_info->bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; default: error_setg(&error_fatal, "invalid pc_info->type for replay"); } @@ -3666,6 +3694,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s,= VTDPASIDCacheInfo *pc_info) vtd_replay_guest_pasid_bindings(s, pc_info); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.bus =3D bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c87e59554d..9af073d843 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -583,6 +583,8 @@ typedef enum VTDPCInvType { =20 /* Reset all PASID cache entries, used in system level reset */ VTD_PASID_CACHE_FORCE_RESET =3D 0x10, + /* Invalidate all PASID entries in a device */ + VTD_PASID_CACHE_DEVSI, } VTDPCInvType; =20 typedef struct VTDPASIDCacheInfo { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 1c31b9a873..830b11f68b 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009181; cv=none; d=zohomail.com; s=zohoarc; b=QrFK9knMeT53Nolg37LSXeQl1kKxJqYV4zig7l3wmsaJ4VJD4ik+yFYQuswA+dTeNX9aqSwI0yckDK+miJCidEaKf0qJDIDx3NBC2sgY9+0r/MFaxl47HJ/lgjXU7ztXQKTfYgk/xpn1LmndflAM08YccWTC57EN9nrosOSu2YU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009181; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lI+zJJGhTZeWPWqoD07iQCprVBAtc7Xmnf+eNuS5r+8=; b=UokDgka5ev6Tj7JEwOicmak3alnyM8VQhGsMpqfZ/1t+E1uZsnc0V28uEJqNIe0iaDJzELWdyfRcrZUtZslhufRzVaUETTrIuC6xbqp325gJ/2zupdlPfljUVn3kFVYKKKT3UI6rsPRU7GfeoTetqG2s3Bk3sA9Iah6qaMspIJI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009181313400.28740420609813; Tue, 8 Jul 2025 14:13:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFDb-000309-BB; Tue, 08 Jul 2025 16:47:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsL-0000eT-0y for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:12 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsA-0008BN-JT for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:02 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:21 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002459; x=1783538459; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ShIehTFb3p9MKkiVPnCmMIig5SMIJy5XRedD7Veywv8=; b=GI9hGU2QcO14NUcXxeHFu9RODDgSEZWMBSqV0VLeBjDTYPBQoTpOxSuT 3SFuxAH3KpVV2zM416/w11gRWG67G9jsqiEzhNO4kctklnFXD8gIAw600 lQNj83yepP6Y1nExzxrxfyT71Mno6jNu/8bkiWHgWLjwMU1peWvrcsDij WuJW5qOKOzcZnLWsbKnWXE8gk7bJLFJPuZ2afVnlp6YzYfmQ77gpm25OL GEs2tqL76/0d4Z2shsU1bNUekOc+/WcPrsFsxxAz/ihI+pkepC5Pcaz4g gHJoHGNxgAdIAubhLsnXHoWCFAfwaetTFWlzzv1oprsO/HuyLG/w/C/I7 g==; X-CSE-ConnectionGUID: k4lxSEq/RK+3cWvcD0QC/A== X-CSE-MsgGUID: xqQVJcRQTp6AEw4ignma4g== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974075" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974075" X-CSE-ConnectionGUID: Ma1qJf7ySBGUD/B47JIUbg== X-CSE-MsgGUID: TsCjrEuBRrKPn78hXtH+vw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648014" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan Subject: [PATCH v3 16/20] intel_iommu: Propagate PASID-based iotlb invalidation to host Date: Tue, 8 Jul 2025 07:05:57 -0400 Message-ID: <20250708110601.633308-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009182480116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This traps the guest PASID-based iotlb invalidation request and propagate it to host. Intel VT-d 3.0 supports nested translation in PASID granularity. Guest SVA support could be implemented by configuring nested translation on specific pasid. This is also known as dual stage DMA translation. Under such configuration, guest owns the GVA->GPA translation which is configured as stage-1 page table on host side for a specific pasid, and host owns GPA->HPA translation. As guest owns stage-1 translation table, piotlb invalidation should be propagated to host since host IOMMU will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 95 +++++++++++++++++++++++++++++++++- hw/i386/intel_iommu_internal.h | 6 +++ 2 files changed, 99 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 887830a855..d8b4296fe4 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2606,12 +2606,99 @@ static int vtd_bind_guest_pasid(VTDAddressSpace *vt= d_as, VTDPASIDOp op, =20 return ret; } + +static void +vtd_invalidate_piotlb_locked(VTDAddressSpace *vtd_as, + struct iommu_hwpt_vtd_s1_invalidate *cache) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(s, vtd_as); + HostIOMMUDeviceIOMMUFD *idev; + uint32_t entry_num =3D 1; /* Only implement one request for simplicity= */ + Error *local_err =3D NULL; + + if (!vtd_hiod || !vtd_as->s1_hwpt) { + return; + } + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); + + if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_as->s1_hwpt, + IOMMU_HWPT_INVALIDATE_DATA_VTD_S= 1, + sizeof(*cache), &entry_num, cach= e, + &local_err)) { + /* Something wrong in kernel, but trying to continue */ + error_report_err(local_err); + } +} + +/* + * This function is a loop function for the s->vtd_address_spaces + * list with VTDPIOTLBInvInfo as execution filter. It propagates + * the piotlb invalidation to host. + */ +static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPIOTLBInvInfo *piotlb_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + uint32_t pasid; + uint16_t did; + + /* Replay only fills pasid entry cache for passthrough device */ + if (!pc_entry->valid || + !vtd_pe_pgtt_is_flt(&pc_entry->pasid_entry)) { + return; + } + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return; + } + + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D pas= id) { + vtd_invalidate_piotlb_locked(vtd_as, piotlb_info->inv_data); + } +} + +static void +vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool ih) +{ + struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; + VTDPIOTLBInvInfo piotlb_info; + + cache_info.addr =3D addr; + cache_info.npages =3D npages; + cache_info.flags =3D ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0; + + piotlb_info.domain_id =3D domain_id; + piotlb_info.pasid =3D pasid; + piotlb_info.inv_data =3D &cache_info; + + /* + * Go through each vtd_as instance in s->vtd_address_spaces, find out + * the affected host device which need host piotlb invalidation. Piotlb + * invalidation should check pasid cache per architecture point of vie= w. + */ + g_hash_table_foreach(s->vtd_address_spaces, + vtd_flush_host_piotlb_locked, &piotlb_info); +} #else static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, Error **errp) { return 0; } + +static void +vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool ih) +{ +} #endif =20 static int vtd_bind_guest_pasid_report_err(VTDAddressSpace *vtd_as, @@ -3286,6 +3373,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, 0, (uint64_t)-1,= 0); vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { @@ -3307,7 +3395,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, } =20 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, - uint32_t pasid, hwaddr addr, uint8_= t am) + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) { VTDIOTLBPageInvInfo info; =20 @@ -3319,6 +3408,7 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUStat= e *s, uint16_t domain_id, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, addr, 1 << am, i= h); vtd_iommu_unlock(s); =20 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid); @@ -3350,7 +3440,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); - vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 9af073d843..f4982b19a2 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -595,6 +595,12 @@ typedef struct VTDPASIDCacheInfo { uint16_t devfn; } VTDPASIDCacheInfo; =20 +typedef struct VTDPIOTLBInvInfo { + uint16_t domain_id; + uint32_t pasid; + struct iommu_hwpt_vtd_s1_invalidate *inv_data; +} VTDPIOTLBInvInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752009435; cv=none; d=zohomail.com; s=zohoarc; b=fLotaWQaSVevtSGVcWOnSpYwRO+lv7m1sHPTcW5X/d25s8VI8GlAaHLO/1ormKuUHFIrgc8fodsMbWK0u0MXYyzxKtb37uBNiTyFTcb4jWywXFAWi9YD9oXpuyozy1/GipmSP6samW6HfYtAoo8xtFYw03UE13ZwfsliGVnjL+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752009435; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Lvt5JZ2Yb4fVEjOku4Pc7Dra/dQe7u+dFR5T1itnUUE=; b=Klp/9CcFnCUesSPAFZWV4JJgAj6gBYjrGJ0nK9BidunikWm/xoo2eoKlAlViYr2PVz/iiGtPUWyo4GBgHcxN2Zm7LiYanB0ogvGfwbdLjog711n/ls7qAeTS56GVQpUPTCefdNCwG+eCNxCFlmItEmovdJXPIyvBJtzkrg/eicE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752009435336624.0467033592582; Tue, 8 Jul 2025 14:17:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFG6-0006Ps-Ql; Tue, 08 Jul 2025 16:49:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsT-0000jk-Sl for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:25 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsN-00086x-EO for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:15 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:26 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002472; x=1783538472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dCdMwZtfNTWkcMIeigv9JOJVasGlx1kVILv8S0JT6pM=; b=Y6GYObwXJD32sowXHvkRneieF/oOMoNTEQL1HQ7PwwT9m2PEErWGpm0B kuBctwNS6aiXVvIODj76vfYHHal6kqTxFQlj41dJZkDETp2dr0ur5hykL //ZxbyWovFHakIpv9dRa5otPIPElO9gq5CxZN4lvaFSUVOWu12W3FQvqh +Z4rLB4Q+6l4YyP6cRzMvQIXQXccNqSOewazUgPIYfJVF1txWqoXvJZu/ eU9geAHDfW3EChJ3RtNa4w16bjw9XKcG2L+NSkfAPzSnv8d/vfWafrw8r 9SJmaQGzBXZd1JTPScQNylngwrwpUov/8h2F1HM76B6PP0326EdSpqEq+ Q==; X-CSE-ConnectionGUID: N9P0UXIHT2m/rKKGSbR6XQ== X-CSE-MsgGUID: OXhfQxAMS4mkrpyi5e5dPA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974085" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974085" X-CSE-ConnectionGUID: Uf1TDdP3QuGBO9YOaiXiSA== X-CSE-MsgGUID: enIbriHURwWdMzEplbdfZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648020" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 17/20] intel_iommu: Replay all pasid bindings when either SRTP or TE bit is changed Date: Tue, 8 Jul 2025 07:05:58 -0400 Message-ID: <20250708110601.633308-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752009437776116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, all pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_replay_pasid_bindings_all() to go through a= ll pasid entries in all passthrough devices to update host side bindings. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index d8b4296fe4..0a86bd47b2 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -89,6 +89,7 @@ struct vtd_iotlb_key { =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); static void vtd_pasid_cache_sync(IntelIOMMUState *s, @@ -3044,6 +3045,7 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Set Interrupt Remap Table Pointer */ @@ -3078,6 +3080,7 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bo= ol en) =20 vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Handle Interrupt Remap Enable/Disable */ @@ -3758,6 +3761,17 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, } } =20 +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .type =3D VTD_PASID_CACHE_GLOBAL_INV }; + + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + vtd_replay_guest_pasid_bindings(s, &pc_info); +} + /* Update the pasid cache in vIOMMU */ static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) { --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752007814; cv=none; d=zohomail.com; s=zohoarc; b=Lv9rEnKfJaohkuCZSDvxGGdUdVAokcL73P4K63X+KiUu8Ti/pFiy5Tjrx++1gtKB2tJa4XSkDZsZchlzTQNDxuHkT/AfRhdFZEyDAC1d9wb8TyiaGW28r09CSXt6w1bqc9mDLaVyPPGMS7TB3hYAZHoWMHzPFFWqAIdXMx/tn1I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752007814; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2ct0zZ76i7nj2pzIjRieUm+15+WoeOi0VH20P6sFTlU=; b=NgVFByPWGLh841TBu+KATI5vIWI2kuNtYodVZ4oH0hfEIGn2ZQBluLbXD4OOplkRRAwrynRcv6MhFATYdhYlWFnRwonG8f4st8WyxMh+fiwZs3LHfvU6ivlXa8Tax5OPDWACo6YKGAPFPArNBGxWA3DJBaEax/mtVlGVbOtv4eY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752007814490839.3540527066871; Tue, 8 Jul 2025 13:50:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFDi-0003tw-NH; Tue, 08 Jul 2025 16:47:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsP-0000iS-Sd for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:16 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsK-00082f-Oy for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:12 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:30 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002469; x=1783538469; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=87jeU0Q5s4cmeTgXORj6Zg9qNbO+ELiEuV0x8pWO1/Q=; b=ZLyE9pCwc0rp1tSE13nZ7RmsdGl5+gfMCFFa0F/DtX2v/O7Nvb1v9agh 06vuuzSGcEew2nvngNeqwzYjJV/xP6wIlEhsRKF2N+Gnah3bVxIrPs0PP ir/Qd0q+FgLBqjcD9jpuOCUb7Kt0fz6StOq+Bup+O1swao+Jlwi9B6n6J xUI5awxxfJFHLWJRbEz5y/aRgRll7J3kk8DAHtmba3pmAq6RkwA7fKZMI 2ECTJoBJexr8sYreJT2aqVcQFlkkdgkPKUs7QIEdIUcJwbHVGiEz3ZXY/ nRCZBPi6fCKyiF5zw0eLVYxpm4fWEMWuPwzn4Yp2KZ7DP6G41g9D5RWZC w==; X-CSE-ConnectionGUID: lEh9z6YnSzeGiwiDC290wQ== X-CSE-MsgGUID: X8H2FAt+RkWPvblg2AIrVg== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974091" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974091" X-CSE-ConnectionGUID: zqMh02LdT7OpYEH8kIqbtw== X-CSE-MsgGUID: Nn+hzOVxRYCkLvVyGLSM/Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648024" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 18/20] vfio: Add a new element bypass_ro in VFIOContainerBase Date: Tue, 8 Jul 2025 07:05:59 -0400 Message-ID: <20250708110601.633308-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752007815504116600 Content-Type: text/plain; charset="utf-8" When bypass_ro is true, read only memory section is bypassed from mapping in the container. This is a preparing patch to workaround Intel ERRATA_772415. Signed-off-by: Zhenzhong Duan --- hw/vfio/listener.c | 13 +++++++++---- include/hw/vfio/vfio-container-base.h | 1 + 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index f498e23a93..c64aa4539e 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -364,7 +364,8 @@ static bool vfio_known_safe_misalignment(MemoryRegionSe= ction *section) return true; } =20 -static bool vfio_listener_valid_section(MemoryRegionSection *section, +static bool vfio_listener_valid_section(VFIOContainerBase *bcontainer, + MemoryRegionSection *section, const char *name) { if (vfio_listener_skipped_section(section)) { @@ -375,6 +376,10 @@ static bool vfio_listener_valid_section(MemoryRegionSe= ction *section, return false; } =20 + if (bcontainer && bcontainer->bypass_ro && section->readonly) { + return false; + } + if (unlikely((section->offset_within_address_space & ~qemu_real_host_page_mask()) !=3D (section->offset_within_region & ~qemu_real_host_page_mas= k()))) { @@ -494,7 +499,7 @@ void vfio_container_region_add(VFIOContainerBase *bcont= ainer, int ret; Error *err =3D NULL; =20 - if (!vfio_listener_valid_section(section, "region_add")) { + if (!vfio_listener_valid_section(bcontainer, section, "region_add")) { return; } =20 @@ -655,7 +660,7 @@ static void vfio_listener_region_del(MemoryListener *li= stener, int ret; bool try_unmap =3D true; =20 - if (!vfio_listener_valid_section(section, "region_del")) { + if (!vfio_listener_valid_section(bcontainer, section, "region_del")) { return; } =20 @@ -812,7 +817,7 @@ static void vfio_dirty_tracking_update(MemoryListener *= listener, container_of(listener, VFIODirtyRangesListener, listener); hwaddr iova, end; =20 - if (!vfio_listener_valid_section(section, "tracking_update") || + if (!vfio_listener_valid_section(NULL, section, "tracking_update") || !vfio_get_section_iova_range(dirty->bcontainer, section, &iova, &end, NULL)) { return; diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-c= ontainer-base.h index bded6e993f..31fd784d76 100644 --- a/include/hw/vfio/vfio-container-base.h +++ b/include/hw/vfio/vfio-container-base.h @@ -51,6 +51,7 @@ typedef struct VFIOContainerBase { QLIST_HEAD(, VFIODevice) device_list; GList *iova_ranges; NotifierWithReturn cpr_reboot_notifier; + bool bypass_ro; } VFIOContainerBase; =20 typedef struct VFIOGuestIOMMU { --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752008128; cv=none; d=zohomail.com; s=zohoarc; b=Ro34TiKhdJZ13BfJYgcXiU/yum5csOMUo1WWFZ4g0S3wOB6OpuZ9p1gxb7NILfgkl63PlClVMT03tNtzKonK+zQP2wldONfBU6CXgojgZ8xPqomQJIzP2sMD9fpxfOhIJa4aB5UDDEobEoXwpYUjUIvMs7LjTdfm63GyiHtz4jE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752008128; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0oRMwhv3LIX8m13nK9/ydatU+MugeBNMg+jrzEcjFKA=; b=TBFF6EU/WFDqsuxRTAtOZUBcZKj9GqQ+zse01G1BfcH0eFF35KdF100dDaKBuq33N1bdFUxiwvzFrUfIqYXQR0Hz+9JI2tmqday0bCXkCvK7uCxRRQ35g6ut6Qt7zsURv+FScelZpQg9i/fuf3psFraKtF3WxlRbTV5nLVvVdD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752008128511391.1546266473573; Tue, 8 Jul 2025 13:55:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFFp-0004XQ-1n; Tue, 08 Jul 2025 16:49:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsd-0000rt-Or for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:31 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsW-0008BN-OH for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:24 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:34 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002481; x=1783538481; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jDbFGrl3ticFY3df04LBd7wGvPRkWrzxn5Mt/fsOwnA=; b=Vb3X+vW1CWXAieet+/Tllz1N+TluGzDvqn4Bf1QAJWNux0C9orPqPv3u ulY96EAW0haSlAr1L6OPDOgItNqpoMpNR++kIvYfhv0t509koFbL7oVV4 CDL1CDbAsRaboL6MCIUCU1vZjxBpWqLKMTF6a2Ekn26TCopcTsZunMfYU QIZm5esr/6X0dg+QNNmS5P5rrryt/BVvEcGO9fTSmTQvW/dMCOXPEwqnd 7Zd1mpKrb6/AmEQHDL5EFGSzG8+c/tHBQKiCjj6eJc5p0kWeQYz2ItTMM VIdZTtTB65Wim1pFtK8wEOLfz7eNrqim6p+QHZpqLyzQqBBrTnPPMYfYl w==; X-CSE-ConnectionGUID: W7f8cO4URXaJa811pFFmog== X-CSE-MsgGUID: 2TLv7zLNT6SGlz+0d2hAbg== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974103" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974103" X-CSE-ConnectionGUID: p4i2uV9OS1msSi87NyPOIg== X-CSE-MsgGUID: keQvgkTcRAC6lVHII13CQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648034" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 19/20] Workaround for ERRATA_772415_SPR17 Date: Tue, 8 Jul 2025 07:06:00 -0400 Message-ID: <20250708110601.633308-20-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752008130745116600 Content-Type: text/plain; charset="utf-8" On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SP= R17 is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readon= ly range mapped on stage-2 page table could still be written. Reference from 4th Gen Intel Xeon Processor Scalable Family Specification Update, Errata Details, SPR17. https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/eagle-stream/sapphire-rapids-specification-update/ Also copied the SPR17 details from above link: "Problem: When remapping hardware is configured by system software in scalable mode as Nested (PGTT=3D011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only. Implication: Due to this erratum, pages mapped as Read-only in second-stage page-tables may be modified by remapping hardware Access/Dirty bit updates. Workaround: None identified. System software enabling nested translations for a VM should ensure that there are no read-only pages in the corresponding second-stage mappings." Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index c172c177fc..a28641b5f5 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -325,6 +325,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, { ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; + struct iommu_hw_info_vtd vtd; uint32_t type, flags =3D 0; uint64_t hw_caps; VFIOIOASHwpt *hwpt; @@ -372,10 +373,15 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *= vbasedev, * instead. */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, - &type, NULL, 0, &hw_caps, errp)) { + &type, &vtd, sizeof(vtd), &hw_cap= s, + errp)) { return false; } =20 + if (vtd.flags & IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17) { + container->bcontainer.bypass_ro =3D true; + } + if (hw_caps & IOMMU_HW_CAP_DIRTY_TRACKING) { flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } --=20 2.47.1 From nobody Sat Nov 15 12:16:21 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1752007804; cv=none; d=zohomail.com; s=zohoarc; b=OxjIoDZOlFIMPSdu7SArqB4L9XCfVLqOcMgt3AI7xaIioTv/sdG7BOCmoLmxawxGYQcNGqyprzL2tHQ9qHlimNctr/G3vCy9Uk62P/lgvAStZQ+Sq4zKfIhHDQijGOgkJDNxr/I/aAmZidw/9rt0O3F3fFy7zcM9K1frczi9lP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752007804; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rqyNJVcMrOQd2kyJzidceTZk0heQJCBLBtpUWPfe9vs=; b=a9lvCR8OYe66Rjd4IH7z1SMH54EPuClFlM3oI9txptMFN/rHplepI9cqoIQ2GYv3p1AqUyBCVCLFQLmSfezDhMCInAmAXiF7/1iguppKUiiOwCRL5rXYRgBrjn6KWWwzbrmP9plCc+mXpIkkkUTdG/DUtHWR+QfRQRh1SsvN+Bg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1752007804730321.7637663469469; Tue, 8 Jul 2025 13:50:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uZFGA-0006o2-VH; Tue, 08 Jul 2025 16:49:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsf-0000yp-BH for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:31 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uZDsb-00082f-3f for qemu-devel@nongnu.org; Tue, 08 Jul 2025 15:21:28 -0400 Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:38 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2025 04:07:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752002486; x=1783538486; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ecCMAEtIFZ0ONaJFrbOrf4SBvoPdLunNt7lfHH3s8UY=; b=jeA58G/HieA9NtX8l3t7V7WTe6RY1nvZ0Xi57SoNn3I4MQyee1XAd9+i PKfmr+dMF1/YiLF1nzDq8CB/Z4IA9Epz14yTYvainRTwAIyA2OzPwhmVP LTjwIGOOynuItaHszuHbHlCXSAp3iJMxFvV5NLzNysPCKjQJjqRYXrmHc J9Ye2jicXzNil9e6Eebwofd2JI1Yi6jq5tMqlP14m+BZlOCLO5lRpFA6C GUFqzq7u0Zuybkf0qzIzhRRUoofAzzNnN3jei5r8Bu9w+SeYMotLKUt86 KOEuRuQ6eD/e5AdouWgycQKUZkVemjEJWgX3RZJ3Rnn0ovWL4SXquXXdV Q==; X-CSE-ConnectionGUID: Yr26/+RuQaCfGGUQqkpJ4Q== X-CSE-MsgGUID: lIEkm4RDT168lrMcz7mHAA== X-IronPort-AV: E=McAfee;i="6800,10657,11487"; a="57974127" X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="57974127" X-CSE-ConnectionGUID: eRaIQmN4TweP5v58V4pByA== X-CSE-MsgGUID: 1GRpPe+SQhCAGO2avQ47Kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,297,1744095600"; d="scan'208";a="192648042" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, shameerali.kolothum.thodi@huawei.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v3 20/20] intel_iommu: Enable host device when x-flts=on in scalable mode Date: Tue, 8 Jul 2025 07:06:01 -0400 Message-ID: <20250708110601.633308-21-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250708110601.633308-1-zhenzhong.duan@intel.com> References: <20250708110601.633308-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1752007805337116600 Content-Type: text/plain; charset="utf-8" Now that all infrastructures of supporting passthrough device running with stage-1 translation are there, enable it now. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0a86bd47b2..08e4d5cfe7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5203,6 +5203,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, VTDHos= tIOMMUDevice *vtd_hiod, "when x-flts=3Don"); return false; } + + return true; #endif =20 error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); --=20 2.47.1