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Mon, 07 Jul 2025 13:21:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/20] target/arm: Convert v8m_security_lookup to access_perm Date: Mon, 7 Jul 2025 14:20:59 -0600 Message-ID: <20250707202111.293787-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250707202111.293787-1-richard.henderson@linaro.org> References: <20250707202111.293787-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::831; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x831.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751922177944116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/ptw.c | 8 ++++---- target/arm/tcg/m_helper.c | 7 +++---- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 629aa7bc23..1781943fac 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1535,7 +1535,7 @@ typedef struct V8M_SAttributes { } V8M_SAttributes; =20 void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + unsigned access_perm, ARMMMUIdx mmu_idx, bool secure, V8M_SAttributes *sattrs); =20 /* Cacheability and shareability attributes for a memory access */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 78a9c21fab..709dfa2684 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2770,7 +2770,7 @@ static bool v8m_is_sau_exempt(CPUARMState *env, } =20 void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + unsigned access_perm, ARMMMUIdx mmu_idx, bool is_secure, V8M_SAttributes *sattrs) { /* @@ -2793,12 +2793,12 @@ void v8m_security_lookup(CPUARMState *env, uint32_t= address, &idau_nsc); } =20 - if (access_type =3D=3D MMU_INST_FETCH && extract32(address, 28, 4) =3D= =3D 0xf) { + if ((access_perm & PAGE_EXEC) && extract32(address, 28, 4) =3D=3D 0xf)= { /* 0xf0000000..0xffffffff is always S for insn fetches */ return; } =20 - if (idau_exempt || v8m_is_sau_exempt(env, address, 1 << access_type)) { + if (idau_exempt || v8m_is_sau_exempt(env, address, access_perm)) { sattrs->ns =3D !is_secure; return; } @@ -2891,7 +2891,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, bool ret; =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - v8m_security_lookup(env, address, access_type, mmu_idx, + v8m_security_lookup(env, address, 1 << access_type, mmu_idx, secure, &sattrs); if (access_type =3D=3D MMU_INST_FETCH) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 220a3b472f..e52ab261be 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -684,7 +684,7 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, b= ool targets_secure, if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { V8M_SAttributes sattrs =3D {}; =20 - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + v8m_security_lookup(env, addr, PAGE_READ, mmu_idx, targets_secure, &sattrs); if (sattrs.ns) { attrs.secure =3D false; @@ -1996,7 +1996,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx= mmu_idx, bool secure, ARMMMUFaultInfo fi =3D {}; MemTxResult txres; =20 - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattr= s); + v8m_security_lookup(env, addr, PAGE_EXEC, mmu_idx, secure, &sattrs); if (!sattrs.nsc || sattrs.ns) { /* * This must be the second half of the insn, and it straddles a @@ -2838,8 +2838,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) } =20 if (env->v7m.secure) { - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - targetsec, &sattrs); + v8m_security_lookup(env, addr, PAGE_READ, mmu_idx, targetsec, &sat= trs); nsr =3D sattrs.ns && r; nsrw =3D sattrs.ns && rw; } else { --=20 2.43.0