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Tsirkin" , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , qemu-block@nongnu.org, Richard Henderson , qemu-ppc@nongnu.org, Paolo Bonzini , qemu-riscv@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-10.1 v6 04/14] qemu/target-info: Introduce target_base_arch() Date: Mon, 7 Jul 2025 19:19:58 +0200 Message-ID: <20250707172009.3884-5-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250707172009.3884-1-philmd@linaro.org> References: <20250707172009.3884-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751908991263116600 target_base_arch() returns the base architecture as in QEMU target/$arch/ path. For example, X86_64 is implemented in the target/i386/ so its QEMU base arch is 'i386'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/target-info-impl.h | 2 ++ include/qemu/target-info-qapi.h | 7 +++++++ target-info-stub.c | 1 + target-info.c | 10 ++++++++++ 4 files changed, 20 insertions(+) diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-imp= l.h index a8b34d150ab..c5aea6fa6d2 100644 --- a/include/qemu/target-info-impl.h +++ b/include/qemu/target-info-impl.h @@ -16,6 +16,8 @@ typedef struct TargetInfo { const char *target_name; /* related to TARGET_ARCH definition */ SysEmuTarget target_arch; + /* related to TARGET_BASE_ARCH definition (target/${base_arch}/ path) = */ + SysEmuTarget target_base_arch; /* runtime equivalent of TARGET_LONG_BITS definition */ unsigned long_bits; /* runtime equivalent of CPU_RESOLVING_TYPE definition */ diff --git a/include/qemu/target-info-qapi.h b/include/qemu/target-info-qap= i.h index dae92c47eb1..5d63fc4ab84 100644 --- a/include/qemu/target-info-qapi.h +++ b/include/qemu/target-info-qapi.h @@ -18,4 +18,11 @@ */ SysEmuTarget target_arch(void); =20 +/** + * target_base_arch: + * + * Returns: QAPI SysEmuTarget enum (i.e. SYS_EMU_TARGET_I386). + */ +SysEmuTarget target_base_arch(void); + #endif diff --git a/target-info-stub.c b/target-info-stub.c index 2e4407ff04b..c0f438b45c4 100644 --- a/target-info-stub.c +++ b/target-info-stub.c @@ -15,6 +15,7 @@ static const TargetInfo target_info_stub =3D { .target_name =3D TARGET_NAME, .target_arch =3D SYS_EMU_TARGET__MAX, + .target_base_arch =3D SYS_EMU_TARGET__MAX, .long_bits =3D TARGET_LONG_BITS, .cpu_type =3D CPU_RESOLVING_TYPE, .machine_typename =3D TYPE_MACHINE, diff --git a/target-info.c b/target-info.c index 8e29553b4ef..46780ec5450 100644 --- a/target-info.c +++ b/target-info.c @@ -33,6 +33,16 @@ SysEmuTarget target_arch(void) return arch; } =20 +SysEmuTarget target_base_arch(void) +{ + SysEmuTarget base_arch =3D target_info()->target_base_arch; + + if (base_arch =3D=3D SYS_EMU_TARGET__MAX) { + base_arch =3D target_arch(); + } + return base_arch; +} + const char *target_cpu_type(void) { return target_info()->cpu_type; --=20 2.49.0