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charset="utf-8" From: Haibo Xu Allow virt arm machine to set the interrupt ID for the KVM GIC maintenance interrupt. This setting must be done before the KVM_DEV_ARM_VGIC_CTRL_INIT hence the choice to perform the setting in the GICv3 realize instead of proceeding the same way as kvm_arm_pmu_set_irq(). Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger --- v3 -> v4: - only set maint_irq if vms->virt v2 -> v3: - tweak the commit message and explain why we do not proceed the same way as kvm_arm_pmu_set_irq (Peter) v1 -> v2: - [Miguel] replaced the has_virt_extensions by the maintenance irq intid property. [Eric] restored kvm_device_check_attr and kvm_device_access standard usage and conditionally call those if the prop is set. --- include/hw/intc/arm_gicv3_common.h | 1 + hw/arm/virt.c | 3 +++ hw/intc/arm_gicv3_common.c | 1 + hw/intc/arm_gicv3_kvm.c | 21 +++++++++++++++++++++ 4 files changed, 26 insertions(+) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index a3d6a0e507..c18503869f 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -231,6 +231,7 @@ struct GICv3State { uint32_t num_cpu; uint32_t num_irq; uint32_t revision; + uint32_t maint_irq; bool lpi_enable; bool nmi_support; bool security_extn; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3bcdf92e2f..550a272fbb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -828,6 +828,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) OBJECT(mem), &error_fatal); qdev_prop_set_bit(vms->gic, "has-lpi", true); } + } else if (vms->virt) { + qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", + ARCH_GIC_MAINT_IRQ); } } else { if (!kvm_irqchip_in_kernel()) { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 1cee68193c..e438d8c042 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -612,6 +612,7 @@ static const Property arm_gicv3_common_properties[] =3D= { DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), + DEFINE_PROP_UINT32("maintenance-interrupt-id", GICv3State, maint_irq, = 0), /* * Compatibility property: force 8 bits of physical priority, even * if the CPU being emulated should have fewer. diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3be3bf6c28..b30aac7aee 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -22,6 +22,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/arm/virt.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "system/kvm.h" @@ -825,6 +826,26 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) return; } =20 + if (s->maint_irq) { + int ret; + + ret =3D kvm_device_check_attr(s->dev_fd, + KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); + if (!ret) { + error_setg_errno(errp, errno, + "VGICv3 setting maintenance IRQ is not " + "supported by this host kernel"); + return; + } + + ret =3D kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IR= Q, 0, + &s->maint_irq, true, errp); + if (ret) { + error_setg_errno(errp, errno, "Failed to set VGIC maintenance = IRQ"); + return; + } + } + multiple_redist_region_allowed =3D kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ADDR, KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION); --=20 2.49.0 From nobody Sat Dec 13 23:02:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1751906563; cv=none; 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Mon, 7 Jul 2025 16:41:49 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.32.187]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 957C718003FC; Mon, 7 Jul 2025 16:41:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1751906512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Y7zgkic6Vn3Gg62tyqYV3n0+jagdb6H2rJ2Bf3rpzog=; b=S6QMg+BsvIqWbqrHOkQzGfLybxBT1+bRiWZtPQCGNvzh/9o8WdhrQh2CdcK8YSs2obyY0S /Se9KueV2is0PrZaBFl35oCk6zH5o4gzKvm6DS7mko8XW0ronhmSl9dnzGKBLgARZlfjPy 6737FLNfnOtA0o53Nd4dc291MZGbbhM= X-MC-Unique: Vy6HWRAaO4WQhhZEBAaNXA-1 X-Mimecast-MFC-AGG-ID: Vy6HWRAaO4WQhhZEBAaNXA_1751906509 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, miguel.luis@oracle.com, peter.maydell@linaro.org, richard.henderson@linaro.org, maz@kernel.org, gkulkarni@amperecomputing.com, gankulkarni@os.amperecomputing.com Cc: hi@alyssa.is Subject: [PATCH v9 2/5] target/arm/kvm: Add helper to detect EL2 when using KVM Date: Mon, 7 Jul 2025 18:40:28 +0200 Message-ID: <20250707164129.1167837-3-eric.auger@redhat.com> In-Reply-To: <20250707164129.1167837-1-eric.auger@redhat.com> References: <20250707164129.1167837-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1751906564521116600 From: Haibo Xu Introduce query support for KVM_CAP_ARM_EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm_arm.h | 7 +++++++ target/arm/kvm-stub.c | 5 +++++ target/arm/kvm.c | 5 +++++ 3 files changed, 17 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 7dc83caed5..b4cad05155 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -191,6 +191,13 @@ bool kvm_arm_sve_supported(void); */ bool kvm_arm_mte_supported(void); =20 +/** + * kvm_arm_el2_supported: + * + * Returns true if KVM can enable EL2 and false otherwise. + */ +bool kvm_arm_el2_supported(void); + /** * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 34e57fab01..c93462c5b9 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -47,6 +47,11 @@ bool kvm_arm_mte_supported(void) return false; } =20 +bool kvm_arm_el2_supported(void) +{ + return false; +} + /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 426f8b159e..e5708e54ae 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1762,6 +1762,11 @@ bool kvm_arm_aarch32_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); 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charset="utf-8" From: Haibo Xu KVM_CAP_ARM_EL2 must be supported by the cpu to enable ARM_FEATURE_EL2. In case the host does support NV, expose the feature. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson --- v2 -> v3: - check pmu->has_el2 on kvm_arch_init_vcpu() when setting KVM_ARM_VCPU_HAS_EL2 feature (Peter) v1 -> v2: - remove isar_feature_aa64_aa32_el2 modif in target/arm/cpu.h [Richard] and use el2_supported in kvm_arch_init_vcpu --- target/arm/kvm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e5708e54ae..46e5f19637 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -250,6 +250,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) */ int fdarray[3]; bool sve_supported; + bool el2_supported; bool pmu_supported =3D false; uint64_t features =3D 0; int err; @@ -269,6 +270,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; } =20 + /* + * Ask for EL2 if supported. + */ + el2_supported =3D kvm_arm_el2_supported(); + if (el2_supported) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; + } + /* * Ask for Pointer Authentication if supported, so that we get * the unsanitized field values for AA64ISAR1_EL1. @@ -422,6 +431,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) features |=3D 1ULL << ARM_FEATURE_AARCH64; features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; =20 + if (el2_supported) { + features |=3D 1ULL << ARM_FEATURE_EL2; + } + ahcf->features =3D features; =20 return true; @@ -1887,6 +1900,9 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); } + if (cpu->has_el2 && kvm_arm_el2_supported()) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_HAS_EL2; + } =20 /* Do KVM_ARM_VCPU_INIT ioctl */ ret =3D kvm_arm_vcpu_init(cpu); --=20 2.49.0 From nobody Sat Dec 13 23:02:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=T+w8opYkCAX1Lv1IexSr5cdwB8R+aGKdoquyLGoJlbsahTm9e3/4Fq/HEDtKm83CiTNhJO JIq0T2VfEELF4e1XSrttbnRqnM5CS3sbCXAUHw48B3riGI1CRgfJU2oth2hZbFZC4fdCmi 6WM7DKQ1/C0kmmMKmpVeiVpR0bWLfB4= X-MC-Unique: E-35iN02Ot6wS8fewfBnhA-1 X-Mimecast-MFC-AGG-ID: E-35iN02Ot6wS8fewfBnhA_1751906518 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, miguel.luis@oracle.com, peter.maydell@linaro.org, richard.henderson@linaro.org, maz@kernel.org, gkulkarni@amperecomputing.com, gankulkarni@os.amperecomputing.com Cc: hi@alyssa.is Subject: [PATCH v9 4/5] hw/arm/arm_gicv3_kvm: Add a migration blocker with kvm nested virt Date: Mon, 7 Jul 2025 18:40:30 +0200 Message-ID: <20250707164129.1167837-5-eric.auger@redhat.com> In-Reply-To: <20250707164129.1167837-1-eric.auger@redhat.com> References: <20250707164129.1167837-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We may be miss some NV related GIC register save/restore. Until we complete the study, let's add a migration blocker when the maintenance IRQ is set. Signed-off-by: Eric Auger Suggested-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index b30aac7aee..fccb3886bf 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -827,8 +827,16 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Er= ror **errp) } =20 if (s->maint_irq) { + Error *kvm_nv_migration_blocker =3D NULL; int ret; =20 + error_setg(&kvm_nv_migration_blocker, + "Live migration disabled due to KVM nested virt ena= bled"); + if (migrate_add_blocker(&kvm_nv_migration_blocker, errp)) { + error_free(kvm_nv_migration_blocker); + return; + } + ret =3D kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ, 0); if (!ret) { --=20 2.49.0 From nobody Sat Dec 13 23:02:24 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Haibo Xu Up to now virt support on guest has been only supported with TCG. Now it becomes feasible to use it with KVM acceleration. Check neither in-kernel GICv3 nor aarch64=3Doff is used along with KVM EL2. Signed-off-by: Haibo Xu Signed-off-by: Miguel Luis Signed-off-by: Eric Auger Reviewed-by: Richard Henderson --- v8 -> v9: - remove the migration blocker from the machine code as it is now in the GIC code itself. v7 -> v8: - add the migration blocker - s/only is/is only - check aarch64=3Doff - update the commit message v6 -> v7: - rebase on top of "hw/arm/virt: Make EL2 accelerator check an accept-list". I dared to keep Richard's R-b though. v2 -> v3: - check gic version/in-kernel implementation when kvm el2 is set (Peter) v1 -> v2: - fixed test ordering: virt && ((kvm && !kvm_el2) || hvf) [Richard] - tweeked the commit title & message --- hw/arm/virt.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 550a272fbb..6f5339aade 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -792,6 +792,13 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) default: g_assert_not_reached(); } + + if (kvm_enabled() && vms->virt && + (revision !=3D 3 || !kvm_irqchip_in_kernel())) { + error_report("KVM EL2 is only supported with in-kernel GICv3"); + exit(1); + } + vms->gic =3D qdev_new(gictype); qdev_prop_set_uint32(vms->gic, "revision", revision); qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); @@ -2066,6 +2073,10 @@ static void virt_post_cpus_gic_realized(VirtMachineS= tate *vms, memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NU= LL); memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime); } + if (!aarch64 && vms->virt) { + error_report("vcpu with both EL1_32BIT and HAS_EL2 is not supp= orted"); + exit(1); + } =20 CPU_FOREACH(cpu) { if (pmu) { @@ -2211,7 +2222,8 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - if (vms->virt && !tcg_enabled() && !qtest_enabled()) { + if (vms->virt && !(kvm_enabled() && kvm_arm_el2_supported()) && + !tcg_enabled() && !qtest_enabled()) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", current_accel_name()); --=20 2.49.0