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Fri, 04 Jul 2025 09:57:33 -0700 (PDT) From: Jackson Donaldson X-Google-Original-From: Jackson Donaldson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PATCH v3 03/11] MAX78000: Add ICC to SOC Date: Fri, 4 Jul 2025 12:57:21 -0400 Message-Id: <20250704165729.208381-4-jcksn@duck.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704165729.208381-1-jcksn@duck.com> References: <20250704165729.208381-1-jcksn@duck.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=jackson88044@gmail.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1751648283428116600 Content-Type: text/plain; charset="utf-8" This commit adds the instruction cache controller to max78000_soc Signed-off-by: Jackson Donaldson Reviewed-by: Peter Maydell --- hw/arm/max78000_soc.c | 20 ++++++++++++++++---- include/hw/arm/max78000_soc.h | 6 ++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c index 9676ada6a2..0c83b08eca 100644 --- a/hw/arm/max78000_soc.c +++ b/hw/arm/max78000_soc.c @@ -17,12 +17,20 @@ #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" =20 +static const uint32_t max78000_icc_addr[] =3D {0x4002a000, 0x4002a800}; + static void max78000_soc_initfn(Object *obj) { MAX78000State *s =3D MAX78000_SOC(obj); + int i; =20 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + g_autofree char *name =3D g_strdup_printf("icc%d", i); + object_initialize_child(obj, name, &s->icc[i], TYPE_MAX78000_ICC); + } + s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); } =20 @@ -30,8 +38,9 @@ static void max78000_soc_realize(DeviceState *dev_soc, Er= ror **errp) { MAX78000State *s =3D MAX78000_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); - DeviceState *armv7m; + DeviceState *dev, *armv7m; Error *err =3D NULL; + int i; =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); @@ -74,6 +83,12 @@ static void max78000_soc_realize(DeviceState *dev_soc, E= rror **errp) return; } =20 + for (i =3D 0; i < MAX78000_NUM_ICC; i++) { + dev =3D DEVICE(&(s->icc[i])); + sysbus_realize(SYS_BUS_DEVICE(dev), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, max78000_icc_addr[i]); + } + create_unimplemented_device("globalControl", 0x40000000, 0x400); create_unimplemented_device("systemInterface", 0x40000400, 0x400); create_unimplemented_device("functionControl", 0x40000800, 0x400); @@ -107,9 +122,6 @@ static void max78000_soc_realize(DeviceState *dev_soc, = Error **errp) create_unimplemented_device("standardDMA", 0x40028000, 0x1000= ); create_unimplemented_device("flashController0", 0x40029000, 0x400); =20 - create_unimplemented_device("icc0", 0x4002a000, 0x800); - create_unimplemented_device("icc1", 0x4002a800, 0x800); - create_unimplemented_device("adc", 0x40034000, 0x1000= ); create_unimplemented_device("pulseTrainEngine", 0x4003c000, 0xa0); create_unimplemented_device("oneWireMaster", 0x4003d000, 0x1000= ); diff --git a/include/hw/arm/max78000_soc.h b/include/hw/arm/max78000_soc.h index 97bf4099c9..27b506d6ee 100644 --- a/include/hw/arm/max78000_soc.h +++ b/include/hw/arm/max78000_soc.h @@ -11,6 +11,7 @@ =20 #include "hw/or-irq.h" #include "hw/arm/armv7m.h" +#include "hw/misc/max78000_icc.h" #include "qom/object.h" =20 #define TYPE_MAX78000_SOC "max78000-soc" @@ -21,6 +22,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(MAX78000State, MAX78000_SOC) #define SRAM_BASE_ADDRESS 0x20000000 #define SRAM_SIZE (128 * 1024) =20 +/* The MAX78k has 2 instruction caches; only icc0 matters, icc1 is for RIS= C */ +#define MAX78000_NUM_ICC 2 + struct MAX78000State { SysBusDevice parent_obj; =20 @@ -29,6 +33,8 @@ struct MAX78000State { MemoryRegion sram; MemoryRegion flash; =20 + Max78000IccState icc[MAX78000_NUM_ICC]; + Clock *sysclk; }; =20 --=20 2.34.1