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This will be helpful later for predicate as counter. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-76-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 2 ++ target/arm/tcg/translate-sve.c | 13 +++++-------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 5e11e86e5e0..b8f3fbb816c 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4133,6 +4133,7 @@ uint32_t HELPER(sve_whilel)(void *vd, uint32_t count,= uint32_t pred_desc) uint64_t esz_mask =3D pred_esz_masks[esz]; ARMPredicateReg *d =3D vd; =20 + count <<=3D esz; memset(d, 0, sizeof(*d)); do_whilel(d, esz_mask, count, oprbits); return pred_count_test(oprbits, count, false); @@ -4165,6 +4166,7 @@ uint32_t HELPER(sve_whileg)(void *vd, uint32_t count,= uint32_t pred_desc) uint64_t esz_mask =3D pred_esz_masks[esz]; ARMPredicateReg *d =3D vd; =20 + count <<=3D esz; memset(d, 0, sizeof(*d)); do_whileg(d, esz_mask, count, oprbits); return pred_count_test(oprbits, count, true); diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 210a029ab84..f74f2bb1b38 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3198,9 +3198,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, t0); =20 - /* Scale elements to bits. */ - tcg_gen_shli_i32(t2, t2, a->esz); - desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); =20 @@ -3234,7 +3231,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) op0 =3D read_cpu_reg(s, a->rn, 1); op1 =3D read_cpu_reg(s, a->rm, 1); =20 - tmax =3D tcg_constant_i64(vsz); + tmax =3D tcg_constant_i64(vsz >> a->esz); diff =3D tcg_temp_new_i64(); =20 if (a->rw) { @@ -3244,15 +3241,15 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WH= ILE_ptr *a) tcg_gen_sub_i64(diff, op0, op1); tcg_gen_sub_i64(t1, op1, op0); tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); - /* Round down to a multiple of ESIZE. */ - tcg_gen_andi_i64(diff, diff, -1 << a->esz); + /* Divide, rounding down, by ESIZE. */ + tcg_gen_shri_i64(diff, diff, a->esz); /* If op1 =3D=3D op0, diff =3D=3D 0, and the condition is always t= rue. */ tcg_gen_movcond_i64(TCG_COND_EQ, diff, op0, op1, tmax, diff); } else { /* WHILEWR */ tcg_gen_sub_i64(diff, op1, op0); - /* Round down to a multiple of ESIZE. */ - tcg_gen_andi_i64(diff, diff, -1 << a->esz); + /* Divide, rounding down, by ESIZE. */ + tcg_gen_shri_i64(diff, diff, a->esz); /* If op0 >=3D op1, diff <=3D 0, the condition is always true. */ tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, tmax, diff); } --=20 2.43.0