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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b96534sm2816857f8f.48.2025.07.04.09.26.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751646381; x=1752251181; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=B5CANpDPQWpyeOcAzPhRg6M8ZmHELAiHl2F8gI+LHZk=; b=LQgj2my3gu84UXza3pqgryCJLPsvf/cPqDyfTDASVQvp0rHk34EwBNbDuRq0tLcJS1 uwZVuuPiC9B7dweiVElyHWPh56zsCQ7eK8Q0plBxu5elzcpSYZSDUKzKDWYAyPzheSDI 3CONpbSDX9YA+AZarWpbwGclRVRcU8pIi2M8lJBwk1AoXelCNF3dsbuSgUWOh+n8mdpf DsvLiox839LaiJLWHP71c/uosdzzagjCfZhT2THkVIhXve4Xref3HF2cMzY0L0XHEMA5 NXfRPH5KNd/4SSCDzrYgUoJzROZ5QLH/K9i7DZfbBLA6JysnDu7RvAfjJIDfFSdNCkiZ hbXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646381; x=1752251181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B5CANpDPQWpyeOcAzPhRg6M8ZmHELAiHl2F8gI+LHZk=; b=iIXQX/0t/qiIfJSjz222rp+hGeKP4YZ8RqMDbdbKlzU8WdU+zRJwxwvq5MBYiNuBxK j1xMzn+TqsdHLrDlyZMpUTTFVKqYmbQhlUDBqW0hdrPi0UvWoctTcVKlYY1Azt/nsyaM CAVDCzJ/qbosulPOfOstq+EnX7k3MJSg+L6wVvkOJFJp0knf42snngjMcqiJRsjlq/+W h1/MGmHbi/tmAv1jLa1L4XBqZeqWe1leeDNc8RqPcGPjGjCfaBdyP6E2z7BQHO5lJ0R8 J6g4nru/hvm4ezpeWAq8flMuq33YjqkHNIHhtghfbuyuepZra8XMZ4yXj8nex+THB1+t ok4Q== X-Gm-Message-State: AOJu0YzGdm5hzXbXWXAvBqXRVtk5hd27Pxb22Jr2pCkkdaWqjExWt5ax kDS2CWjAhUZ8t4MQHAIj1abXqcf6i3Fzdo86x+hLhnw4CQxsy1NmEFS1neFFQAWISoNugBX4p4d se+68 X-Gm-Gg: ASbGncvhIj4yDcG+YYEqtuYMm0Ef8cG0bdC2/ZXfyYsv9tmlivBkL4NC/65DQMMFUYj /wd3om+ebdLa0wVwGzVONduIHT0O20HL97o/ful/qGz51GX+zu6PDHTPF8WajQ3iCwZZ0CWpvEr 54uWP2FpTng3KfUhLYum/e039cZ9qRwcVQnroXuqEhFDMvniWWqQNrSVpnO0zsNwA7FfWWHQb3k eaMfpX5vPwc8d7mv4AOFwTQy1bJ8BBNW/fjLYUv907fNSw136MNSdPftmV0d+lf9ZPgUaYBhxXy hlJF/u+q5j8SKtmgFYa5wCSHKcXv6IcJlS2k2HH8L7pMdmL/IqszBcFeYLI/tDyagaXR X-Google-Smtp-Source: AGHT+IFODmfwX70NNIHnw3UunoToh1RubFYqPKcgPwM0cJdrseAn41wHH+CGTCPDjLhVDLe4lGCyzQ== X-Received: by 2002:a5d:5f08:0:b0:3a4:f70e:bc25 with SMTP id ffacd0b85a97d-3b495ccb8efmr3156051f8f.27.1751646381319; Fri, 04 Jul 2025 09:26:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 082/119] target/arm: Introduce pred_count_test Date: Fri, 4 Jul 2025 17:24:22 +0100 Message-ID: <20250704162501.249138-83-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704162501.249138-1-peter.maydell@linaro.org> References: <20250704162501.249138-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751646906933116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson For WHILE, we have the count of enabled predicates, so we don't need to search to compute the PredTest result. Reuse the logic that will shortly be required for counted predicates. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20250704142112.1018902-71-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sve_helper.c | 81 +++++++++++++++++++++---------------- 1 file changed, 46 insertions(+), 35 deletions(-) diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0e59ad22624..5b5871ba138 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -4102,30 +4102,46 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint3= 2_t pred_desc) return sum; } =20 +/* C.f. Arm pseudocode PredCountTest */ +static uint32_t pred_count_test(uint32_t elements, uint32_t count, bool in= vert) +{ + uint32_t flags; + + if (count =3D=3D 0) { + flags =3D 1; /* !N, Z, C */ + } else if (!invert) { + flags =3D (1u << 31) | 2; /* N, !Z */ + flags |=3D count !=3D elements; /* C */ + } else { + flags =3D 2; /* !Z, !C */ + flags |=3D (count =3D=3D elements) << 31; /* N */ + } + return flags; +} + uint32_t HELPER(sve_whilel)(void *vd, uint32_t count, uint32_t pred_desc) { intptr_t oprsz =3D FIELD_EX32(pred_desc, PREDDESC, OPRSZ); intptr_t esz =3D FIELD_EX32(pred_desc, PREDDESC, ESZ); uint64_t esz_mask =3D pred_esz_masks[esz]; ARMPredicateReg *d =3D vd; - uint32_t flags; - intptr_t i; + intptr_t i, oprbits =3D oprsz * 8; + + tcg_debug_assert(count <=3D oprbits); =20 /* Begin with a zero predicate register. */ - flags =3D do_zero(d, oprsz); - if (count =3D=3D 0) { - return flags; + do_zero(d, oprsz); + if (count) { + /* Set all of the requested bits. */ + for (i =3D 0; i < count / 64; ++i) { + d->p[i] =3D esz_mask; + } + if (count & 63) { + d->p[i] =3D MAKE_64BIT_MASK(0, count & 63) & esz_mask; + } } =20 - /* Set all of the requested bits. */ - for (i =3D 0; i < count / 64; ++i) { - d->p[i] =3D esz_mask; - } - if (count & 63) { - d->p[i] =3D MAKE_64BIT_MASK(0, count & 63) & esz_mask; - } - - return predtest_ones(d, oprsz, esz_mask); + return pred_count_test(oprbits, count, false); } =20 uint32_t HELPER(sve_whileg)(void *vd, uint32_t count, uint32_t pred_desc) @@ -4134,34 +4150,29 @@ uint32_t HELPER(sve_whileg)(void *vd, uint32_t coun= t, uint32_t pred_desc) intptr_t esz =3D FIELD_EX32(pred_desc, PREDDESC, ESZ); uint64_t esz_mask =3D pred_esz_masks[esz]; ARMPredicateReg *d =3D vd; - intptr_t i, invcount, oprbits; + intptr_t i, invcount, oprbits =3D oprsz * 8; uint64_t bits; =20 - if (count =3D=3D 0) { - return do_zero(d, oprsz); - } - - oprbits =3D oprsz * 8; tcg_debug_assert(count <=3D oprbits); =20 - bits =3D esz_mask; - if (oprbits & 63) { - bits &=3D MAKE_64BIT_MASK(0, oprbits & 63); - } - - invcount =3D oprbits - count; - for (i =3D (oprsz - 1) / 8; i > invcount / 64; --i) { - d->p[i] =3D bits; + /* Begin with a zero predicate register. */ + do_zero(d, oprsz); + if (count) { + /* Set all of the requested bits. */ bits =3D esz_mask; + if (oprbits & 63) { + bits &=3D MAKE_64BIT_MASK(0, oprbits & 63); + } + + invcount =3D oprbits - count; + for (i =3D (oprsz - 1) / 8; i > invcount / 64; --i) { + d->p[i] =3D bits; + bits =3D esz_mask; + } + d->p[i] =3D bits & MAKE_64BIT_MASK(invcount & 63, 64); } =20 - d->p[i] =3D bits & MAKE_64BIT_MASK(invcount & 63, 64); - - while (--i >=3D 0) { - d->p[i] =3D 0; - } - - return predtest_ones(d, oprsz, esz_mask); + return pred_count_test(oprbits, count, true); } =20 /* Recursive reduction on a function; --=20 2.43.0