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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b96534sm2816857f8f.48.2025.07.04.09.25.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:25:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751646336; x=1752251136; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TwjynpGV/1pTWOQilt3QgTNlLQPjzgarmUwDRRKoh/I=; b=beUvr+RSFwO7ofLPXyzecGTW9+w/rO6mosHCN6hXJKotUXYzvAWA3PQYPpnHQ0V+cK wBdReatGVlC5kqd7wcHckKw8UJNrQ0MYy5zNW1Uv8tn4hgQAczo9t+D8XHfkrI2m6Yfg egHNzZ6DjOXsjnVlIszqN4wJetX2pVSTXthzwP36Fj7nW7aFCh7IpPqEjF+WjE+a/DZf myRwyG/CIxPShXi4w8llIRrL1kH5eF1Aa39oo79DyCxvvF/TfRFmwNVOrI2c7YxUO/iN qM5B30MTsj/0vzpi/eLCTlZ5dvf5fnAgLJJU1byhjsQZJxkIXqi9WT9Sn+N7QrRMCI22 FBmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646336; x=1752251136; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TwjynpGV/1pTWOQilt3QgTNlLQPjzgarmUwDRRKoh/I=; b=hea4Mq7/RORX1FrkxG98+WwMjkewlMWfo9lHNeV4nLKoxFbW6jFkmHRU0OAHlnEFgs yOg0Ng1TeJJdc9PKbcP4eZ7rkZGcBKnwRz+o2l7r79mIpJV2zGdNQxfxI/gfTCNCJFfs 8F/vNRyVCCmvsORGJEjcorcf4xqJugOBhYtSe5rQXhGaqiPHsymrfSq+E4mO01ptrzcl AAwP1xzL4+jfP4sHXgDFRf90kMwI2/+tqj4G9L4EGX3KxoYq3A7IGUMSrayasDJqV6VP tXJVH0bR6gB4W5kDmD0J3Mtoo4js8VSsljVH/VOtApkVE159PKI2wNOR8lqqWCJbMXUi iZ/g== X-Gm-Message-State: AOJu0Ywj1P2v7QYhEbBh3/Ned+oNXJuZBDj8uqKXsM6PfQbUo01GTXKj fsL7npZy4gqRVdDCU2+KQqy3nJi1q82AACFxNNcX4r+7/HmW+stmKJYmaDlb5v5XY0XqaHrHQ/W qUcT0 X-Gm-Gg: ASbGncvoxDQeckWwKAe5tV+cfvHyVPs6nLn2Px3uW4ZrLtS+lI10iRMhVbMxQ4r/muD X/0Ib6JgUCZFm1VKpEMUaHre+Q9YKwPnN7C7lxMYKEB5pNZGUXkVjOsHkCRvIYC+NYE72LBUHtU GVd/XP7u52JPEYRhBRwd/4XdIA+IjDbh7pDEvpecgTekwXhgcR1golDNI/T14AhSsHjU4IsEjzZ Vzc+XcfJ10hNipf3Qxvd1cd5S8CAtg5wpm0T9Ttl+MAATfh03i4c9x390fG6G2ThQsbaMGxc+Dt RFwxcGv1Gk48EoK4ztDLKxAp09FNzQbT8BKekdtZ13ELIxBm086dWDabf0pZHvdtkNUF X-Google-Smtp-Source: AGHT+IGSEg9YO29PiRnAmJ1RGi/rWZIwZNdQ9lxd86TlfDC2Q6beUfnY+tTXoUlIILgjPoS3esuRxA== X-Received: by 2002:a05:6000:41fb:b0:3a4:d6ed:8e2e with SMTP id ffacd0b85a97d-3b49702e6camr2393803f8f.41.1751646336105; Fri, 04 Jul 2025 09:25:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 036/119] target/arm: Introduce ARMCPU.sme_max_vq Date: Fri, 4 Jul 2025 17:23:36 +0100 Message-ID: <20250704162501.249138-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704162501.249138-1-peter.maydell@linaro.org> References: <20250704162501.249138-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751646906993116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39a9234ff28..c8cf0ab417b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1136,6 +1136,7 @@ struct ArchCPU { =20 /* Used to set the maximum vector length the cpu will support. */ uint32_t sve_max_vq; + uint32_t sme_max_vq; =20 #ifdef CONFIG_USER_ONLY /* Used to set the default vector length at process start. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 77e7c4a6a52..bd33d6cc6ea 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -363,6 +363,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) } =20 cpu->sme_vq.map =3D vq_map; + cpu->sme_max_vq =3D 32 - clz32(vq_map); } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) --=20 2.43.0