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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b96534sm2816857f8f.48.2025.07.04.09.25.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751646324; x=1752251124; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rw2V7LRv7N3yBEu1EXHYSf8y/jFZBXV4IPLu7x+20gQ=; b=rvKj9vUr51dTW/FvE+zTOcUTnQrkwwPHMjMxmjZRVVHpiFGGCCMl6V3zziWH4YIgm7 ahZZAcD9VoN8Eh0Vl1DAK6ECvbTe3IQsjhbgjeQIwJ0wHiTDzPp49H8sEbDHSc4uzAYf pgJ3W06iWqVSoR68HKrbol4Ya6VqoBFI29mgzjIAqdCtOwCzLDiZAxzSc9rUZ8BY+Qez /qiEHePkTtnUGMmih/CF+9wHjMmE6ACuL31zJC9kQUxlHvse0oEmb/+ltP0AqG9KhwH0 J/IAv3rVRwdTferUECHM/0mCEvsxi6/pDnYiwf+22iH0eqbyANQtxfyVdcceNY2SeGkN Vs8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646324; x=1752251124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rw2V7LRv7N3yBEu1EXHYSf8y/jFZBXV4IPLu7x+20gQ=; b=gEuAVVHiS2vpvbvnSA9FMx4lB8rsh4w1ZFjmJmHA1v18rANrHmPEop3/yNqJ3jsRzP jwDEXFthsLGyfPAFfMRxmwGoJmxQPu6Y90nsxqli4NjY8akYlDINQVbiO12CXvU3B0IW 8w2xyf2gGhEPeA55baC1TFYgrYfzT1CtR402Y4g+siLJ+z+yfbkoGcFlRREDOreaHjkz BhS96WBM9DhU/0+snKPN6Lxfz9CiOnhRIR3Blt0dFdmymV4Rgdqw2a3fahIwEOZ8h83S fqBcigMMAEyDeU8ioiC8KKWKriqy1rDSgHuvrzHXyzWoiLKfdpwSWef4NckErQBkwNrq P95w== X-Gm-Message-State: AOJu0YzHQ2t9LdDyXda3ny2k9cb0QCZjzNMgCOA7dB6Fi7yVHYLVE7ND bq1SVme3CH4RWt8IQxnOuddMqy+UHLOyei+VZzaoQh1zUe0VJvIbsHONPbCWEHvR3bQsToXtSyg YFaaw X-Gm-Gg: ASbGnctF6CQMUZSVeYez9sBWIb9CQTHQyrRdLWx3fXEVwZviNYJIwTQ/06cahoQce6u jEdP6NhtRA8To1BkgZobwYwaEdvQ2QWDOcW6OLntxmsdUszOsEGwbs819lOoiQGKMgKHzu8a6Da 2/TdONwIf14M0sLFFQvsXBbcCF1kYf6u9tA/nPa7HR2gV/TZfYBBYCGYJaXkcYIX8DIsxk2se71 Id68MBReL1XJkfaxq1oNe12BCNyCcJOPtNsgmX+5BR+Hfy9If63bw0xKBWzPrWJtJDLojLi5/ux IXnmeofrp+9i/ZgqF/sn2mJxVPzW8rgjtsUByW0MvZ62vaNu/vDCn363DxsTmfm+2AuI X-Google-Smtp-Source: AGHT+IEBFrDZpH5OvyUYkiTNlzjXX6xep6fJt7cpQrZdpPxSiiJF0TVROBghkKCvp2Wg9IwrsmZ49A== X-Received: by 2002:a05:6000:22c6:b0:3a5:3a3b:6a3a with SMTP id ffacd0b85a97d-3b4970432aamr2244306f8f.54.1751646324221; Fri, 04 Jul 2025 09:25:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 023/119] target/arm: Introduce FPST_ZA, FPST_ZA_F16 Date: Fri, 4 Jul 2025 17:23:23 +0100 Message-ID: <20250704162501.249138-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704162501.249138-1-peter.maydell@linaro.org> References: <20250704162501.249138-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751647042833116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Rather than repeatedly copying FPST_FPCR to locals and setting default nan mode, create dedicated float_status. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 +++++++++++- target/arm/cpu.c | 4 ++++ target/arm/tcg/vfp_helper.c | 12 +++++++++++- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 96a49072665..2530aaca22c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -207,6 +207,8 @@ typedef struct NVICState NVICState; * when FPCR.AH =3D=3D 1 (bfloat16 conversions and multiplies, * and the reciprocal and square root estimate/step insns); * for half-precision + * ZA: the "streaming sve" fp status. + * ZA_F16: likewise for half-precision. * * Half-precision operations are governed by a separate * flush-to-zero control bit in FPSCR:FZ16. We pass a separate @@ -227,6 +229,12 @@ typedef struct NVICState NVICState; * they ignore FPCR.RMode. But they don't ignore FPCR.FZ16, * which means we need an FPST_AH_F16 as well. * + * The "ZA" float_status are for Streaming SVE operations which use + * default-NaN and do not generate fp exceptions, which means that they + * do not accumulate exception bits back into FPCR. + * See e.g. FPAdd vs FPAdd_ZA pseudocode functions, and the setting + * of fpcr.DN and fpexec parameters. + * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical * OR of the flags in the four fp statuses. This relies on the @@ -240,10 +248,12 @@ typedef enum ARMFPStatusFlavour { FPST_A64_F16, FPST_AH, FPST_AH_F16, + FPST_ZA, + FPST_ZA_F16, FPST_STD, FPST_STD_F16, } ARMFPStatusFlavour; -#define FPST_COUNT 8 +#define FPST_COUNT 10 =20 typedef struct CPUArchState { /* Regs for current mode. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ebac86f70d3..7b207f2620c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -554,11 +554,15 @@ static void arm_cpu_reset_hold(Object *obj, ResetType= type) set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]); set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]); + set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA]); + set_default_nan_mode(1, &env->vfp.fp_status[FPST_ZA_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]); set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]); diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index b1324c5c0a6..e156e3774ad 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -123,7 +123,7 @@ uint32_t vfp_get_fpsr_from_host(CPUARMState *env) a64_flags |=3D (get_float_exception_flags(&env->vfp.fp_status[FPST_A64= _F16]) & ~(float_flag_input_denormal_flushed | float_flag_input_denorma= l_used)); /* - * We do not merge in flags from FPST_AH or FPST_AH_F16, because + * We do not merge in flags from FPST_{AH,ZA} or FPST_{AH,ZA}_F16, bec= ause * they are used for insns that must not set the cumulative exception = bits. */ =20 @@ -196,6 +196,8 @@ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t va= l, uint32_t mask) set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_ZA]); + set_float_rounding_mode(i, &env->vfp.fp_status[FPST_ZA_F16]); } if (changed & FPCR_FZ16) { bool ftz_enabled =3D val & FPCR_FZ16; @@ -203,15 +205,18 @@ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t = val, uint32_t mask) set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA_F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32= _F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64= _F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD= _F16]); set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_= F16]); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA_= F16]); } if (changed & FPCR_FZ) { bool ftz_enabled =3D val & FPCR_FZ; set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]); + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA]); /* FIZ is A64 only so FZ always makes A32 code flush inputs to zer= o */ set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32= ]); } @@ -223,6 +228,7 @@ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t va= l, uint32_t mask) bool fitz_enabled =3D (val & FPCR_FIZ) || (val & (FPCR_FZ | FPCR_AH)) =3D=3D FPCR_FZ; set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A6= 4]); + set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_ZA= ]); } if (changed & FPCR_DN) { bool dnan_enabled =3D val & FPCR_DN; @@ -240,9 +246,13 @@ void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t v= al, uint32_t mask) /* Change behaviours for A64 FP operations */ arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); + arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); } else { arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16= ]); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); + arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]= ); } } /* --=20 2.43.0