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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b96534sm2816857f8f.48.2025.07.04.09.25.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 09:25:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751646321; x=1752251121; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZzBhsK295U+QrtJeMulwQMRMjYmffakd1q/LVwjhdAQ=; b=h2WMMofP5NjQYQHtGjeprZVljZ/zlbWWOmiR9J0q11OOcHC4c6Knd7XoRFsre6eAUJ 9rD/NBG52OyeiSz+LW/2+vQTSEXwDEdLnxfjzhlbQyBSioqQQFDYJN0OqcKKeDMYDQuj MG9tafh0nUO6dq/+wJ8ag8xPqD+7fY64it8Z/cMgaUfPpyZRaJ5VXqxtgcadg1wICJ4v jIzPYI3dTtmp4V1Fc0iOk+O1D2WnutElBjTMPPnoCBFeqLIFE8/IyHu4YTTBeybpBnjV XM9ef7iAw7gFW2N9XoYB0rmBxuK/vW1Fs9T7jioAJIUxkSU4AQcKe+yOdPjZty2Jas9a qb8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751646321; x=1752251121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZzBhsK295U+QrtJeMulwQMRMjYmffakd1q/LVwjhdAQ=; b=OEDk5ofJs6PHzIcNDND+rPGe+SEAbtG6jOsKwbjd0JGQBfk++XcUz1V8OfOP9DJ2gG L72G1gR0fKnLFKqfXUX0jKXfFszTAei5kEb9HyFu0ALn+HxLJZOqON52ueQBYyW7O0qN z3pfmj27o7SNolE9np2GIAaGaDUY3a9r00SRti/z7H0OQoeK5ZF41SoLLjGX6RF0OLJF BAfJCVnrc6gE0O4P3U8akwmubuaHBAuQ0WF7/HPkp7rJ+tGmPgKQEszB6MUpJensmn1P 1VU6izCFPm0Qu76KwYDpsYBNaIVCGrObnKOj0r4AyWP0oaHHARcLOl+3bWKW6blcCP04 GI8w== X-Gm-Message-State: AOJu0Yyfu+j6CLdKxdffgXQrusdfFqjQ404KPA+xA6OKX3t5dYNtDkoi fLl0hLY4Pw/wx+EgV/mgQyK5x3J6QmnISSwwy5SmQ8hrVvMsT2QCCGk/hI4pcgybGhso9+wGlMf mU/qs X-Gm-Gg: ASbGncvKdUdzU3WpCTbQjIFbUiCUfJ2NDQV2KOqetx3j08VVldeuedi0gt2ivo0bimg ypUgXpqnyVyQ1LOJ1fgZJy2EdrdkxdfkscNflccxtuFs5gjuYcAhuk/F3G4uWIcBp6AEEBX/eaG KjOdMjjlCTZzocWmkt0ta2jMdRRmt2hIkBMAWrfylnKZ6O+kCiKdaoNp7+Y4J52ZgPPeXJCvJ0F R54/Ey2M7mrZuZidliMoQ03sguJ17ghUsgHG8mE26lSM2RVfXJN2A47WsO3bli2T+pzl9EOFPjM 3RHFCvLfCRazH0P8vMztJkSR3mQTNMu/jwLQAYViAJ2KR/EOeQs8Dx+KqQWqts/T9sn5 X-Google-Smtp-Source: AGHT+IH19NFgdKVeWxiKF3q0+XaBnOQJ/99B0bkV6A+HVtTmeNSQZiKQeT1JK4HJok2PFFrxut498g== X-Received: by 2002:a05:600c:3b10:b0:441:a715:664a with SMTP id 5b1f17b1804b1-454b91597d9mr9365025e9.20.1751646321561; Fri, 04 Jul 2025 09:25:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 020/119] target/arm: Fix f16_dotadd vs nan selection Date: Fri, 4 Jul 2025 17:23:20 +0100 Message-ID: <20250704162501.249138-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250704162501.249138-1-peter.maydell@linaro.org> References: <20250704162501.249138-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751646520355116600 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Implement FPProcessNaNs4 within f16_dotadd, rather than simply letting NaNs propagate through the function. Cc: qemu-stable@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/sme_helper.c | 62 +++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index de0c6e54d4b..8f33387e4bd 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -1005,25 +1005,55 @@ static float32 f16_dotadd(float32 sum, uint32_t e1,= uint32_t e2, * - we have pre-set-up copy of s_std which is set to round-to-odd, * for the multiply (see below) */ - float64 e1r =3D float16_to_float64(e1 & 0xffff, true, s_f16); - float64 e1c =3D float16_to_float64(e1 >> 16, true, s_f16); - float64 e2r =3D float16_to_float64(e2 & 0xffff, true, s_f16); - float64 e2c =3D float16_to_float64(e2 >> 16, true, s_f16); - float64 t64; + float16 h1r =3D e1 & 0xffff; + float16 h1c =3D e1 >> 16; + float16 h2r =3D e2 & 0xffff; + float16 h2c =3D e2 >> 16; float32 t32; =20 - /* - * The ARM pseudocode function FPDot performs both multiplies - * and the add with a single rounding operation. Emulate this - * by performing the first multiply in round-to-odd, then doing - * the second multiply as fused multiply-add, and rounding to - * float32 all in one step. - */ - t64 =3D float64_mul(e1r, e2r, s_odd); - t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + /* C.f. FPProcessNaNs4 */ + if (float16_is_any_nan(h1r) || float16_is_any_nan(h1c) || + float16_is_any_nan(h2r) || float16_is_any_nan(h2c)) { + float16 t16; =20 - /* This conversion is exact, because we've already rounded. */ - t32 =3D float64_to_float32(t64, s_std); + if (float16_is_signaling_nan(h1r, s_f16)) { + t16 =3D h1r; + } else if (float16_is_signaling_nan(h1c, s_f16)) { + t16 =3D h1c; + } else if (float16_is_signaling_nan(h2r, s_f16)) { + t16 =3D h2r; + } else if (float16_is_signaling_nan(h2c, s_f16)) { + t16 =3D h2c; + } else if (float16_is_any_nan(h1r)) { + t16 =3D h1r; + } else if (float16_is_any_nan(h1c)) { + t16 =3D h1c; + } else if (float16_is_any_nan(h2r)) { + t16 =3D h2r; + } else { + t16 =3D h2c; + } + t32 =3D float16_to_float32(t16, true, s_f16); + } else { + float64 e1r =3D float16_to_float64(h1r, true, s_f16); + float64 e1c =3D float16_to_float64(h1c, true, s_f16); + float64 e2r =3D float16_to_float64(h2r, true, s_f16); + float64 e2c =3D float16_to_float64(h2c, true, s_f16); + float64 t64; + + /* + * The ARM pseudocode function FPDot performs both multiplies + * and the add with a single rounding operation. Emulate this + * by performing the first multiply in round-to-odd, then doing + * the second multiply as fused multiply-add, and rounding to + * float32 all in one step. + */ + t64 =3D float64_mul(e1r, e2r, s_odd); + t64 =3D float64r32_muladd(e1c, e2c, t64, 0, s_std); + + /* This conversion is exact, because we've already rounded. */ + t32 =3D float64_to_float32(t64, s_std); + } =20 /* The final accumulation step is not fused. */ return float32_add(sum, t32, s_std); --=20 2.43.0