Switched to a new branch '20250704162501.249138-1-peter.maydell@linaro.org' Applying: hw/arm/highbank: Mark the "highbank" and the "midway" machine as deprecated Applying: target/arm: Bring VLSTM/VLLDM helper store/load closer to the ARM pseudocode Applying: target/arm: Fix BLXNS helper store alignment checks Applying: target/arm: Fix function_return helper load alignment checks Applying: target/arm: Fix VLDR helper load alignment checks Applying: target/arm: Fix VSTR helper store alignment checks Applying: target/arm: Fix VLDR_SG helper load alignment checks Applying: target/arm: Fix VSTR_SG helper store alignment checks Applying: target/arm: Fix VLD4 helper load alignment checks Applying: target/arm: Fix VLD2 helper load alignment checks Applying: target/arm: Fix VST4 helper store alignment checks Applying: target/arm: Fix VST2 helper store alignment checks Applying: target/arm: Fix SME vs AdvSIMD exception priority Applying: target/arm: Fix sve_access_check for SME Applying: target/arm: Fix 128-bit element ZIP, UZP, TRN Applying: target/arm: Replace @rda_rn_rm_e0 in sve.decode Applying: target/arm: Fix FMMLA (64-bit element) for 128-bit VL Applying: target/arm: Disable FEAT_F64MM if maximum SVE vector size too small Applying: target/arm: Fix PSEL size operands to tcg_gen_gvec_ands Applying: target/arm: Fix f16_dotadd vs nan selection Applying: target/arm: Fix bfdotadd_ebf vs nan selection Applying: target/arm: Remove CPUARMState.vfp.scratch Applying: target/arm: Introduce FPST_ZA, FPST_ZA_F16 Applying: target/arm: Use FPST_ZA for sme_fmopa_[hsd] Applying: target/arm: Rename zarray to za_state.za Applying: target/arm: Add isar feature tests for SME2p1, SVE2p1 Applying: target/arm: Add ZT0 Applying: target/arm: Add zt0_excp_el to DisasContext Applying: target/arm: Implement SME2 ZERO ZT0 Applying: target/arm: Add alignment argument to gen_sve_{ldr, str} Applying: target/arm: Implement SME2 LDR/STR ZT0 Applying: target/arm: Implement SME2 MOVT Applying: target/arm: Split get_tile_rowcol argument tile_index Applying: target/arm: Rename MOVA for translate Applying: target/arm: Split out get_zarray Applying: target/arm: Introduce ARMCPU.sme_max_vq Applying: target/arm: Implement SME2 MOVA to/from tile, multiple registers Applying: target/arm: Implement SME2 MOVA to/from array, multiple registers Applying: target/arm: Implement SME2 BMOPA Applying: target/arm: Implement SME2 SMOPS, UMOPS (2-way) Applying: target/arm: Introduce gen_gvec_sve2_sqdmulh Applying: target/arm: Implement SME2 Multiple and Single SVE Destructive Applying: target/arm: Implement SME2 Multiple Vectors SVE Destructive Applying: target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector) Applying: target/arm: Implement SME2 ADD/SUB (array results, multiple vectors) Applying: target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s Applying: target/arm: Add helper_gvec{_ah}_bfmlsl{_nx} Applying: target/arm: Implement SME2 FMLAL, BFMLAL Applying: target/arm: Implement SME2 FDOT Applying: target/arm: Implement SME2 BFDOT Applying: target/arm: Implement SME2 FVDOT, BFVDOT Applying: target/arm: Rename helper_gvec_*dot_[bh] to *_4[bh] Applying: target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT Applying: target/arm: Rename SVE SDOT and UDOT patterns Applying: target/arm: Tighten USDOT (vectors) decode Applying: target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1 Applying: target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT Applying: target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL Applying: target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix Applying: target/arm: Implement SME2 FMLA, FMLS Applying: target/arm: Implement SME2 BFMLA, BFMLS Applying: target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB Applying: target/arm: Implement SME2 ADD/SUB (array accumulator) Applying: target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN Applying: target/arm: Implement SME2 FCVT (widening), FCVTL Applying: target/arm: Implement SME2 FCVTZS, FCVTZU Applying: target/arm: Implement SME2 SCVTF, UCVTF Applying: target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA Applying: target/arm: Introduce do_[us]sat_[bhs] macros Applying: target/arm: Use do_[us]sat_[bhs] in sve_helper.c Applying: target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU Applying: target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1 Applying: target/arm: Implement SME2 SUNPK, UUNPK Applying: target/arm: Implement SME2 ZIP, UZP (four registers) Applying: target/arm: Move do_urshr, do_srshr to vec_internal.h Applying: target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN Applying: target/arm: Implement SME2 ZIP, UZP (two registers) Applying: target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP Applying: target/arm: Enable SCLAMP, UCLAMP for SVE2p1 Applying: target/arm: Implement FCLAMP for SME2, SVE2p1 Applying: target/arm: Implement SME2p1 Multiple Zero Applying: target/arm: Introduce pred_count_test Applying: target/arm: Fold predtest_ones into helper_sve_brkns Applying: target/arm: Expand do_zero inline Applying: target/arm: Split out do_whilel from helper_sve_whilel Applying: target/arm: Split out do_whileg from helper_sve_whileg Applying: target/arm: Move scale by esz into helper_sve_while* Applying: target/arm: Split trans_WHILE to lt and gt Applying: target/arm: Enable PSEL for SVE2p1 Applying: target/arm: Implement SVE2p1 WHILE (predicate pair) Applying: target/arm: Implement SVE2p1 WHILE (predicate as counter) Applying: target/arm: Implement SVE2p1 PTRUE (predicate as counter) Applying: target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1 Applying: target/arm: Implement SVE2p1 PEXT Applying: target/arm: Implement SME2 SEL Applying: target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1 Applying: target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1 Applying: target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1 Applying: target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1 Applying: target/arm: Implement DUPQ for SME2p1/SVE2p1 Applying: target/arm: Implement EXTQ for SME2p1/SVE2p1 Applying: target/arm: Implement PMOV for SME2p1/SVE2p1 Applying: target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1 Applying: target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1 Applying: target/arm: Implement SME2 counted predicate register load/store Applying: target/arm: Split the ST_zpri and ST_zprr patterns Applying: target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1 Applying: target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h Applying: target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1 Applying: target/arm: Implement LD1Q, ST1Q for SVE2p1 Applying: target/arm: Implement MOVAZ for SME2p1 Applying: target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1 Applying: target/arm: Rename FMOPA_h to FMOPA_w_h Applying: target/arm: Rename BFMOPA to BFMOPA_w Applying: target/arm: Support FPCR.AH in SME FMOPS, BFMOPS Applying: target/arm: Implement FMOPA (non-widening) for fp16 Applying: target/arm: Implement SME2 BFMOPA (non-widening) Applying: target/arm: Enable FEAT_SME2p1 on -cpu max Applying: linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1 Warning: Permanently added 'github.com' (ED25519) to the list of known hosts. To github.com:patchew-project/qemu * [new tag] patchew/20250704162501.249138-1-peter.maydell@linaro.org -> patchew/20250704162501.249138-1-peter.maydell@linaro.org