From nobody Fri Dec 19 21:48:40 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751642157; cv=none; d=zohomail.com; s=zohoarc; b=ZmkCEucxmrLrdj7uZ+ziijtAC9J7fhMl4qPxUTSQkY5dij3bj2z3NEr4dsq3NsF7hqSCyZOQd5y0wxfY/wAEeXDeJZWtKKkhVu0ejLeG4iBvXxEMIEUprg4eG+qffkD1TmffWVicdrNZUZ23mKpjvqCZiAev9YLSor6ijhWtEm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751642157; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=Nq9rssmXj14uTOOAa1/pqUkLIM5u4uHRzInjz1kG7fI82GSPeozYUPWdUBQukCw3YBaPsyivAfsTYuBMxmPhHX+lSYUUdgL1Q483/atWY/BMFJ0X8AT2FQ/kOQp6krPwpcheBdYry26Ud0zdWVz3F6V5CFNodSSSfdXIktDxjW4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751642157781418.1195367088012; Fri, 4 Jul 2025 08:15:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uXi8E-000272-ME; Fri, 04 Jul 2025 11:15:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uXi87-0001zI-OJ for qemu-devel@nongnu.org; Fri, 04 Jul 2025 11:15:14 -0400 Received: from mail-qv1-xf36.google.com ([2607:f8b0:4864:20::f36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uXi85-0004cx-PG for qemu-devel@nongnu.org; Fri, 04 Jul 2025 11:15:11 -0400 Received: by mail-qv1-xf36.google.com with SMTP id 6a1803df08f44-702cbfe860cso4267856d6.1 for ; Fri, 04 Jul 2025 08:15:09 -0700 (PDT) Received: from gromero0.. ([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d6039fsm13658666d6.111.2025.07.04.08.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 08:15:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751642109; x=1752246909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=mIYuFd0tF+N4tEuCtIpQhHyLIJ/ZYWQyx3urdJDpaG+vIrMl/sGzWYn3zLngNm4lcY yoHHYJqtqdZKkeZ9tewrJl7cx+HTLLM99P8AQNhQixI3Z1z/fbG8zjBhKcdcv4/gSQeB mYMQw/fJH39hM3nTu2+vlIiEfCurDZBrwaI5UBJ2Ulk/B7Q7u+AalBgr+NwYWV9LHXQV JHlOVHipLT7gdOaRHkviPu+kr5OMkyXKq3BrC4BjZpZizm8/aTrrEGd5yt0/EtuG/HiQ sEE4IUSkD+Zs4TWhj1d4xr+xcES63TpnrU+69VoiDWU4jsS6MvynRyrIddvtG1F4hYwg dlsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751642109; x=1752246909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=Igwl4DkjQ2VPjOIjt2ilbwa2cEmCKf5IWMaxsXFsq3p0oweePxmpi2uhQpScd+rHYR +ljfwL/bEUFsnrBPxtnXY8MGxQkyB3V322Aqpw5d9GD3J2l4od+v+PljBfkHe0tUnc4a yRqc9dX8iU/RdXfzwVYKCPF7HDmFKKSo76vx/Rj0fCAsK3qJEbMfajLgD+Jp3Melw7V2 cHj8NyL+SXSTemmnRYIFCGTUkn1ExyOhTs8jOJ87XWjxK16yz/MawWZRZrOsC9mh9TEy +pPGsJ3b3O+i6rg2j7lASp8fBfO4GEXx6B6t+LVo3/dxDSMyPpEq6Joq/xtgmQGYGFwW XMKw== X-Gm-Message-State: AOJu0YwQTHjTJocT2h1oT/5rVQm4PJ1ilkka635Ufo8J44E9qBpUoXBc j87fi8HcbqowMQapQ5c7h8xYjt8fIiy1mmk+rdnjl0PXJ4TRNrAvRayBAyCcWVNGW8I= X-Gm-Gg: ASbGncvcPUYDEDMhhnLZdmfzxc3O69fN+l40XslygE14pqgfdc/7IcEt3Iyipifjsso 7W9TNimGcJwFEkN2WgHHSaVYCWBWKclNn2/irWbW8WTgxVti3bgEqHaLCDzG/dmWV1UTOSB9DjC mt7cVqbZyNliw7Qvzi4dZ3YWCaf6qRju8sJ18YgdipqVXtV7me4OZ5Xi17yB1GhDlogsuCW8/oD HRHX282jcYtqKWogjl+87jUxDTiRydTUvLtthuoWTM7ANjZnRs1ek/m/poDlC7zylu8Fus/ofrH HIMRJjgkTp5ArMgJWANIYgcrgJnj5qPopIiydLMQAtiz5XLEgITCqk21c0wV3RUnLp4= X-Google-Smtp-Source: AGHT+IHj77mXCr/eo8Y9pVElKQB6QlMeINThWHuNNEHwQi2m0hzBWii/jY6k/xnVh3sxR5m+fSPUHA== X-Received: by 2002:a05:6214:301a:b0:702:c150:46c2 with SMTP id 6a1803df08f44-702c6d33a2dmr42807526d6.10.1751642108469; Fri, 04 Jul 2025 08:15:08 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [WIP-for-10.1 v2 2/5] target/arm: Add FEAT_MEC registers Date: Fri, 4 Jul 2025 15:14:28 +0000 Message-Id: <20250704151431.1033520-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704151431.1033520-1-gustavo.romero@linaro.org> References: <20250704151431.1033520-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751642158785116600 Content-Type: text/plain; charset="utf-8" Add all FEAT_MEC registers. To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected. FEAT_MEC also requires two new cache management instructions, not included in this commit, that will be implemented in subsequent commits. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 14 +++++++ target/arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ce30ca857..9509217486 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -565,6 +565,16 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecidr_el2; + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -2389,6 +2399,10 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 +FIELD(MECIDR, MECIDW, 0, 4) +FIELD(MECID, MECID, 0, 16) +FIELD(VMECID, MECID, 0, 16) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 889d308807..9f8a284261 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6823,6 +6823,100 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static void mecidr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* MECIDWidthm1 =3D 15, i.e. 16 bits is the width of a MECID. */ + env->cp15.mecidr_el2 =3D FIELD_DP64(0, MECIDR, MECIDW, 15); +} + +static uint64_t mecidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + if (!arm_is_el2_enabled(env)) { + /* All bits are RES0. */ + return 0ULL; + } + + valid_mask =3D R_MECIDR_MECIDW_MASK; + return env->cp15.mecidr_el2 & valid_mask; +} + +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el; + + el =3D arm_current_el(env); + if (el =3D=3D 2 && !(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static uint64_t mecid_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + return raw_read(env, ri) & valid_mask; +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .resetfn =3D mecidr_reset, + .access =3D PL2_RW, .accessfn =3D mecid_access, .readfn =3D mecidr_r= ead, + .writefn =3D arm_cp_write_ignore, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecidr_el2) }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9008,6 +9102,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.34.1