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([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d6039fsm13658666d6.111.2025.07.04.08.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 08:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751642106; x=1752246906; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=cWIjx3S2POrzVWFa9dGbOP2QypTWNjAtygi7YorlrMijQVCT3kkQ8mRWtaAXfj12FZ dmpG1xDwOXxppj0+G8HcQeOELAIa5OyRPNpocTEndNYpantT8t5URCHrY5lU6jG6W9GM 2p3IkFmgCys3btypC42ubSDAaigxDZZezj51b+8yKOPfEW8nzzBzL9h9KBHIyJ/Mg20a EIRojsVybR/k1Y8Q/QwNVPT8ZFEs+SpnF6kHY1owNy72tManS3uW4/3FDh348bPwgl2M 8H49jL5d/ulh068F0FXjtPlgZE/86lFuZV1poXY3vRRM6/l9QcSAO/Hfic4uSIr8pohI SE1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751642106; x=1752246906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NElkJwQRf1CyYZ1pLfGMEkRff1YKnUUmnNhqdv4yZE4=; b=MH/iH0MheCdPbxElYMlUo/SCdJCWEJ3zpdpqC+gaXe5pkFHFogyJNlNNKSatXmahz3 Z29rut5HnTfX9qS8vSPglxN2ModozJeYDW5Wp95iYVk85ZE/VdpqHYrOqZsyTefqorF7 9g9p7UisOlyrQNieXQNndnw6XuO5kMdFdYoRjuiMwMnM3QcCm+6eG7Tp5F423M3TvjuD OLOZWxrgfIPabMVjFgKbhPr8P4OPtmcCjfg2eGh1mfTIHqb/WZ804WLv0zLxsAIe6E/e rukfzcAiWjF3MkaHsxVBUppo3C5Rabn/1I6jmML9+KIkKzLf4v2UIvLcTy9Tgrl2PNSo 4Z8Q== X-Gm-Message-State: AOJu0YxrA8N6QuZrEE14zGl7pX1cly+iiV3UhaGHH6oFmgNYgadCU5Nr 9c9uou/V7jYurIovmzDCelUv5oxeSzb3iyrwARwCInPWtm4QXtr88JWqR97RVE8LQY+fEcJSzzP 19mDR X-Gm-Gg: ASbGncuyLBO2NhL5OkiTm+jfQhqUtXXcd5rtb5K5vQzkNsaOJ1epSu+v/zsiVyBn+9S X0AaVIwnPXrhETOcvwHTNDR9QeC4FfBmgydgq3hhLsaXPiBkkKqBaOs+53P69bqxxNZYATN5d9a xMwJjbLZzC6U3wCPk/K+jIV/GMXMGAkBAA1hq1qqz1z927qeUjOd8mXG04yHBvOS67u6G0bdYWT FmlqSsCBgplJVAhLbe4yXzTwkjKbItJUgbQAtc01fZ53YC3WCfshEM0YCAaTdM156Xiir3ZpzNx 0ZKHafHXZbWxo2QBLwLr65pHMRQrofiHgFwDFpgfAPGuwAd8Ilgwv+xC6e9UafObKQA= X-Google-Smtp-Source: AGHT+IHbzxQh2U+33z2cIAXvHE/qRdlCtc7FLiLSRjUktLxqC4c4FdKRLsSj1Z5+AZRfY8CCcMrguw== X-Received: by 2002:a05:6214:1d0b:b0:6fa:d976:197e with SMTP id 6a1803df08f44-702c6d8c788mr38540696d6.33.1751642106295; Fri, 04 Jul 2025 08:15:06 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [WIP-for-10.1 v2 1/5] target/arm: Add the MECEn SCR_EL3 bit Date: Fri, 4 Jul 2025 15:14:27 +0000 Message-Id: <20250704151431.1033520-2-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704151431.1033520-1-gustavo.romero@linaro.org> References: <20250704151431.1033520-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751642223318116600 Content-Type: text/plain; charset="utf-8" The MECEn bit in SCR_EL3 enables access to the EL2 MECID registers from EL2, so add it to the SCR mask list to use it later on. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 302c24e232..8ce30ca857 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1683,6 +1683,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) =20 /* Return the current FPSCR value. */ --=20 2.34.1 From nobody Sat Dec 13 22:59:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751642157; cv=none; d=zohomail.com; s=zohoarc; b=ZmkCEucxmrLrdj7uZ+ziijtAC9J7fhMl4qPxUTSQkY5dij3bj2z3NEr4dsq3NsF7hqSCyZOQd5y0wxfY/wAEeXDeJZWtKKkhVu0ejLeG4iBvXxEMIEUprg4eG+qffkD1TmffWVicdrNZUZ23mKpjvqCZiAev9YLSor6ijhWtEm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1751642157; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=Nq9rssmXj14uTOOAa1/pqUkLIM5u4uHRzInjz1kG7fI82GSPeozYUPWdUBQukCw3YBaPsyivAfsTYuBMxmPhHX+lSYUUdgL1Q483/atWY/BMFJ0X8AT2FQ/kOQp6krPwpcheBdYry26Ud0zdWVz3F6V5CFNodSSSfdXIktDxjW4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1751642157781418.1195367088012; Fri, 4 Jul 2025 08:15:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uXi8E-000272-ME; Fri, 04 Jul 2025 11:15:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uXi87-0001zI-OJ for qemu-devel@nongnu.org; Fri, 04 Jul 2025 11:15:14 -0400 Received: from mail-qv1-xf36.google.com ([2607:f8b0:4864:20::f36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uXi85-0004cx-PG for qemu-devel@nongnu.org; Fri, 04 Jul 2025 11:15:11 -0400 Received: by mail-qv1-xf36.google.com with SMTP id 6a1803df08f44-702cbfe860cso4267856d6.1 for ; Fri, 04 Jul 2025 08:15:09 -0700 (PDT) Received: from gromero0.. ([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d6039fsm13658666d6.111.2025.07.04.08.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 08:15:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751642109; x=1752246909; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=mIYuFd0tF+N4tEuCtIpQhHyLIJ/ZYWQyx3urdJDpaG+vIrMl/sGzWYn3zLngNm4lcY yoHHYJqtqdZKkeZ9tewrJl7cx+HTLLM99P8AQNhQixI3Z1z/fbG8zjBhKcdcv4/gSQeB mYMQw/fJH39hM3nTu2+vlIiEfCurDZBrwaI5UBJ2Ulk/B7Q7u+AalBgr+NwYWV9LHXQV JHlOVHipLT7gdOaRHkviPu+kr5OMkyXKq3BrC4BjZpZizm8/aTrrEGd5yt0/EtuG/HiQ sEE4IUSkD+Zs4TWhj1d4xr+xcES63TpnrU+69VoiDWU4jsS6MvynRyrIddvtG1F4hYwg dlsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751642109; x=1752246909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I2pA8Kdl7I3oMXH8ei53t6GkTDaEspN8YWJLUEgwyNk=; b=Igwl4DkjQ2VPjOIjt2ilbwa2cEmCKf5IWMaxsXFsq3p0oweePxmpi2uhQpScd+rHYR +ljfwL/bEUFsnrBPxtnXY8MGxQkyB3V322Aqpw5d9GD3J2l4od+v+PljBfkHe0tUnc4a yRqc9dX8iU/RdXfzwVYKCPF7HDmFKKSo76vx/Rj0fCAsK3qJEbMfajLgD+Jp3Melw7V2 cHj8NyL+SXSTemmnRYIFCGTUkn1ExyOhTs8jOJ87XWjxK16yz/MawWZRZrOsC9mh9TEy +pPGsJ3b3O+i6rg2j7lASp8fBfO4GEXx6B6t+LVo3/dxDSMyPpEq6Joq/xtgmQGYGFwW XMKw== X-Gm-Message-State: AOJu0YwQTHjTJocT2h1oT/5rVQm4PJ1ilkka635Ufo8J44E9qBpUoXBc j87fi8HcbqowMQapQ5c7h8xYjt8fIiy1mmk+rdnjl0PXJ4TRNrAvRayBAyCcWVNGW8I= X-Gm-Gg: ASbGncvcPUYDEDMhhnLZdmfzxc3O69fN+l40XslygE14pqgfdc/7IcEt3Iyipifjsso 7W9TNimGcJwFEkN2WgHHSaVYCWBWKclNn2/irWbW8WTgxVti3bgEqHaLCDzG/dmWV1UTOSB9DjC mt7cVqbZyNliw7Qvzi4dZ3YWCaf6qRju8sJ18YgdipqVXtV7me4OZ5Xi17yB1GhDlogsuCW8/oD HRHX282jcYtqKWogjl+87jUxDTiRydTUvLtthuoWTM7ANjZnRs1ek/m/poDlC7zylu8Fus/ofrH HIMRJjgkTp5ArMgJWANIYgcrgJnj5qPopIiydLMQAtiz5XLEgITCqk21c0wV3RUnLp4= X-Google-Smtp-Source: AGHT+IHj77mXCr/eo8Y9pVElKQB6QlMeINThWHuNNEHwQi2m0hzBWii/jY6k/xnVh3sxR5m+fSPUHA== X-Received: by 2002:a05:6214:301a:b0:702:c150:46c2 with SMTP id 6a1803df08f44-702c6d33a2dmr42807526d6.10.1751642108469; Fri, 04 Jul 2025 08:15:08 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [WIP-for-10.1 v2 2/5] target/arm: Add FEAT_MEC registers Date: Fri, 4 Jul 2025 15:14:28 +0000 Message-Id: <20250704151431.1033520-3-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704151431.1033520-1-gustavo.romero@linaro.org> References: <20250704151431.1033520-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f36; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751642158785116600 Content-Type: text/plain; charset="utf-8" Add all FEAT_MEC registers. To work properly, FEAT_MEC also depends on FEAT_SCTLR2 and FEAT_TCR2, which are not implemented in this commit. The bits in SCTLR2 and TCR2 control which translation regimes use MECIDs, and determine which MECID is selected. FEAT_MEC also requires two new cache management instructions, not included in this commit, that will be implemented in subsequent commits. Signed-off-by: Gustavo Romero --- target/arm/cpu.h | 14 +++++++ target/arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ce30ca857..9509217486 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -565,6 +565,16 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + /* MEC registers */ + uint64_t mecidr_el2; + uint64_t mecid_p0_el2; + uint64_t mecid_a0_el2; + uint64_t mecid_p1_el2; + uint64_t mecid_a1_el2; + uint64_t mecid_rl_a_el3; + uint64_t vmecid_p_el2; + uint64_t vmecid_a_el2; } cp15; =20 struct { @@ -2389,6 +2399,10 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 +FIELD(MECIDR, MECIDW, 0, 4) +FIELD(MECID, MECID, 0, 16) +FIELD(VMECID, MECID, 0, 16) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 889d308807..9f8a284261 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6823,6 +6823,100 @@ static const ARMCPRegInfo nmi_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, }; =20 +static void mecidr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* MECIDWidthm1 =3D 15, i.e. 16 bits is the width of a MECID. */ + env->cp15.mecidr_el2 =3D FIELD_DP64(0, MECIDR, MECIDW, 15); +} + +static uint64_t mecidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + if (!arm_is_el2_enabled(env)) { + /* All bits are RES0. */ + return 0ULL; + } + + valid_mask =3D R_MECIDR_MECIDW_MASK; + return env->cp15.mecidr_el2 & valid_mask; +} + +static CPAccessResult mecid_access(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el; + + el =3D arm_current_el(env); + if (el =3D=3D 2 && !(env->cp15.scr_el3 & SCR_MECEN)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static void mecid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static uint64_t mecid_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t valid_mask; + + valid_mask =3D R_MECID_MECID_MASK; + return raw_read(env, ri) & valid_mask; +} + +static const ARMCPRegInfo mec_reginfo[] =3D { + { .name =3D "MECIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 7, .crn =3D 10, .crm =3D 8, + .resetfn =3D mecidr_reset, + .access =3D PL2_RW, .accessfn =3D mecid_access, .readfn =3D mecidr_r= ead, + .writefn =3D arm_cp_write_ignore, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecidr_el2) }, + { .name =3D "MECID_P0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p0_el2) }, + { .name =3D "MECID_A0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a0_el2) }, + { .name =3D "MECID_P1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_p1_el2) }, + { .name =3D "MECID_A1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 8, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_a1_el2) }, + { .name =3D "MECID_RL_A_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 1, .crn =3D 10, .crm =3D 10, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.mecid_rl_a_el3) }, + { .name =3D "VMECID_P_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 0, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_p_el2) }, + { .name =3D "VMECID_A_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 1, .crn =3D 10, .crm =3D 9, + .access =3D PL2_RW, .accessfn =3D mecid_access, + .readfn =3D mecid_read, .writefn =3D mecid_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmecid_a_el2) }, +}; + static void define_pmu_regs(ARMCPU *cpu) { /* @@ -9008,6 +9102,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_mec, cpu)) { + define_arm_cp_regs(cpu, mec_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.34.1 From nobody Sat Dec 13 22:59:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1751642213; cv=none; d=zohomail.com; s=zohoarc; b=kqWnDMV5lX0RGAF6iyNJ4wjQsZEKc/rkhqkvzAc5YVToqABDHVT7JUx9JiH223NRG5jV/Dqpe4dhysFYusquwpekVGAVCScUX9UwKVuuBD8AvftbXrE0Sq+f9oGClMOdehy5R+qeS9PO6Lqm3vymrC058yRaW9obBxLxi4P/kkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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These registers are extension of the SCTLR_ELx ones. Because the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, this commit only implements the EMEC bits related to FEAT_MEC in CTLR2_EL2 and SCTLR2_EL3. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 ++++ target/arm/cpu.h | 15 +++++++++++ target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + 5 files changed, 73 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 78c2fd2113..5a82c602f2 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4452e7c21e..a42d1133c2 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -296,6 +296,11 @@ static inline bool isar_feature_aa32_ats1e1(const ARMI= SARegisters *id) return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_mmfr3, ID_AA64MMFR3, SCTLRX) =3D=3D 1; +} + static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9509217486..ac38306873 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -326,6 +326,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1401,6 +1402,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8 /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1692,6 +1706,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 42) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9f8a284261..413672174b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7840,6 +7840,53 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_access(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (!cpu_isar_feature(aa64_sctlr2, env_archcpu(env))) { + return CP_ACCESS_UNDEFINED; + } + + if ((el < 3) && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +}; + +static void sctlr2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int el =3D arm_current_el(env); + uint64_t valid_mask =3D 0ULL; + + if (el > 1 && cpu_isar_feature(aa64_mec, env_archcpu(env))) { + /* SCTLR2_EL1 does not implement the EMEC bit */ + valid_mask |=3D SCTLR2_EMEC; + } + value &=3D valid_mask; + raw_write(env, ri, value); +}; + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_access, + .writefn =3D sctlr2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_access, + .writefn =3D sctlr2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .accessfn =3D sctlr2_access, + .writefn =3D sctlr2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9106,6 +9153,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mec_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5d8ed2794d..5f77d320ea 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1242,6 +1242,7 @@ void aarch64_max_tcg_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64mmfr3; t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ cpu->isar.id_aa64mmfr3 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; --=20 2.34.1 From nobody Sat Dec 13 22:59:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d6039fsm13658666d6.111.2025.07.04.08.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 08:15:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751642113; x=1752246913; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mp+FS8nNFswUhOtJAecxTCYZShRBLW2IyvTVb/fmyBo=; b=RuMTU4fQxadogE34xE8XNAoJsnXwZ6RKCEWswdv6ZI2M2H2hKFFfSRm1OJqEYJZrlg fuSwch+iK8RYhbSkLZpVqxfg945jhzO2JjM+a5Htq24R42LgU+SMHvlfwKe8/ssvMKRB iXAPt7eJAafb3qJ2WCJHJIwl0P1i0C63PcrWn0VfWzxLPSaLsNLEeGaRjELSA4tbvzTG v3Emc4vBZDnlqMD4KC+xOWZO595iBox+At7WzltXgH6WWh8avKEdOI7v7n/XPEzbkzE5 wWkRXzwbxP5/Voa2iF7YXOaJY0a8r+Bnj3WNNSHkBAK47DjLu/XY2HrL7TGvvh5nlIAT 3V/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751642113; x=1752246913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mp+FS8nNFswUhOtJAecxTCYZShRBLW2IyvTVb/fmyBo=; b=pa9SYtrfidE/8QfyWV9h6WGmOJLv5J3xT3se96QIpzhzK9mQpApdjOn2RBEOOw7GK5 wYodY7AAEB4ZYPyGlcg47VYXsiZHgp1LM20hZOuYPBXo4w4XTrzA8pwHEG6pXO7ftsgJ Lu5dGUmVehWsBa2OPTtjsl88zmf+wKv1btvm4k2Dgi+xDT1YXv3vErSNW7v5jb5rU2kP TxurmB6dDPt4b/ZZVRFFXzTQceD5w9o35EeEYv54lrWOiMl8C2SgsQgif3nT/QJiuWTC Gylw5Ud3uS2J8nWk8JnHNSN7AVgdwTrQtGL30Iy3LHd/fBDews8qmhLpay67nIFjLsNw P5dw== X-Gm-Message-State: AOJu0YzGSQ+JQLt7H5WYJAu5SxCka1QDqtEG+UvdOUE6yceLaVlk7vrC /auLPjHjr4frmtgALZy5Zn5kzLh5/VKqlwDNArIBsnzKpHp/4jtlb026v/v97tznzAw= X-Gm-Gg: ASbGncul0vdBWVX2gfbsnxW0DRdNvRuNLQoHHBcHMXxBpi4LXQCT/JNQ8h12q4FdUM5 klEPLL2pkkR88dQEbW/73P6z4MAosIfPBO0AdNFTk6gssuLCURJwVYa7kl43gf1xleaLwttg9jk ESwDX0JONdv6gnIrc38fMeF0tyfIVJrHSPqx7Xp8Oxd0DFAKTg4fg0zwpfAIRYds4EpjCb2dulY PIy63RBV5x1vnKoxu97Q4rStNWtiPQ23MI9VGYSydl5hKrMNR6t5nUzVZXPq73EccuLTe6xINn2 YEbtXCKCGmTpEL9ITlT1deWyZjEPcWIgT38nki4FrwHEDgCA+4RzS/KaT8hi0WigypVCajK7ILg 9ug== X-Google-Smtp-Source: AGHT+IGnPSYZa7NKK/KNBH2+GrMrOd8yqr+MDF3k1dQh6bc7B4U5EVpM8oPAZSh2FEpcPsy+qHCMTw== X-Received: by 2002:a05:6214:4993:b0:6fa:980d:52f with SMTP id 6a1803df08f44-702c8bcec02mr31874706d6.23.1751642112712; Fri, 04 Jul 2025 08:15:12 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [WIP-for-10.1 v2 4/5] target/arm: Add FEAT_TCR2 Date: Fri, 4 Jul 2025 15:14:30 +0000 Message-Id: <20250704151431.1033520-5-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704151431.1033520-1-gustavo.romero@linaro.org> References: <20250704151431.1033520-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f31; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751642172855116600 Content-Type: text/plain; charset="utf-8" Add FEAT_TCR2, which introduces TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Since the bits in these registers depend on other CPU features, and only FEAT_MEC is supported at the moment, the FEAT_TCR2 registers only implement the bits related to FEAT_MEC for now. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/cpu.h | 1 + target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++ target/arm/internals.h | 18 ++++++++++++++++ 5 files changed, 65 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 5a82c602f2..611d7385d8 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -143,6 +143,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage= 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage= 1) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index a42d1133c2..e6a731472f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -485,6 +485,11 @@ static inline bool isar_feature_aa64_xs(const ARMISARe= gisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) !=3D 0; } =20 +static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr3, ID_AA64MMFR3, TCRX) !=3D 0; +} + /* * These are the values from APA/API/APA3. * In general these must be compared '>=3D', per the normal Arm ARM diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ac38306873..6fd984a22f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -355,6 +355,7 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ uint64_t tcr_el[4]; + uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 413672174b..c34aa18ee3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7887,6 +7887,42 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 +static CPAccessResult tcr2_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + return CP_ACCESS_OK; +}; + +static void tcr2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int el =3D arm_current_el(env); + uint64_t valid_mask =3D 0ULL; + + valid_mask |=3D TCR2_AMEC0; + if (el_is_in_host(env, el)) { + if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + valid_mask |=3D TCR2_AMEC1; + } + } + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo tcr2_reginfo[] =3D { + { .name =3D "TCR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D tcr2_access, + .writefn =3D tcr2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, + { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D tcr2_access, + .writefn =3D tcr2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -9157,6 +9193,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, sctlr2_reginfo); } =20 + if (cpu_isar_feature(aa64_tcr2, cpu)) { + define_arm_cp_regs(cpu, tcr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/internals.h b/target/arm/internals.h index 3360de9150..a4886f9406 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -201,6 +201,24 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +#define TCR2_PNCH (1ULL << 0) +#define TCR2_PIE (1ULL << 1) +#define TCR2_E0POE (1ULL << 2) +#define TCR2_POE (1ULL << 3) +#define TCR2_AIE (1ULL << 4) +#define TCR2_D128 (1ULL << 5) +#define TCR2_PTTWI (1ULL << 10) +#define TCR2_HAFT (1ULL << 11) +#define TCR2_AMEC0 (1ULL << 12) +#define TCR2_AMEC1 (1ULL << 13) +#define TCR2_DISCH0 (1ULL << 14) +#define TCR2_DISCH1 (1ULL << 15) +#define TCR2_A2 (1ULL << 16) +#define TCR2_FNG0 (1ULL << 17) +#define TCR2_FNG1 (1ULL << 18) +#define TCR2_FNGNA0 (1ULL << 20) +#define TCR2_FNGNA1 (1ULL << 21) + FIELD(VTCR, T0SZ, 0, 6) FIELD(VTCR, SL0, 6, 2) FIELD(VTCR, IRGN0, 8, 2) --=20 2.34.1 From nobody Sat Dec 13 22:59:25 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([189.110.24.38]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-702c4d6039fsm13658666d6.111.2025.07.04.08.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jul 2025 08:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1751642115; x=1752246915; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EoLfxluEkOnqZWGvoYUYEDIuHb2S6wPjEZT0a5AA8Vs=; b=NUh6Yrr/wkU+J4IdYilovqUcnzFH39aa7NBzZ8P4S1n7CfhWCOGVYNYCtLrcCNYVuN wu7GcIQZkUGG3IBKHGIKbWaq2ek6vCjjP2KI67G0rnzUr7K/a7+rLUGltLd0A70mCaiP OdXbaAX9qunjjTJM0ltLtmYkKT+ILQa8XRZelJ0BCmiPFKsSM1vOk+yQ1J8Gpo7BrmPp L7erZVXzFQYUbeWOydJf7IcQI0wF4K2+RuA1jRLL+NYY/lYY4wWtc5eRJu3N5SMQ7FxA sMHDuROaXlT2BBRy3MmZYRb5Z5e4OI1t89qNx5N1THGisV217QZUMPRSpZG0DMSp4Gqh GkqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751642115; x=1752246915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EoLfxluEkOnqZWGvoYUYEDIuHb2S6wPjEZT0a5AA8Vs=; b=TRvtG8yngQBVGGJQ8KLQP3uTKCZd/J1Es5w8bHvfjtxL9qq95u64lAWZTelKklphNh sPFcbRPJohUA9YV82iIDCAzZHw1xGlgxS6pGbrI1DPwMupVFMf1v4xKAJ9g5O/P/BzKZ m7odFQZxW9C6ZGFwYuMU/zUqDQqBtpKODWFaLhSS1huoaqhmnauLFqHYDV437pZZnk1o xpulUQlQuj7Wvum9szHqTvP5hn6+R1XtW+pf5oWh8+ffFvvBFWcTKmIqA79VorrlTJFR 9Whn9k4lpaCQqRteIWTc876zFV4BVJCvM91rLQMMlVPKSW+rEKXkKvqcoknzTH7/kGBJ seQg== X-Gm-Message-State: AOJu0Ywp98l4RFVebcPQGtvtfniIcgBGjPronvAxPgYs13759VWPeRRZ uBpqNXi/55TK+x8N0e/ATV6jaM99kxjj6D5fZ6oV6Ikbmj1o2JaXQ87HNgq+1uPDxJ4= X-Gm-Gg: ASbGncuGNzrpObfRLB8jMPDpmphbKoUXu2vO5eKV8tXIoB0hMXQLAX8fbtyxe2hcofW rxLjeV7Tm8HTEhTTxjOtS6CiZaMeTDiAt2y3WYoCEyBZc0gcLVZ7sTwPdVma2MwGyhdPbFQeaI1 u8bRtFMSi6jCedZIhxykX1ZCq7N9uC7yjnkyb2eqdOArVjwmOBrVbK/13F4axUJ2Jj0SF3imNEP tOTlPZGGHoFowOee/ppASDBbnMemsjxxDwC6TpaUqDTRQXH2qZr+8shQBU+CPffTCEK4TrbNk0f gouH+xkKZ54Vg2nWCZs4y0K1V+9SsM0AocHhO/AgPW/3F4N+F572Khn2jpDbAkiRE8c6wR8jTpg oHQ== X-Google-Smtp-Source: AGHT+IGBKNTZQF8m01ia30/qAaj3rTGj3sv76gjBLyjix3w0Rk2Wqy1FdnzE/7UzPybfwIeFKAWw/g== X-Received: by 2002:a05:6214:3f92:b0:700:c717:493b with SMTP id 6a1803df08f44-702c8bc0f08mr36682916d6.25.1751642114783; Fri, 04 Jul 2025 08:15:14 -0700 (PDT) From: Gustavo Romero To: qemu-arm@nongnu.org, alex.bennee@linaro.org Cc: qemu-devel@nongnu.org, gustavo.romero@linaro.org Subject: [WIP-for-10.1 v2 5/5] target/arm: Advertise FEAT_MEC in cpu max Date: Fri, 4 Jul 2025 15:14:31 +0000 Message-Id: <20250704151431.1033520-6-gustavo.romero@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250704151431.1033520-1-gustavo.romero@linaro.org> References: <20250704151431.1033520-1-gustavo.romero@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=gustavo.romero@linaro.org; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1751642213212116600 Content-Type: text/plain; charset="utf-8" Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a first step to fully support FEAT_MEC. The FEAT_MEC is an extension to FEAT_RME that implements multiple Memory Encryption Contexts (MEC) so the memory in a realm can be encrypted and accessing it from the wrong encryption context is not possible. An encryption context allow the selection of a memory encryption engine. At this point, no real memory encryption or obfuscation is supported, but software stacks that rely on FEAT_MEC to run should work properly, except if they use the new cache management instructions, which will be implement in a subsequent commit. Signed-off-by: Gustavo Romero --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++++ target/arm/tcg/cpu64.c | 1 + 3 files changed, 7 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 611d7385d8..14f17febe2 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -89,6 +89,7 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MEC (Memory Encryption Contexts) - FEAT_MixedEnd (Mixed-endian support) - FEAT_MixedEndEL0 (Mixed-endian support at EL0) - FEAT_MOPS (Standardization of memory operations) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e6a731472f..009618fd9c 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -603,6 +603,11 @@ static inline bool isar_feature_aa64_hbc(const ARMISAR= egisters *id) return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; } =20 +static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr3, ID_AA64MMFR3, MEC); +} + static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5f77d320ea..1a127f6cf7 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1243,6 +1243,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr3; t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* FEAT_MEC */ cpu->isar.id_aa64mmfr3 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; --=20 2.34.1