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a="64576071" X-IronPort-AV: E=Sophos;i="6.16,287,1744095600"; d="scan'208";a="64576071" X-CSE-ConnectionGUID: yzU+YDRaQGOegLlQ0NeJsQ== X-CSE-MsgGUID: xTjXYT+5SWSPs5WymSOLVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,287,1744095600"; d="scan'208";a="185676903" From: Xiaoyao Li To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu , tao1.su@intel.com, chenyi.qiang@intel.com, xiaoyao.li@intel.com Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10 Date: Fri, 4 Jul 2025 22:45:04 +0800 Message-ID: <20250704144504.4094810-1-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.11; envelope-from=xiaoyao.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.218, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1751640914695116600 Content-Type: text/plain; charset="utf-8" Intel AVX10 spec has been updated to make the bit 16-18 of CPUID.24_0.EBX as reserved at 1 because all the Intel processors with AVX10 support will support all the vector lengths. The bits will be reserved at 1 to ensure the compatibility of the existing software. For QEMU, it makes no sense to allow the configurability of the bits anymore. So just remove the leaf FEAT_24_0_EBX and related stuff and hardcore the bits to all 1 when AVX10 is exposed to guest. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 36 +----------------------------------- target/i386/cpu.h | 12 ------------ 2 files changed, 1 insertion(+), 47 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0d35e95430fe..d0c4a3fa113c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -912,7 +912,6 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, #define TCG_SGX_12_0_EAX_FEATURES 0 #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 -#define TCG_24_0_EBX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1208,20 +1207,6 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_7_2_EDX_FEATURES, }, - [FEAT_24_0_EBX] =3D { - .type =3D CPUID_FEATURE_WORD, - .feat_names =3D { - [16] =3D "avx10-128", - [17] =3D "avx10-256", - [18] =3D "avx10-512", - }, - .cpuid =3D { - .eax =3D 0x24, - .needs_ecx =3D true, .ecx =3D 0, - .reg =3D R_EBX, - }, - .tcg_features =3D TCG_24_0_EBX_FEATURES, - }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1839,22 +1824,6 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, .to =3D { FEAT_SGX_12_1_EAX, ~0ull }, }, - { - .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, - .to =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, - }, - { - .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, - .to =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, - }, - { - .from =3D { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK= }, - .to =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, - }, - { - .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, - .to =3D { FEAT_24_0_EBX, ~0ull }, - }, }; =20 typedef struct X86RegisterInfo32 { @@ -4732,9 +4701,6 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { { "movdiri", "on" }, { "movdir64b", "on" }, { "avx10", "on" }, - { "avx10-128", "on" }, - { "avx10-256", "on" }, - { "avx10-512", "on" }, { "avx10-version", "1" }, { "stepping", "1" }, { /* end of list */ } @@ -7720,7 +7686,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx =3D 0; *edx =3D 0; if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count = =3D=3D 0) { - *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; + *ebx =3D (0x7U << 16) | env->avx10_version; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 51e10139dfdf..7856a882f014 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -671,7 +671,6 @@ typedef enum FeatureWord { FEAT_7_1_ECX, /* CPUID[EAX=3D7,ECX=3D1].ECX */ FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ - FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1037,17 +1036,6 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 -/* AVX10 128-bit vector support is present */ -#define CPUID_24_0_EBX_AVX10_128 (1U << 16) -/* AVX10 256-bit vector support is present */ -#define CPUID_24_0_EBX_AVX10_256 (1U << 17) -/* AVX10 512-bit vector support is present */ -#define CPUID_24_0_EBX_AVX10_512 (1U << 18) -/* AVX10 vector length support mask */ -#define CPUID_24_0_EBX_AVX10_VL_MASK (CPUID_24_0_EBX_AVX10_128 | \ - CPUID_24_0_EBX_AVX10_256 | \ - CPUID_24_0_EBX_AVX10_512) - /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) --=20 2.43.0